stm32f1xx_hal_dma.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_dma.h
00004   * @author  MCD Application Team
00005   * @version V1.0.4
00006   * @date    29-April-2016
00007   * @brief   Header file of DMA HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */ 
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_DMA_H
00040 #define __STM32F1xx_HAL_DMA_H
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048 
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052 
00053 /** @addtogroup DMA
00054   * @{
00055   */ 
00056 
00057 /* Exported types ------------------------------------------------------------*/
00058 
00059 /** @defgroup DMA_Exported_Types DMA Exported Types
00060   * @{
00061   */
00062    
00063 /** 
00064   * @brief  DMA Configuration Structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral, 
00069                                            from memory to memory or from peripheral to memory.
00070                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
00071 
00072   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
00073                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
00074                                
00075   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
00076                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
00077   
00078   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
00079                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
00080 
00081   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
00082                                            This parameter can be a value of @ref DMA_Memory_data_size */
00083                                
00084   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
00085                                            This parameter can be a value of @ref DMA_mode
00086                                            @note The circular buffer mode cannot be used if the memory-to-memory
00087                                                  data transfer is configured on the selected Channel */ 
00088 
00089   uint32_t Priority;                   /*!< Specifies the software priority for the DMAy Channelx.
00090                                             This parameter can be a value of @ref DMA_Priority_level */
00091 } DMA_InitTypeDef;
00092 
00093 /** 
00094   * @brief DMA Configuration enumeration values definition
00095   */  
00096 typedef enum 
00097 {
00098   DMA_MODE            = 0,      /*!< Control related DMA mode Parameter in DMA_InitTypeDef        */
00099   DMA_PRIORITY        = 1,      /*!< Control related priority level Parameter in DMA_InitTypeDef  */
00100   
00101 } DMA_ControlTypeDef;
00102 
00103 /**
00104   * @brief  HAL DMA State structures definition  
00105   */
00106 typedef enum
00107 {
00108   HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */
00109   HAL_DMA_STATE_READY             = 0x01,  /*!< DMA initialized and ready for use   */
00110   HAL_DMA_STATE_READY_HALF        = 0x11,  /*!< DMA Half process success            */
00111   HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */
00112   HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */
00113   HAL_DMA_STATE_ERROR             = 0x04,  /*!< DMA error state                     */
00114 }HAL_DMA_StateTypeDef;
00115 
00116 /** 
00117   * @brief  HAL DMA Error Code structure definition
00118   */
00119 typedef enum
00120 {
00121   HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
00122   HAL_DMA_HALF_TRANSFER      = 0x01,    /*!< Half Transfer     */
00123 }HAL_DMA_LevelCompleteTypeDef;
00124 
00125 /** 
00126   * @brief  DMA handle Structure definition
00127   */
00128 typedef struct __DMA_HandleTypeDef
00129 {
00130   DMA_Channel_TypeDef   *Instance;                       /*!< Register base address                  */
00131   
00132   DMA_InitTypeDef       Init;                            /*!< DMA communication parameters           */ 
00133   
00134   HAL_LockTypeDef       Lock;                            /*!< DMA locking object                     */  
00135   
00136   HAL_DMA_StateTypeDef  State;                           /*!< DMA transfer state                     */
00137   
00138   void                  *Parent;                                                      /*!< Parent object state                    */  
00139   
00140   void                  (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
00141   
00142   void                  (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
00143   
00144   void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
00145   
00146   __IO uint32_t         ErrorCode;                                                    /*!< DMA Error code                         */
00147 } DMA_HandleTypeDef;    
00148 /**
00149   * @}
00150   */
00151 
00152 /* Exported constants --------------------------------------------------------*/
00153 
00154 /** @defgroup DMA_Exported_Constants DMA Exported Constants
00155   * @{
00156   */
00157 
00158 /** @defgroup DMA_Error_Code DMA Error Code
00159   * @{
00160   */
00161  #define HAL_DMA_ERROR_NONE      ((uint32_t)0x00)    /*!< No error             */
00162  #define HAL_DMA_ERROR_TE        ((uint32_t)0x01)    /*!< Transfer error       */
00163  #define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x20)    /*!< Timeout error        */
00164 
00165 /**
00166   * @}
00167   */
00168 
00169 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
00170   * @{
00171   */ 
00172 #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)      /*!< Peripheral to memory direction */
00173 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)     /*!< Memory to peripheral direction */
00174 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
00175 
00176 /**
00177   * @}
00178   */
00179 
00180 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
00181   * @{
00182   */ 
00183 #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)   /*!< Peripheral increment mode Enable */
00184 #define DMA_PINC_DISABLE       ((uint32_t)0x00000000)     /*!< Peripheral increment mode Disable */
00185 /**
00186   * @}
00187   */ 
00188 
00189 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
00190   * @{
00191   */ 
00192 #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)   /*!< Memory increment mode Enable  */
00193 #define DMA_MINC_DISABLE        ((uint32_t)0x00000000)     /*!< Memory increment mode Disable */
00194 /**
00195   * @}
00196   */
00197 
00198 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
00199   * @{
00200   */ 
00201 #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Peripheral data alignment: Byte     */
00202 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)   /*!< Peripheral data alignment: HalfWord */
00203 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)   /*!< Peripheral data alignment: Word     */
00204 /**
00205   * @}
00206   */ 
00207 
00208 /** @defgroup DMA_Memory_data_size DMA Memory data size
00209   * @{ 
00210   */
00211 #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Memory data alignment: Byte     */
00212 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)   /*!< Memory data alignment: HalfWord */
00213 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)   /*!< Memory data alignment: Word     */
00214 /**
00215   * @}
00216   */
00217 
00218 /** @defgroup DMA_mode DMA mode
00219   * @{
00220   */ 
00221 #define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
00222 #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)     /*!< Circular mode                */
00223 /**
00224   * @}
00225   */
00226 
00227 /** @defgroup DMA_Priority_level DMA Priority level
00228   * @{
00229   */
00230 #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)     /*!< Priority level : Low       */
00231 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)   /*!< Priority level : Medium    */
00232 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)   /*!< Priority level : High      */
00233 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)     /*!< Priority level : Very_High */
00234 /**
00235   * @}
00236   */ 
00237 
00238 
00239 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
00240   * @{
00241   */
00242 #define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
00243 #define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
00244 #define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
00245 /**
00246   * @}
00247   */
00248 
00249 /** @defgroup DMA_flag_definitions DMA flag definitions
00250   * @{
00251   */ 
00252 #define DMA_FLAG_GL1                      ((uint32_t)0x00000001)
00253 #define DMA_FLAG_TC1                      ((uint32_t)0x00000002)
00254 #define DMA_FLAG_HT1                      ((uint32_t)0x00000004)
00255 #define DMA_FLAG_TE1                      ((uint32_t)0x00000008)
00256 #define DMA_FLAG_GL2                      ((uint32_t)0x00000010)
00257 #define DMA_FLAG_TC2                      ((uint32_t)0x00000020)
00258 #define DMA_FLAG_HT2                      ((uint32_t)0x00000040)
00259 #define DMA_FLAG_TE2                      ((uint32_t)0x00000080)
00260 #define DMA_FLAG_GL3                      ((uint32_t)0x00000100)
00261 #define DMA_FLAG_TC3                      ((uint32_t)0x00000200)
00262 #define DMA_FLAG_HT3                      ((uint32_t)0x00000400)
00263 #define DMA_FLAG_TE3                      ((uint32_t)0x00000800)
00264 #define DMA_FLAG_GL4                      ((uint32_t)0x00001000)
00265 #define DMA_FLAG_TC4                      ((uint32_t)0x00002000)
00266 #define DMA_FLAG_HT4                      ((uint32_t)0x00004000)
00267 #define DMA_FLAG_TE4                      ((uint32_t)0x00008000)
00268 #define DMA_FLAG_GL5                      ((uint32_t)0x00010000)
00269 #define DMA_FLAG_TC5                      ((uint32_t)0x00020000)
00270 #define DMA_FLAG_HT5                      ((uint32_t)0x00040000)
00271 #define DMA_FLAG_TE5                      ((uint32_t)0x00080000)
00272 #define DMA_FLAG_GL6                      ((uint32_t)0x00100000)
00273 #define DMA_FLAG_TC6                      ((uint32_t)0x00200000)
00274 #define DMA_FLAG_HT6                      ((uint32_t)0x00400000)
00275 #define DMA_FLAG_TE6                      ((uint32_t)0x00800000)
00276 #define DMA_FLAG_GL7                      ((uint32_t)0x01000000)
00277 #define DMA_FLAG_TC7                      ((uint32_t)0x02000000)
00278 #define DMA_FLAG_HT7                      ((uint32_t)0x04000000)
00279 #define DMA_FLAG_TE7                      ((uint32_t)0x08000000)
00280 /**
00281   * @}
00282   */
00283 
00284 /**
00285   * @}
00286   */
00287  
00288 
00289 /* Exported macro ------------------------------------------------------------*/
00290 /** @defgroup DMA_Exported_Macros DMA Exported Macros
00291   * @{
00292   */
00293 
00294 /** @brief  Reset DMA handle state
00295   * @param  __HANDLE__: DMA handle.
00296   * @retval None
00297   */
00298 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
00299 
00300 /**
00301   * @brief  Enable the specified DMA Channel.
00302   * @param  __HANDLE__: DMA handle
00303   * @retval None.
00304   */
00305 #define __HAL_DMA_ENABLE(__HANDLE__)        (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
00306 
00307 /**
00308   * @brief  Disable the specified DMA Channel.
00309   * @param  __HANDLE__: DMA handle
00310   * @retval None.
00311   */
00312 #define __HAL_DMA_DISABLE(__HANDLE__)       (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
00313 
00314 
00315 /* Interrupt & Flag management */
00316 
00317 /**
00318   * @brief  Enables the specified DMA Channel interrupts.
00319   * @param  __HANDLE__: DMA handle
00320   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
00321   *          This parameter can be any combination of the following values:
00322   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00323   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00324   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00325   * @retval None
00326   */
00327 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
00328 
00329 /**
00330   * @brief  Disables the specified DMA Channel interrupts.
00331   * @param  __HANDLE__: DMA handle
00332   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
00333   *          This parameter can be any combination of the following values:
00334   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00335   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00336   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00337   * @retval None
00338   */
00339 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
00340 
00341 /**
00342   * @brief  Checks whether the specified DMA Channel interrupt is enabled or disabled.
00343   * @param  __HANDLE__: DMA handle
00344   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
00345   *          This parameter can be one of the following values:
00346   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00347   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00348   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00349   * @retval The state of DMA_IT (SET or RESET).
00350   */
00351 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00352 
00353 /**
00354   * @brief  Returns the number of remaining data units in the current DMAy Channelx transfer.
00355   * @param  __HANDLE__: DMA handle
00356   *   
00357   * @retval The number of remaining data units in the current DMA Channel transfer.
00358   */
00359 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
00360 
00361 /**
00362   * @}
00363   */
00364 
00365 /* Include DMA HAL Extension module */
00366 #include "stm32f1xx_hal_dma_ex.h"   
00367 
00368 /* Exported functions --------------------------------------------------------*/
00369 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
00370   * @{
00371   */
00372 
00373 /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions 
00374   * @{
00375   */
00376 /* Initialization and de-initialization functions *****************************/
00377 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
00378 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
00379 /**
00380   * @}
00381   */
00382 
00383 /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions 
00384   * @{
00385   */
00386 /* IO operation functions *****************************************************/
00387 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00388 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00389 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
00390 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
00391 void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
00392 /**
00393   * @}
00394   */
00395 
00396 /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
00397   * @{
00398   */
00399 /* Peripheral State and Error functions ***************************************/
00400 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
00401 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
00402 /**
00403   * @}
00404   */
00405 
00406 /**
00407   * @}
00408   */
00409 
00410 /* Private Constants -------------------------------------------------------------*/
00411 /** @defgroup DMA_Private_Constants DMA Private Constants
00412   * @brief    DMA private defines and constants 
00413   * @{
00414   */
00415 /**
00416   * @}
00417   */ 
00418 
00419 /* Private macros ------------------------------------------------------------*/
00420 /** @defgroup DMA_Private_Macros DMA Private Macros
00421   * @brief    DMA private macros 
00422   * @{
00423   */
00424 
00425 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
00426 
00427 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
00428                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
00429                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 
00430 
00431 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
00432                                             ((STATE) == DMA_PINC_DISABLE))
00433 
00434 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
00435                                         ((STATE) == DMA_MINC_DISABLE))
00436 
00437 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
00438                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
00439                                            ((SIZE) == DMA_PDATAALIGN_WORD))
00440 
00441 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
00442                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
00443                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
00444 
00445 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
00446                            ((MODE) == DMA_CIRCULAR)) 
00447 
00448 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
00449                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
00450                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
00451                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 
00452 
00453 /**
00454   * @}
00455   */ 
00456 
00457 /* Private functions ---------------------------------------------------------*/
00458 /** @defgroup DMA_Private_Functions DMA Private Functions
00459   * @brief    DMA private  functions 
00460   * @{
00461   */
00462 /**
00463   * @}
00464   */
00465 
00466 /**
00467   * @}
00468   */ 
00469 
00470 /**
00471   * @}
00472   */
00473 
00474 #ifdef __cplusplus
00475 }
00476 #endif
00477 
00478 #endif /* __STM32F1xx_HAL_DMA_H */
00479 
00480 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/