stm32f1xx_hal_cortex.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_cortex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.4
00006   * @date    29-April-2016
00007   * @brief   Header file of CORTEX HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */ 
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_CORTEX_H
00040 #define __STM32F1xx_HAL_CORTEX_H
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048 
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052 
00053 /** @addtogroup CORTEX
00054   * @{
00055   */ 
00056 /* Exported types ------------------------------------------------------------*/
00057 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
00058   * @{
00059   */
00060 
00061 #if (__MPU_PRESENT == 1)
00062 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
00063   * @brief  MPU Region initialization structure 
00064   * @{
00065   */
00066 typedef struct
00067 {
00068   uint8_t                Enable;                /*!< Specifies the status of the region. 
00069                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
00070   uint8_t                Number;                /*!< Specifies the number of the region to protect. 
00071                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
00072   uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
00073   uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
00074                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
00075   uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
00076                                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */         
00077   uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
00078                                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                 
00079   uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
00080                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
00081   uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
00082                                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
00083   uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
00084                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
00085   uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
00086                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
00087   uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
00088                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
00089 }MPU_Region_InitTypeDef;
00090 /**
00091   * @}
00092   */
00093 #endif /* __MPU_PRESENT */
00094 
00095 /**
00096   * @}
00097   */
00098 
00099 /* Exported constants --------------------------------------------------------*/
00100 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
00101   * @{
00102   */
00103 
00104 
00105 /** @defgroup CORTEX_Preemption_Priority_Group  CORTEX Preemption Priority Group 
00106   * @{
00107   */
00108 
00109 #define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
00110                                                                  4 bits for subpriority */
00111 #define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
00112                                                                  3 bits for subpriority */
00113 #define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
00114                                                                  2 bits for subpriority */
00115 #define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
00116                                                                  1 bits for subpriority */
00117 #define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
00118                                                                  0 bits for subpriority */
00119 /**
00120   * @}
00121   */
00122 
00123 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
00124   * @{
00125   */
00126 #define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
00127 #define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
00128 
00129 /**
00130   * @}
00131   */
00132 
00133 #if (__MPU_PRESENT == 1)
00134 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
00135   * @{
00136   */
00137 #define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)  
00138 #define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
00139 #define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
00140 #define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
00141 /**
00142   * @}
00143   */
00144 
00145 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
00146   * @{
00147   */
00148 #define  MPU_REGION_ENABLE     ((uint8_t)0x01)
00149 #define  MPU_REGION_DISABLE    ((uint8_t)0x00)
00150 /**
00151   * @}
00152   */
00153 
00154 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
00155   * @{
00156   */
00157 #define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
00158 #define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
00159 /**
00160   * @}
00161   */
00162 
00163 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
00164   * @{
00165   */
00166 #define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
00167 #define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
00168 /**
00169   * @}
00170   */
00171 
00172 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
00173   * @{
00174   */
00175 #define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
00176 #define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
00177 /**
00178   * @}
00179   */
00180 
00181 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
00182   * @{
00183   */
00184 #define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
00185 #define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
00186 /**
00187   * @}
00188   */
00189 
00190 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
00191   * @{
00192   */
00193 #define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
00194 #define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
00195 #define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
00196 /**
00197   * @}
00198   */
00199 
00200 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
00201   * @{
00202   */
00203 #define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
00204 #define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
00205 #define   MPU_REGION_SIZE_128B     ((uint8_t)0x06) 
00206 #define   MPU_REGION_SIZE_256B     ((uint8_t)0x07) 
00207 #define   MPU_REGION_SIZE_512B     ((uint8_t)0x08) 
00208 #define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)  
00209 #define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
00210 #define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B) 
00211 #define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C) 
00212 #define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D) 
00213 #define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E) 
00214 #define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F) 
00215 #define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
00216 #define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
00217 #define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
00218 #define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13) 
00219 #define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14) 
00220 #define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15) 
00221 #define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16) 
00222 #define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
00223 #define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
00224 #define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
00225 #define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
00226 #define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
00227 #define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
00228 #define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D) 
00229 #define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E) 
00230 #define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
00231 /**                                
00232   * @}
00233   */
00234    
00235 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
00236   * @{
00237   */
00238 #define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)  
00239 #define  MPU_REGION_PRIV_RW        ((uint8_t)0x01) 
00240 #define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)  
00241 #define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)  
00242 #define  MPU_REGION_PRIV_RO        ((uint8_t)0x05) 
00243 #define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
00244 /**
00245   * @}
00246   */
00247 
00248 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
00249   * @{
00250   */
00251 #define  MPU_REGION_NUMBER0    ((uint8_t)0x00)  
00252 #define  MPU_REGION_NUMBER1    ((uint8_t)0x01) 
00253 #define  MPU_REGION_NUMBER2    ((uint8_t)0x02)  
00254 #define  MPU_REGION_NUMBER3    ((uint8_t)0x03)  
00255 #define  MPU_REGION_NUMBER4    ((uint8_t)0x04) 
00256 #define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
00257 #define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
00258 #define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
00259 /**
00260   * @}
00261   */
00262 #endif /* __MPU_PRESENT */
00263 
00264 /**
00265   * @}
00266   */
00267   
00268 
00269 /* Private macro -------------------------------------------------------------*/
00270 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
00271   * @{
00272   */  
00273 
00274 /** @defgroup CORTEX_Preemption_Priority_Group_Macro  CORTEX Preemption Priority Group 
00275   * @{
00276   */
00277 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
00278                                        ((GROUP) == NVIC_PRIORITYGROUP_1) || \
00279                                        ((GROUP) == NVIC_PRIORITYGROUP_2) || \
00280                                        ((GROUP) == NVIC_PRIORITYGROUP_3) || \
00281                                        ((GROUP) == NVIC_PRIORITYGROUP_4))
00282 
00283 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
00284  
00285 #define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
00286 
00287 #define IS_NVIC_DEVICE_IRQ(IRQ)  ((IRQ) >= 0x00)
00288 
00289 /**
00290   * @}
00291   */
00292 
00293 /** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
00294   * @{
00295   */                       
00296 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
00297                                        ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
00298 /**
00299   * @}
00300   */
00301 #if (__MPU_PRESENT == 1)
00302 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
00303                                      ((STATE) == MPU_REGION_DISABLE))
00304 
00305 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
00306                                           ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
00307 
00308 #define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
00309                                           ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
00310 
00311 #define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
00312                                           ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
00313 
00314 #define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
00315                                           ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
00316 
00317 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
00318                                 ((TYPE) == MPU_TEX_LEVEL1)  || \
00319                                 ((TYPE) == MPU_TEX_LEVEL2))
00320 
00321 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
00322                                                   ((TYPE) == MPU_REGION_PRIV_RW)     || \
00323                                                   ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
00324                                                   ((TYPE) == MPU_REGION_FULL_ACCESS) || \
00325                                                   ((TYPE) == MPU_REGION_PRIV_RO)     || \
00326                                                   ((TYPE) == MPU_REGION_PRIV_RO_URO))
00327 
00328 #define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
00329                                          ((NUMBER) == MPU_REGION_NUMBER1) || \
00330                                          ((NUMBER) == MPU_REGION_NUMBER2) || \
00331                                          ((NUMBER) == MPU_REGION_NUMBER3) || \
00332                                          ((NUMBER) == MPU_REGION_NUMBER4) || \
00333                                          ((NUMBER) == MPU_REGION_NUMBER5) || \
00334                                          ((NUMBER) == MPU_REGION_NUMBER6) || \
00335                                          ((NUMBER) == MPU_REGION_NUMBER7))
00336 
00337 #define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
00338                                      ((SIZE) == MPU_REGION_SIZE_64B)   || \
00339                                      ((SIZE) == MPU_REGION_SIZE_128B)  || \
00340                                      ((SIZE) == MPU_REGION_SIZE_256B)  || \
00341                                      ((SIZE) == MPU_REGION_SIZE_512B)  || \
00342                                      ((SIZE) == MPU_REGION_SIZE_1KB)   || \
00343                                      ((SIZE) == MPU_REGION_SIZE_2KB)   || \
00344                                      ((SIZE) == MPU_REGION_SIZE_4KB)   || \
00345                                      ((SIZE) == MPU_REGION_SIZE_8KB)   || \
00346                                      ((SIZE) == MPU_REGION_SIZE_16KB)  || \
00347                                      ((SIZE) == MPU_REGION_SIZE_32KB)  || \
00348                                      ((SIZE) == MPU_REGION_SIZE_64KB)  || \
00349                                      ((SIZE) == MPU_REGION_SIZE_128KB) || \
00350                                      ((SIZE) == MPU_REGION_SIZE_256KB) || \
00351                                      ((SIZE) == MPU_REGION_SIZE_512KB) || \
00352                                      ((SIZE) == MPU_REGION_SIZE_1MB)   || \
00353                                      ((SIZE) == MPU_REGION_SIZE_2MB)   || \
00354                                      ((SIZE) == MPU_REGION_SIZE_4MB)   || \
00355                                      ((SIZE) == MPU_REGION_SIZE_8MB)   || \
00356                                      ((SIZE) == MPU_REGION_SIZE_16MB)  || \
00357                                      ((SIZE) == MPU_REGION_SIZE_32MB)  || \
00358                                      ((SIZE) == MPU_REGION_SIZE_64MB)  || \
00359                                      ((SIZE) == MPU_REGION_SIZE_128MB) || \
00360                                      ((SIZE) == MPU_REGION_SIZE_256MB) || \
00361                                      ((SIZE) == MPU_REGION_SIZE_512MB) || \
00362                                      ((SIZE) == MPU_REGION_SIZE_1GB)   || \
00363                                      ((SIZE) == MPU_REGION_SIZE_2GB)   || \
00364                                      ((SIZE) == MPU_REGION_SIZE_4GB))
00365 
00366 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
00367 #endif /* __MPU_PRESENT */
00368 
00369 /**
00370   * @}
00371   */
00372 
00373 /* Exported functions --------------------------------------------------------*/
00374 /** @addtogroup CORTEX_Exported_Functions
00375   * @{
00376   */
00377 
00378 /** @addtogroup CORTEX_Exported_Functions_Group1
00379   * @{
00380   */  
00381 /* Initialization and de-initialization functions *****************************/
00382 void     HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
00383 void     HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
00384 void     HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
00385 void     HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
00386 void     HAL_NVIC_SystemReset(void);
00387 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
00388 /**
00389   * @}
00390   */
00391 
00392 /** @addtogroup CORTEX_Exported_Functions_Group2
00393   * @{
00394   */ 
00395 /* Peripheral Control functions ***********************************************/
00396 #if (__MPU_PRESENT == 1)
00397 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
00398 #endif /* __MPU_PRESENT */
00399 uint32_t HAL_NVIC_GetPriorityGrouping(void);
00400 void     HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
00401 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
00402 void     HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
00403 void     HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
00404 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
00405 void     HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
00406 void     HAL_SYSTICK_IRQHandler(void);
00407 void     HAL_SYSTICK_Callback(void);
00408 /**
00409   * @}
00410   */
00411 
00412 /**
00413   * @}
00414   */
00415                                                                                
00416 /* Private functions ---------------------------------------------------------*/   
00417 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
00418   * @brief    CORTEX private  functions 
00419   * @{
00420   */
00421 
00422 #if (__MPU_PRESENT == 1)
00423 /**
00424   * @brief  Disables the MPU
00425   * @retval None
00426   */
00427 __STATIC_INLINE void HAL_MPU_Disable(void)
00428 {
00429   /* Disable fault exceptions */
00430   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
00431   
00432   /* Disable the MPU */
00433   MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
00434 }
00435 
00436 /**
00437   * @brief  Enables the MPU
00438   * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, 
00439   *          NMI, FAULTMASK and privileged accessto the default memory 
00440   *          This parameter can be one of the following values:
00441   *            @arg MPU_HFNMI_PRIVDEF_NONE
00442   *            @arg MPU_HARDFAULT_NMI
00443   *            @arg MPU_PRIVILEGED_DEFAULT
00444   *            @arg MPU_HFNMI_PRIVDEF
00445   * @retval None
00446   */
00447 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
00448 {
00449   /* Enable the MPU */
00450   MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
00451   
00452   /* Enable fault exceptions */
00453   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
00454 }
00455 #endif /* __MPU_PRESENT */
00456 
00457 /**
00458   * @}
00459   */
00460 
00461 /**
00462   * @}
00463   */ 
00464 
00465 /**
00466   * @}
00467   */
00468   
00469 #ifdef __cplusplus
00470 }
00471 #endif
00472 
00473 #endif /* __STM32F1xx_HAL_CORTEX_H */
00474  
00475 
00476 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/