stm32_hal_legacy.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32_hal_legacy.h
00004   * @author  MCD Application Team
00005   * @version V1.0.4
00006   * @date    29-April-2016
00007   * @brief   This file contains aliases definition for the STM32Cube HAL constants 
00008   *          macros and functions maintained for legacy purpose.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00013   *
00014   * Redistribution and use in source and binary forms, with or without modification,
00015   * are permitted provided that the following conditions are met:
00016   *   1. Redistributions of source code must retain the above copyright notice,
00017   *      this list of conditions and the following disclaimer.
00018   *   2. Redistributions in binary form must reproduce the above copyright notice,
00019   *      this list of conditions and the following disclaimer in the documentation
00020   *      and/or other materials provided with the distribution.
00021   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00022   *      may be used to endorse or promote products derived from this software
00023   *      without specific prior written permission.
00024   *
00025   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00026   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00027   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00028   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00029   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00030   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00031   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00032   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00033   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00034   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00035   *
00036   ******************************************************************************
00037   */
00038 
00039 /* Define to prevent recursive inclusion -------------------------------------*/
00040 #ifndef __STM32_HAL_LEGACY
00041 #define __STM32_HAL_LEGACY
00042 
00043 #ifdef __cplusplus
00044  extern "C" {
00045 #endif
00046 
00047 /* Includes ------------------------------------------------------------------*/
00048 /* Exported types ------------------------------------------------------------*/
00049 /* Exported constants --------------------------------------------------------*/
00050 
00051 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
00052   * @{
00053   */
00054 #define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
00055 #define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
00056 #define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
00057 #define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
00058 #define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
00059 
00060 /**
00061   * @}
00062   */
00063   
00064 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
00065   * @{
00066   */
00067 #define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
00068 #define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
00069 #define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
00070 #define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
00071 #define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
00072 #define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
00073 #define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
00074 #define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
00075 #define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
00076 #define REGULAR_GROUP                   ADC_REGULAR_GROUP
00077 #define INJECTED_GROUP                  ADC_INJECTED_GROUP
00078 #define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
00079 #define AWD_EVENT                       ADC_AWD_EVENT
00080 #define AWD1_EVENT                      ADC_AWD1_EVENT
00081 #define AWD2_EVENT                      ADC_AWD2_EVENT
00082 #define AWD3_EVENT                      ADC_AWD3_EVENT
00083 #define OVR_EVENT                       ADC_OVR_EVENT
00084 #define JQOVF_EVENT                     ADC_JQOVF_EVENT
00085 #define ALL_CHANNELS                    ADC_ALL_CHANNELS
00086 #define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
00087 #define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
00088 #define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
00089 #define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
00090 #define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
00091 #define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
00092 #define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
00093 #define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
00094 #define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
00095 #define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO 
00096 #define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2 
00097 #define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO 
00098 #define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4  
00099 #define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
00100 #define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
00101 #define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
00102 #define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
00103 #define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
00104 #define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
00105 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
00106 #define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
00107 
00108 #define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
00109 #define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
00110 #define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
00111 #define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
00112 #define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
00113 #define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
00114 #define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1 
00115 /**
00116   * @}
00117   */
00118   
00119 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
00120   * @{
00121   */ 
00122   
00123 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 
00124 
00125 /**
00126   * @}
00127   */   
00128    
00129 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
00130   * @{
00131   */
00132 #define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
00133 #define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
00134 #define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
00135 #define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
00136 #define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
00137 #define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
00138 #define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
00139 #define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
00140 #define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
00141 #define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
00142 #if defined(STM32F373xC) || defined(STM32F378xx)
00143 #define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
00144 #define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
00145 #endif /* STM32F373xC || STM32F378xx */
00146 
00147 #if defined(STM32L0) || defined(STM32L4)
00148 #define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
00149 
00150 #define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
00151 #define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
00152 #define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
00153  
00154 #define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
00155 #define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
00156 #define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
00157 #define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
00158 #define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
00159 #define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
00160 #define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
00161 #define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
00162 #define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
00163 #define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
00164 #define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
00165 #define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
00166 #define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
00167 
00168 #define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
00169 #define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
00170 
00171 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
00172 /*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
00173 #if defined(COMP_CSR_LOCK)
00174 #define COMP_FLAG_LOCK                 COMP_CSR_LOCK
00175 #elif defined(COMP_CSR_COMP1LOCK)
00176 #define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
00177 #elif defined(COMP_CSR_COMPxLOCK)
00178 #define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
00179 #endif
00180 
00181 #if defined(STM32L4)
00182 #define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
00183 #define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
00184 #define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
00185 #define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
00186 #define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
00187 #define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
00188 #define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
00189 #endif
00190 
00191 #if defined(STM32L0)
00192 #define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
00193 #define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
00194 #else
00195 #define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
00196 #define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
00197 #define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
00198 #define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
00199 #endif
00200 
00201 #endif
00202 /**
00203   * @}
00204   */
00205 
00206 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
00207   * @{
00208   */
00209 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
00210 /**
00211   * @}
00212   */
00213 
00214 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
00215   * @{
00216   */
00217   
00218 #define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
00219 #define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
00220 
00221 /**
00222   * @}
00223   */
00224 
00225 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
00226   * @{
00227   */
00228 
00229 #define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
00230 #define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
00231 #define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
00232 #define DAC_WAVE_NONE                                   ((uint32_t)0x00000000U)
00233 #define DAC_WAVE_NOISE                                  ((uint32_t)DAC_CR_WAVE1_0)
00234 #define DAC_WAVE_TRIANGLE                               ((uint32_t)DAC_CR_WAVE1_1)                           
00235 #define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
00236 #define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
00237 #define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
00238 
00239 /**
00240   * @}
00241   */
00242 
00243 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
00244   * @{
00245   */
00246 #define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2       
00247 #define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4 
00248 #define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5   
00249 #define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4       
00250 #define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2       
00251 #define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
00252 #define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
00253 #define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7      
00254 #define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67  
00255 #define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67 
00256 #define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32  
00257 #define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76   
00258 #define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6     
00259 #define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7      
00260 #define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6    
00261   
00262 #define IS_HAL_REMAPDMA                          IS_DMA_REMAP  
00263 #define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
00264 #define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
00265   
00266   
00267   
00268 /**
00269   * @}
00270   */
00271 
00272 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
00273   * @{
00274   */
00275   
00276 #define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
00277 #define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
00278 #define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
00279 #define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
00280 #define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
00281 #define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
00282 #define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
00283 #define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
00284 #define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
00285 #define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
00286 #define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
00287 #define OBEX_PCROP                    OPTIONBYTE_PCROP
00288 #define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
00289 #define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
00290 #define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
00291 #define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
00292 #define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
00293 #define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
00294 #define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
00295 #define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
00296 #define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
00297 #define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
00298 #define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
00299 #define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
00300 #define PAGESIZE                      FLASH_PAGE_SIZE
00301 #define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
00302 #define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
00303 #define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
00304 #define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
00305 #define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
00306 #define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
00307 #define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
00308 #define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
00309 #define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
00310 #define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
00311 #define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
00312 #define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
00313 #define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
00314 #define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
00315 #define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
00316 #define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
00317 #define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
00318 #define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
00319 #define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
00320 #define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
00321 #define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
00322 #define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
00323 #define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
00324 #define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
00325 #define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
00326 #define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
00327 #define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
00328 #define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
00329 #define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
00330 #define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
00331 #define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
00332 #define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
00333 #define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
00334 #define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
00335 #define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
00336 #define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
00337 #define OB_WDG_SW                     OB_IWDG_SW
00338 #define OB_WDG_HW                     OB_IWDG_HW
00339 #define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
00340 #define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
00341 #define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
00342 #define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
00343 #define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
00344 #define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
00345 #define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
00346 #define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
00347 /**
00348   * @}
00349   */
00350   
00351 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
00352   * @{
00353   */
00354   
00355 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
00356 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
00357 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
00358 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
00359 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
00360 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
00361 #define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
00362 #define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
00363 #define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
00364 /**
00365   * @}
00366   */
00367   
00368 
00369 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
00370   * @{
00371   */
00372 #if defined(STM32L4) || defined(STM32F7)
00373 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
00374 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
00375 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
00376 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
00377 #else
00378 #define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
00379 #define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
00380 #define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
00381 #define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
00382 #endif
00383 /**
00384   * @}
00385   */
00386 
00387 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
00388   * @{
00389   */
00390   
00391 #define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
00392 #define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
00393 /**
00394   * @}
00395   */
00396 
00397 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
00398   * @{
00399   */
00400 #define GET_GPIO_SOURCE                           GPIO_GET_INDEX
00401 #define GET_GPIO_INDEX                            GPIO_GET_INDEX
00402 
00403 #if defined(STM32F4)
00404 #define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
00405 #define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
00406 #endif
00407 
00408 #if defined(STM32F7)
00409 #define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
00410 #define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
00411 #endif
00412 
00413 #if defined(STM32L4)
00414 #define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
00415 #define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
00416 #endif
00417 
00418 #define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
00419 #define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
00420 #define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
00421 
00422 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
00423 #define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW     
00424 #define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM     
00425 #define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH     
00426 #define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH       
00427 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
00428 
00429 #if defined(STM32L1) 
00430  #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW     
00431  #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM     
00432  #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH     
00433  #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH     
00434 #endif /* STM32L1 */
00435 
00436 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
00437  #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
00438  #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
00439  #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
00440 #endif /* STM32F0 || STM32F3 || STM32F1 */
00441 
00442 #define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
00443 /**
00444   * @}
00445   */
00446 
00447 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
00448   * @{
00449   */
00450 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
00451 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
00452 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
00453 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
00454 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
00455 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
00456 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
00457 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
00458 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
00459    
00460 #define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
00461 #define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
00462 #define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
00463 #define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
00464 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
00465 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
00466 #define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
00467 #define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
00468 /**
00469   * @}
00470   */
00471 
00472 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
00473   * @{
00474   */
00475 #define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
00476 #define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
00477 #define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
00478 #define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
00479 #define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
00480 #define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
00481 #define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
00482 #define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
00483 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
00484 #define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
00485 #define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
00486 #define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
00487 #define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
00488 #define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
00489 #define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
00490 #endif
00491 /**
00492   * @}
00493   */
00494 
00495 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
00496   * @{
00497   */
00498 #define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
00499 #define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
00500 
00501 /**
00502   * @}
00503   */
00504 
00505 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
00506   * @{
00507   */
00508 #define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
00509 #define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
00510 #define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
00511 #define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
00512 /**
00513   * @}
00514   */
00515 
00516 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
00517   * @{
00518   */
00519 
00520 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
00521 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
00522 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
00523 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
00524 
00525 #define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
00526 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
00527 #define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
00528 
00529 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
00530 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
00531 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
00532 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS        
00533 
00534 /* The following 3 definition have also been present in a temporary version of lptim.h */
00535 /* They need to be renamed also to the right name, just in case */
00536 #define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
00537 #define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
00538 #define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
00539 
00540 /**
00541   * @}
00542   */
00543 
00544 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
00545   * @{
00546   */
00547 #define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
00548 #define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
00549 #define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
00550 #define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
00551 
00552 #define NAND_AddressTypedef             NAND_AddressTypeDef
00553 
00554 #define __ARRAY_ADDRESS                 ARRAY_ADDRESS
00555 #define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
00556 #define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
00557 #define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
00558 #define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
00559 /**
00560   * @}
00561   */
00562    
00563 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
00564   * @{
00565   */
00566 #define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
00567 #define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
00568 #define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
00569 #define NOR_ERROR                      HAL_NOR_STATUS_ERROR
00570 #define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
00571 
00572 #define __NOR_WRITE                    NOR_WRITE
00573 #define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
00574 /**
00575   * @}
00576   */
00577 
00578 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
00579   * @{
00580   */
00581 
00582 #define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
00583 #define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
00584 #define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
00585 #define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
00586                                               
00587 #define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
00588 #define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
00589 #define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
00590 #define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3   
00591 
00592 #define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
00593 #define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
00594 
00595 #define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
00596 #define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
00597 
00598 #define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
00599 #define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1    
00600 
00601 #define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
00602                                                                       
00603 #define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO             
00604 #define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0            
00605 #define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1          
00606                                                         
00607 /**
00608   * @}
00609   */
00610 
00611 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
00612   * @{
00613   */
00614 #define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
00615 #if defined(STM32F7) 
00616   #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
00617 #endif
00618 /**
00619   * @}
00620   */
00621 
00622 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
00623   * @{
00624   */
00625 
00626 /* Compact Flash-ATA registers description */
00627 #define CF_DATA                       ATA_DATA                
00628 #define CF_SECTOR_COUNT               ATA_SECTOR_COUNT        
00629 #define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER       
00630 #define CF_CYLINDER_LOW               ATA_CYLINDER_LOW        
00631 #define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH       
00632 #define CF_CARD_HEAD                  ATA_CARD_HEAD           
00633 #define CF_STATUS_CMD                 ATA_STATUS_CMD          
00634 #define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
00635 #define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA    
00636 
00637 /* Compact Flash-ATA commands */
00638 #define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD 
00639 #define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
00640 #define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
00641 #define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
00642 
00643 #define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
00644 #define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
00645 #define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
00646 #define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
00647 #define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
00648 /**
00649   * @}
00650   */
00651   
00652 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
00653   * @{
00654   */
00655   
00656 #define FORMAT_BIN                  RTC_FORMAT_BIN
00657 #define FORMAT_BCD                  RTC_FORMAT_BCD
00658 
00659 #define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
00660 #define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
00661 #define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
00662 #define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
00663 #define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
00664 
00665 #define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
00666 #define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE 
00667 #define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
00668 #define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE 
00669 #define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
00670 #define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
00671 #define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT 
00672 #define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT 
00673 
00674 #define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
00675 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 
00676 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
00677 #define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
00678 
00679 #define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
00680 #define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
00681 #define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
00682 
00683 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 
00684 #define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1 
00685 #define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
00686 
00687 /**
00688   * @}
00689   */
00690 
00691   
00692 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
00693   * @{
00694   */
00695 #define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
00696 #define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
00697 
00698 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
00699 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
00700 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
00701 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
00702 
00703 #define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
00704 #define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
00705 
00706 #define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
00707 #define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
00708 /**
00709   * @}
00710   */
00711 
00712   
00713 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
00714   * @{
00715   */
00716 #define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
00717 #define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
00718 #define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
00719 #define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
00720 #define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
00721 #define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
00722 #define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
00723 #define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
00724 #define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
00725 #define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
00726 #define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
00727 /**
00728   * @}
00729   */
00730   
00731 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
00732   * @{
00733   */
00734 #define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
00735 #define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
00736 
00737 #define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
00738 #define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
00739 
00740 #define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
00741 #define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
00742 
00743 /**
00744   * @}
00745   */
00746   
00747 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
00748   * @{
00749   */
00750 #define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
00751 #define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
00752   
00753 #define TIM_DMABase_CR1                  TIM_DMABASE_CR1
00754 #define TIM_DMABase_CR2                  TIM_DMABASE_CR2
00755 #define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
00756 #define TIM_DMABase_DIER                 TIM_DMABASE_DIER
00757 #define TIM_DMABase_SR                   TIM_DMABASE_SR
00758 #define TIM_DMABase_EGR                  TIM_DMABASE_EGR
00759 #define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
00760 #define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
00761 #define TIM_DMABase_CCER                 TIM_DMABASE_CCER
00762 #define TIM_DMABase_CNT                  TIM_DMABASE_CNT
00763 #define TIM_DMABase_PSC                  TIM_DMABASE_PSC
00764 #define TIM_DMABase_ARR                  TIM_DMABASE_ARR
00765 #define TIM_DMABase_RCR                  TIM_DMABASE_RCR
00766 #define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
00767 #define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
00768 #define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
00769 #define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
00770 #define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
00771 #define TIM_DMABase_DCR                  TIM_DMABASE_DCR
00772 #define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
00773 #define TIM_DMABase_OR1                  TIM_DMABASE_OR1
00774 #define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
00775 #define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
00776 #define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
00777 #define TIM_DMABase_OR2                  TIM_DMABASE_OR2
00778 #define TIM_DMABase_OR3                  TIM_DMABASE_OR3
00779 #define TIM_DMABase_OR                   TIM_DMABASE_OR
00780 
00781 #define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
00782 #define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
00783 #define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
00784 #define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
00785 #define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
00786 #define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
00787 #define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
00788 #define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
00789 #define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
00790 
00791 #define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
00792 #define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
00793 #define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
00794 #define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
00795 #define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
00796 #define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
00797 #define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
00798 #define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
00799 #define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
00800 #define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
00801 #define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
00802 #define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
00803 #define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
00804 #define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
00805 #define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
00806 #define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
00807 #define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
00808 #define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
00809 
00810 /**
00811   * @}
00812   */
00813 
00814 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
00815   * @{
00816   */
00817 #define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
00818 #define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
00819 /**
00820   * @}
00821   */
00822 
00823 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
00824   * @{
00825   */
00826 #define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
00827 #define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
00828 #define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
00829 #define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
00830 
00831 #define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
00832 #define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
00833 
00834 #define __DIV_SAMPLING16                UART_DIV_SAMPLING16
00835 #define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
00836 #define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
00837 #define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
00838 
00839 #define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
00840 #define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
00841 #define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
00842 #define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
00843 
00844 #define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
00845 #define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
00846 
00847 /**
00848   * @}
00849   */
00850 
00851   
00852 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
00853   * @{
00854   */
00855 
00856 #define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
00857 #define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
00858 
00859 #define USARTNACK_ENABLED               USART_NACK_ENABLE
00860 #define USARTNACK_DISABLED              USART_NACK_DISABLE
00861 /**
00862   * @}
00863   */
00864 
00865 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
00866   * @{
00867   */
00868 #define CFR_BASE                    WWDG_CFR_BASE
00869 
00870 /**
00871   * @}
00872   */
00873 
00874 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
00875   * @{
00876   */
00877 #define CAN_FilterFIFO0             CAN_FILTER_FIFO0
00878 #define CAN_FilterFIFO1             CAN_FILTER_FIFO1
00879 #define CAN_IT_RQCP0                CAN_IT_TME
00880 #define CAN_IT_RQCP1                CAN_IT_TME
00881 #define CAN_IT_RQCP2                CAN_IT_TME
00882 #define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
00883 #define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
00884 #define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
00885 #define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
00886 #define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
00887 
00888 /**
00889   * @}
00890   */
00891   
00892 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
00893   * @{
00894   */
00895 
00896 #define VLAN_TAG                ETH_VLAN_TAG
00897 #define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
00898 #define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
00899 #define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
00900 #define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
00901 #define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
00902 #define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
00903 #define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
00904 
00905 #define ETH_MMCCR              ((uint32_t)0x00000100U)  
00906 #define ETH_MMCRIR             ((uint32_t)0x00000104U)  
00907 #define ETH_MMCTIR             ((uint32_t)0x00000108U)  
00908 #define ETH_MMCRIMR            ((uint32_t)0x0000010CU)  
00909 #define ETH_MMCTIMR            ((uint32_t)0x00000110U)  
00910 #define ETH_MMCTGFSCCR         ((uint32_t)0x0000014CU)  
00911 #define ETH_MMCTGFMSCCR        ((uint32_t)0x00000150U)  
00912 #define ETH_MMCTGFCR           ((uint32_t)0x00000168U)  
00913 #define ETH_MMCRFCECR          ((uint32_t)0x00000194U)  
00914 #define ETH_MMCRFAECR          ((uint32_t)0x00000198U)  
00915 #define ETH_MMCRGUFCR          ((uint32_t)0x000001C4U)
00916  
00917 #define ETH_MAC_TXFIFO_FULL          ((uint32_t)0x02000000)  /* Tx FIFO full */
00918 #define ETH_MAC_TXFIFONOT_EMPTY      ((uint32_t)0x01000000)  /* Tx FIFO not empty */
00919 #define ETH_MAC_TXFIFO_WRITE_ACTIVE  ((uint32_t)0x00400000)  /* Tx FIFO write active */
00920 #define ETH_MAC_TXFIFO_IDLE     ((uint32_t)0x00000000)  /* Tx FIFO read status: Idle */
00921 #define ETH_MAC_TXFIFO_READ     ((uint32_t)0x00100000)  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
00922 #define ETH_MAC_TXFIFO_WAITING  ((uint32_t)0x00200000)  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
00923 #define ETH_MAC_TXFIFO_WRITING  ((uint32_t)0x00300000)  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
00924 #define ETH_MAC_TRANSMISSION_PAUSE     ((uint32_t)0x00080000)  /* MAC transmitter in pause */
00925 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            ((uint32_t)0x00000000)  /* MAC transmit frame controller: Idle */
00926 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         ((uint32_t)0x00020000)  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
00927 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   ((uint32_t)0x00040000)  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
00928 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    ((uint32_t)0x00060000)  /* MAC transmit frame controller: Transferring input frame for transmission */
00929 #define ETH_MAC_MII_TRANSMIT_ACTIVE      ((uint32_t)0x00010000)  /* MAC MII transmit engine active */
00930 #define ETH_MAC_RXFIFO_EMPTY             ((uint32_t)0x00000000)  /* Rx FIFO fill level: empty */
00931 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD   ((uint32_t)0x00000100)  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
00932 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   ((uint32_t)0x00000200)  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
00933 #define ETH_MAC_RXFIFO_FULL              ((uint32_t)0x00000300)  /* Rx FIFO fill level: full */
00934 #if defined(STM32F1)
00935 #else
00936 #define ETH_MAC_READCONTROLLER_IDLE               ((uint32_t)0x00000000)  /* Rx FIFO read controller IDLE state */
00937 #define ETH_MAC_READCONTROLLER_READING_DATA       ((uint32_t)0x00000020)  /* Rx FIFO read controller Reading frame data */
00938 #define ETH_MAC_READCONTROLLER_READING_STATUS     ((uint32_t)0x00000040)  /* Rx FIFO read controller Reading frame status (or time-stamp) */
00939 #endif
00940 #define ETH_MAC_READCONTROLLER_FLUSHING           ((uint32_t)0x00000060)  /* Rx FIFO read controller Flushing the frame data and status */
00941 #define ETH_MAC_RXFIFO_WRITE_ACTIVE     ((uint32_t)0x00000010)  /* Rx FIFO write controller active */
00942 #define ETH_MAC_SMALL_FIFO_NOTACTIVE    ((uint32_t)0x00000000)  /* MAC small FIFO read / write controllers not active */
00943 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE  ((uint32_t)0x00000002)  /* MAC small FIFO read controller active */
00944 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004)  /* MAC small FIFO write controller active */
00945 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE    ((uint32_t)0x00000006)  /* MAC small FIFO read / write controllers active */
00946 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   ((uint32_t)0x00000001)  /* MAC MII receive protocol engine active */
00947 
00948 /**
00949   * @}
00950   */
00951   
00952 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
00953   * @{
00954   */
00955 #define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
00956 #define DCMI_IT_OVF             DCMI_IT_OVR
00957 #define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
00958 #define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
00959 
00960 #define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
00961 #define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
00962 #define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
00963 
00964 /**
00965   * @}
00966   */  
00967   
00968 #if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
00969     defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00970 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
00971   * @{
00972   */
00973 #define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
00974 #define DMA2D_RGB888            DMA2D_OUTPUT_RGB888  
00975 #define DMA2D_RGB565            DMA2D_OUTPUT_RGB565  
00976 #define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
00977 #define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
00978 
00979 #define CM_ARGB8888             DMA2D_INPUT_ARGB8888
00980 #define CM_RGB888               DMA2D_INPUT_RGB888  
00981 #define CM_RGB565               DMA2D_INPUT_RGB565  
00982 #define CM_ARGB1555             DMA2D_INPUT_ARGB1555
00983 #define CM_ARGB4444             DMA2D_INPUT_ARGB4444
00984 #define CM_L8                   DMA2D_INPUT_L8      
00985 #define CM_AL44                 DMA2D_INPUT_AL44    
00986 #define CM_AL88                 DMA2D_INPUT_AL88    
00987 #define CM_L4                   DMA2D_INPUT_L4      
00988 #define CM_A8                   DMA2D_INPUT_A8      
00989 #define CM_A4                   DMA2D_INPUT_A4      
00990 /**
00991   * @}
00992   */    
00993 #endif  /* STM32L4xx ||  STM32F7*/
00994 
00995 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
00996   * @{
00997   */
00998   
00999 /**
01000   * @}
01001   */
01002 
01003 /* Exported functions --------------------------------------------------------*/
01004 
01005 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
01006   * @{
01007   */
01008 #define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
01009 /**
01010   * @}
01011   */  
01012 
01013 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
01014   * @{
01015   */ 
01016 #define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
01017 #define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
01018 #define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
01019 #define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
01020 #define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
01021 #define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
01022 
01023 /*HASH Algorithm Selection*/
01024 
01025 #define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1 
01026 #define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
01027 #define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
01028 #define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
01029 
01030 #define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH 
01031 #define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
01032 
01033 #define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
01034 #define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
01035 /**
01036   * @}
01037   */
01038   
01039 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
01040   * @{
01041   */
01042 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
01043 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
01044 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
01045 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
01046 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
01047 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
01048 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
01049 #define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
01050 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
01051 #if defined(STM32L0)
01052 #else
01053 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
01054 #endif
01055 #define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
01056 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
01057 /**
01058   * @}
01059   */
01060 
01061 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
01062   * @{
01063   */
01064 #define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
01065 #define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
01066 #define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
01067 #define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
01068 #define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
01069 #define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
01070 #define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
01071 
01072  /**
01073   * @}
01074   */
01075 
01076 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
01077   * @{
01078   */
01079 #define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
01080 #define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
01081 #define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
01082 #define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
01083 
01084 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
01085  /**
01086   * @}
01087   */
01088 
01089 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
01090   * @{
01091   */
01092 #define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
01093 #define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
01094 #define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
01095 #define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
01096 #define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
01097 #define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
01098 #define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
01099 #define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
01100 #define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
01101 #define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
01102 #define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
01103 #define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
01104 #define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
01105 #define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
01106 #define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
01107 #define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
01108 
01109 #define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
01110 #define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
01111 #define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
01112 #define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
01113 #define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
01114 #define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
01115 #define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
01116 
01117 #define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
01118 #define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
01119 
01120 #define DBP_BitNumber                                 DBP_BIT_NUMBER
01121 #define PVDE_BitNumber                                PVDE_BIT_NUMBER
01122 #define PMODE_BitNumber                               PMODE_BIT_NUMBER
01123 #define EWUP_BitNumber                                EWUP_BIT_NUMBER
01124 #define FPDS_BitNumber                                FPDS_BIT_NUMBER
01125 #define ODEN_BitNumber                                ODEN_BIT_NUMBER
01126 #define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
01127 #define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
01128 #define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
01129 #define BRE_BitNumber                                 BRE_BIT_NUMBER
01130 
01131 #define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
01132  
01133  /**
01134   * @}
01135   */  
01136   
01137 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
01138   * @{
01139   */
01140 #define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
01141 #define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback         
01142 #define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback   
01143 /**
01144   * @}
01145   */
01146 
01147 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
01148   * @{
01149   */
01150 #define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
01151 /**
01152   * @}
01153   */  
01154 
01155 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
01156   * @{
01157   */
01158 #define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
01159 #define HAL_TIM_DMAError                                TIM_DMAError
01160 #define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
01161 #define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
01162 /**
01163   * @}
01164   */
01165    
01166 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
01167   * @{
01168   */ 
01169 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
01170 /**
01171   * @}
01172   */
01173   
01174 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
01175   * @{
01176   */ 
01177 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
01178 /**
01179   * @}
01180   */  
01181    
01182   
01183 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
01184   * @{
01185   */
01186   
01187 /**
01188   * @}
01189   */
01190 
01191 /* Exported macros ------------------------------------------------------------*/
01192 
01193 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
01194   * @{
01195   */
01196 #define AES_IT_CC                      CRYP_IT_CC
01197 #define AES_IT_ERR                     CRYP_IT_ERR
01198 #define AES_FLAG_CCF                   CRYP_FLAG_CCF
01199 /**
01200   * @}
01201   */  
01202   
01203 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
01204   * @{
01205   */
01206 #define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
01207 #define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
01208 #define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
01209 #define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
01210 #define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
01211 #define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 
01212 #define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
01213 #define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
01214 #define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
01215 #define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
01216 #define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
01217 #define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
01218 #define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
01219 
01220 #define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
01221 #define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
01222 #define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
01223 #define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
01224 #define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
01225 
01226 /**
01227   * @}
01228   */
01229 
01230    
01231 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
01232   * @{
01233   */
01234 #define __ADC_ENABLE                                     __HAL_ADC_ENABLE
01235 #define __ADC_DISABLE                                    __HAL_ADC_DISABLE
01236 #define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
01237 #define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
01238 #define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
01239 #define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
01240 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
01241 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
01242 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
01243 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
01244 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
01245 #define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
01246 #define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
01247 
01248 #define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
01249 #define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
01250 #define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
01251 #define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
01252 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
01253 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
01254 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
01255 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
01256 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
01257 #define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
01258 #define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
01259 #define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
01260 #define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
01261 #define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
01262 #define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
01263 #define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
01264 #define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
01265 #define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
01266 #define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
01267 #define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
01268 
01269 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
01270 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
01271 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
01272 #define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
01273 #define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
01274 #define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
01275 #define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
01276 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
01277 #define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
01278 #define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
01279 
01280 #define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
01281 #define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
01282 #define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
01283 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
01284 #define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
01285 #define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
01286 #define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
01287 #define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
01288 
01289 #define __HAL_ADC_SQR1                                   ADC_SQR1
01290 #define __HAL_ADC_SMPR1                                  ADC_SMPR1
01291 #define __HAL_ADC_SMPR2                                  ADC_SMPR2
01292 #define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
01293 #define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
01294 #define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
01295 #define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
01296 #define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
01297 #define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
01298 #define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
01299 #define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
01300 #define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
01301 #define __HAL_ADC_JSQR                                   ADC_JSQR
01302 
01303 #define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
01304 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
01305 #define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
01306 #define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
01307 #define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
01308 #define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
01309 #define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
01310 #define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
01311 
01312 /**
01313   * @}
01314   */
01315 
01316 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
01317   * @{
01318   */
01319 #define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
01320 #define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
01321 #define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
01322 #define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
01323 
01324 /**
01325   * @}
01326   */
01327    
01328 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
01329   * @{
01330   */
01331 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
01332 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
01333 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
01334 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
01335 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
01336 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
01337 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
01338 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
01339 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
01340 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
01341 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
01342 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
01343 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
01344 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
01345 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
01346 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
01347 
01348 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
01349 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
01350 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
01351 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
01352 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
01353 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
01354 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
01355 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
01356 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
01357 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
01358 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
01359 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
01360 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
01361 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
01362 
01363 
01364 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
01365 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
01366 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
01367 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
01368 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
01369 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
01370 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
01371 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
01372 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
01373 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
01374 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
01375 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
01376 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
01377 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
01378 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
01379 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
01380 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
01381 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
01382 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
01383 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
01384 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
01385 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
01386 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
01387 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
01388 
01389 /**
01390   * @}
01391   */
01392 
01393 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
01394   * @{
01395   */
01396 #if defined(STM32F3)
01397 #define COMP_START                                       __HAL_COMP_ENABLE
01398 #define COMP_STOP                                        __HAL_COMP_DISABLE
01399 #define COMP_LOCK                                        __HAL_COMP_LOCK
01400    
01401 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
01402 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
01403                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
01404                                                           __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
01405 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
01406                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
01407                                                           __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
01408 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
01409                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
01410                                                           __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
01411 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
01412                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
01413                                                           __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
01414 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
01415                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
01416                                                           __HAL_COMP_COMP6_EXTI_ENABLE_IT())
01417 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
01418                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
01419                                                           __HAL_COMP_COMP6_EXTI_DISABLE_IT())
01420 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
01421                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
01422                                                           __HAL_COMP_COMP6_EXTI_GET_FLAG())
01423 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
01424                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
01425                                                           __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
01426 # endif
01427 # if defined(STM32F302xE) || defined(STM32F302xC)
01428 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
01429                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
01430                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
01431                                                           __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
01432 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
01433                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
01434                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
01435                                                           __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
01436 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
01437                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
01438                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
01439                                                           __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
01440 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
01441                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
01442                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
01443                                                           __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
01444 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
01445                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
01446                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
01447                                                           __HAL_COMP_COMP6_EXTI_ENABLE_IT())
01448 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
01449                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
01450                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
01451                                                           __HAL_COMP_COMP6_EXTI_DISABLE_IT())
01452 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
01453                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
01454                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
01455                                                           __HAL_COMP_COMP6_EXTI_GET_FLAG())
01456 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
01457                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
01458                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
01459                                                           __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
01460 # endif
01461 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
01462 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
01463                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
01464                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
01465                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
01466                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
01467                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
01468                                                           __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
01469 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
01470                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
01471                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
01472                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
01473                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
01474                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
01475                                                           __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
01476 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
01477                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
01478                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
01479                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
01480                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
01481                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
01482                                                           __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
01483 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
01484                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
01485                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
01486                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
01487                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
01488                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
01489                                                           __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
01490 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
01491                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
01492                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
01493                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
01494                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
01495                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
01496                                                           __HAL_COMP_COMP7_EXTI_ENABLE_IT())
01497 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
01498                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
01499                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
01500                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
01501                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
01502                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
01503                                                           __HAL_COMP_COMP7_EXTI_DISABLE_IT())
01504 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
01505                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
01506                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
01507                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
01508                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
01509                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
01510                                                           __HAL_COMP_COMP7_EXTI_GET_FLAG())
01511 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
01512                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
01513                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
01514                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
01515                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
01516                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
01517                                                           __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
01518 # endif
01519 # if defined(STM32F373xC) ||defined(STM32F378xx)
01520 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
01521                                                           __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
01522 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
01523                                                           __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
01524 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
01525                                                           __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
01526 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
01527                                                           __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
01528 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
01529                                                           __HAL_COMP_COMP2_EXTI_ENABLE_IT())
01530 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
01531                                                           __HAL_COMP_COMP2_EXTI_DISABLE_IT())
01532 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
01533                                                           __HAL_COMP_COMP2_EXTI_GET_FLAG())
01534 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
01535                                                           __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
01536 # endif
01537 #else
01538 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
01539                                                           __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
01540 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
01541                                                           __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
01542 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
01543                                                           __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
01544 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
01545                                                           __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
01546 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
01547                                                           __HAL_COMP_COMP2_EXTI_ENABLE_IT())
01548 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
01549                                                           __HAL_COMP_COMP2_EXTI_DISABLE_IT())
01550 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
01551                                                           __HAL_COMP_COMP2_EXTI_GET_FLAG())
01552 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
01553                                                           __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
01554 #endif
01555 
01556 #define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
01557 
01558 #if defined(STM32L0) || defined(STM32L4)
01559 /* Note: On these STM32 families, the only argument of this macro             */
01560 /*       is COMP_FLAG_LOCK.                                                   */
01561 /*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
01562 /*       argument.                                                            */
01563 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
01564 #endif
01565 /**
01566   * @}
01567   */
01568 
01569 #if defined(STM32L0) || defined(STM32L4)
01570 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
01571   * @{
01572   */
01573 #define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
01574 #define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
01575 /**
01576   * @}
01577   */
01578 #endif
01579 
01580 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
01581   * @{
01582   */
01583 
01584 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
01585                           ((WAVE) == DAC_WAVE_NOISE)|| \
01586                           ((WAVE) == DAC_WAVE_TRIANGLE))
01587   
01588 /**
01589   * @}
01590   */
01591 
01592 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
01593   * @{
01594   */
01595 
01596 #define IS_WRPAREA          IS_OB_WRPAREA
01597 #define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
01598 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
01599 #define IS_TYPEERASE        IS_FLASH_TYPEERASE
01600 #define IS_NBSECTORS        IS_FLASH_NBSECTORS
01601 #define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
01602 
01603 /**
01604   * @}
01605   */
01606   
01607 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
01608   * @{
01609   */
01610   
01611 #define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
01612 #define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
01613 #define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
01614 #define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
01615 #define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
01616 #define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
01617 #define __HAL_I2C_SPEED                 I2C_SPEED
01618 #define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
01619 #define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
01620 #define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
01621 #define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
01622 #define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
01623 #define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
01624 #define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
01625 #define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
01626 /**
01627   * @}
01628   */
01629   
01630 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
01631   * @{
01632   */
01633   
01634 #define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
01635 #define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
01636 
01637 /**
01638   * @}
01639   */
01640 
01641 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
01642   * @{
01643   */
01644   
01645 #define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
01646 #define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
01647 
01648 #define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
01649 #define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
01650 #define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
01651 #define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
01652 
01653 #define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE                  
01654 
01655 
01656 /**
01657   * @}
01658   */
01659 
01660 
01661 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
01662   * @{
01663   */
01664 #define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
01665 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
01666 /**
01667   * @}
01668   */
01669 
01670 
01671 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
01672   * @{
01673   */
01674 
01675 #define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
01676 #define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
01677 #define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
01678 
01679 /**
01680   * @}
01681   */
01682   
01683   
01684 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
01685   * @{
01686   */
01687 #define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
01688 #define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
01689 #define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
01690 #define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
01691 #define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
01692 #define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
01693 #define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
01694 #define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
01695 #define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
01696 #define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
01697 #define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
01698 #define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
01699 #define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
01700 
01701 /**
01702   * @}
01703   */
01704 
01705 
01706 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
01707   * @{
01708   */
01709 #define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
01710 #define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
01711 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
01712 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
01713 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
01714 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
01715 #define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
01716 #define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
01717 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
01718 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
01719 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
01720 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
01721 #define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
01722 #define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
01723 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
01724 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
01725 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
01726 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
01727 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
01728 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
01729 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
01730 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
01731 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
01732 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
01733 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
01734 #define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
01735 #define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
01736 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
01737 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
01738 #define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
01739 #define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
01740 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
01741 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
01742 #define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
01743 #define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
01744 
01745 #if defined (STM32F4)
01746 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
01747 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
01748 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()   
01749 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
01750 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
01751 #else
01752 #define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
01753 #define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
01754 #define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
01755 #define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
01756 #define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG 
01757 #endif /* STM32F4 */
01758 /**   
01759   * @}
01760   */  
01761   
01762   
01763 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
01764   * @{
01765   */
01766   
01767 #define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
01768 #define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
01769 
01770 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
01771 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
01772 
01773 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
01774 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
01775 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
01776 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
01777 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
01778 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
01779 #define __ADC1_CLK_DISABLE        __HAL_RCC_ADC1_CLK_DISABLE
01780 #define __ADC1_CLK_ENABLE         __HAL_RCC_ADC1_CLK_ENABLE
01781 #define __ADC1_FORCE_RESET        __HAL_RCC_ADC1_FORCE_RESET
01782 #define __ADC1_RELEASE_RESET      __HAL_RCC_ADC1_RELEASE_RESET
01783 #define __ADC1_CLK_SLEEP_ENABLE   __HAL_RCC_ADC1_CLK_SLEEP_ENABLE  
01784 #define __ADC1_CLK_SLEEP_DISABLE  __HAL_RCC_ADC1_CLK_SLEEP_DISABLE  
01785 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
01786 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
01787 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
01788 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
01789 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
01790 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
01791 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
01792 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
01793 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
01794 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
01795 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
01796 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
01797 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
01798 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
01799 #define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
01800 #define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
01801 #define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
01802 #define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
01803 #define __CRYP_FORCE_RESET  __HAL_RCC_CRYP_FORCE_RESET
01804 #define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
01805 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
01806 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
01807 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
01808 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
01809 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
01810 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
01811 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
01812 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
01813 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
01814 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
01815 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
01816 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
01817 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
01818 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
01819 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
01820 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
01821 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
01822 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
01823 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
01824 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
01825 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
01826 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
01827 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
01828 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
01829 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
01830 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
01831 #define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
01832 #define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
01833 #define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
01834 #define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
01835 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
01836 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
01837 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
01838 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
01839 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
01840 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
01841 #define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
01842 #define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
01843 #define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
01844 #define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
01845 #define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
01846 #define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
01847 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
01848 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
01849 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
01850 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
01851 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
01852 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
01853 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
01854 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
01855 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
01856 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
01857 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
01858 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
01859 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
01860 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
01861 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
01862 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
01863 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
01864 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
01865 #define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
01866 #define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
01867 #define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
01868 #define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
01869 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
01870 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
01871 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
01872 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
01873 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
01874 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
01875 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
01876 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
01877 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
01878 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
01879 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
01880 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
01881 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
01882 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
01883 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
01884 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
01885 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
01886 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
01887 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
01888 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
01889 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
01890 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
01891 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
01892 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
01893 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
01894 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
01895 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
01896 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
01897 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
01898 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
01899 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
01900 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
01901 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
01902 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
01903 #define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
01904 #define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
01905 #define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
01906 #define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
01907 #define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
01908 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
01909 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
01910 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
01911 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
01912 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
01913 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
01914 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
01915 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
01916 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
01917 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
01918 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
01919 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
01920 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
01921 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
01922 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
01923 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
01924 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
01925 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
01926 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
01927 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
01928 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
01929 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
01930 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
01931 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
01932 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
01933 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
01934 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
01935 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
01936 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
01937 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
01938 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
01939 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
01940 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
01941 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
01942 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
01943 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
01944 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
01945 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
01946 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
01947 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
01948 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
01949 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
01950 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
01951 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
01952 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
01953 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
01954 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
01955 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
01956 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
01957 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
01958 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
01959 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
01960 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
01961 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
01962 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
01963 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
01964 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
01965 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
01966 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
01967 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
01968 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
01969 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
01970 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
01971 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
01972 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
01973 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
01974 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
01975 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
01976 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
01977 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
01978 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
01979 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
01980 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
01981 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
01982 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
01983 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
01984 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
01985 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
01986 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
01987 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
01988 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
01989 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
01990 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
01991 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
01992 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
01993 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
01994 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
01995 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
01996 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
01997 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
01998 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
01999 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
02000 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
02001 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
02002 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
02003 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
02004 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
02005 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
02006 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
02007 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
02008 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
02009 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
02010 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
02011 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
02012 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
02013 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
02014 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
02015 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
02016 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
02017 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
02018 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
02019 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
02020 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
02021 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
02022 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
02023 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
02024 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
02025 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
02026 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
02027 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
02028 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
02029 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
02030 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
02031 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
02032 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
02033 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
02034 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
02035 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
02036 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
02037 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
02038 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
02039 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
02040 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
02041 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
02042 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
02043 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
02044 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
02045 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
02046 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
02047 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
02048 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
02049 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
02050 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
02051 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
02052 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
02053 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
02054 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
02055 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
02056 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
02057 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
02058 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
02059 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
02060 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
02061 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
02062 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
02063 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
02064 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
02065 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
02066 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
02067 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
02068 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
02069 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
02070 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
02071 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
02072 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
02073 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
02074 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
02075 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
02076 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
02077 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
02078 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
02079 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
02080 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
02081 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
02082 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
02083 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
02084 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
02085 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
02086 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
02087 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
02088 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
02089 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
02090 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
02091 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
02092 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
02093 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
02094 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
02095 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
02096 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
02097 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
02098 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
02099 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
02100 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
02101 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
02102 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
02103 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
02104 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
02105 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
02106 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
02107 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
02108 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
02109 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
02110 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
02111 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
02112 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
02113 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
02114 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
02115 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
02116 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
02117 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
02118 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
02119 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
02120 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
02121 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
02122 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
02123 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
02124 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
02125 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
02126 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
02127 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
02128 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
02129 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
02130 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
02131 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
02132 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
02133 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
02134 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
02135 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
02136 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
02137 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
02138 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
02139 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
02140 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
02141 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
02142 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
02143 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
02144 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
02145 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
02146 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
02147 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
02148 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
02149 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
02150 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
02151 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
02152 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
02153 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
02154 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
02155 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
02156 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
02157 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
02158 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
02159 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
02160 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
02161 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
02162 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
02163 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
02164 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
02165 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
02166 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
02167 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
02168 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
02169 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
02170 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
02171 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
02172 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
02173 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
02174 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
02175 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
02176 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
02177 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
02178 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
02179 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
02180 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
02181 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
02182 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
02183 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
02184 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
02185 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
02186 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
02187 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
02188 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
02189 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
02190 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
02191 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
02192 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
02193 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
02194 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
02195 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
02196 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
02197 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
02198 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
02199 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
02200 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
02201 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
02202 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
02203 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
02204 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
02205 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
02206 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
02207 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
02208 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
02209 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
02210 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
02211 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
02212 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
02213 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
02214 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
02215 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
02216 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
02217 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
02218 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
02219 #define __USART4_CLK_DISABLE        __HAL_RCC_USART4_CLK_DISABLE
02220 #define __USART4_CLK_ENABLE         __HAL_RCC_USART4_CLK_ENABLE
02221 #define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_USART4_CLK_SLEEP_ENABLE
02222 #define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_USART4_CLK_SLEEP_DISABLE 
02223 #define __USART4_FORCE_RESET        __HAL_RCC_USART4_FORCE_RESET
02224 #define __USART4_RELEASE_RESET      __HAL_RCC_USART4_RELEASE_RESET
02225 #define __USART5_CLK_DISABLE        __HAL_RCC_USART5_CLK_DISABLE
02226 #define __USART5_CLK_ENABLE         __HAL_RCC_USART5_CLK_ENABLE
02227 #define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_USART5_CLK_SLEEP_ENABLE
02228 #define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_USART5_CLK_SLEEP_DISABLE 
02229 #define __USART5_FORCE_RESET        __HAL_RCC_USART5_FORCE_RESET
02230 #define __USART5_RELEASE_RESET      __HAL_RCC_USART5_RELEASE_RESET
02231 #define __USART7_CLK_DISABLE        __HAL_RCC_USART7_CLK_DISABLE
02232 #define __USART7_CLK_ENABLE         __HAL_RCC_USART7_CLK_ENABLE
02233 #define __USART7_FORCE_RESET        __HAL_RCC_USART7_FORCE_RESET
02234 #define __USART7_RELEASE_RESET      __HAL_RCC_USART7_RELEASE_RESET
02235 #define __USART8_CLK_DISABLE        __HAL_RCC_USART8_CLK_DISABLE
02236 #define __USART8_CLK_ENABLE         __HAL_RCC_USART8_CLK_ENABLE
02237 #define __USART8_FORCE_RESET        __HAL_RCC_USART8_FORCE_RESET
02238 #define __USART8_RELEASE_RESET      __HAL_RCC_USART8_RELEASE_RESET
02239 #define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
02240 #define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
02241 #define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
02242 #define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
02243 #define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
02244 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
02245 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
02246 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
02247 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
02248 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
02249 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
02250 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
02251 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
02252 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
02253 #define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
02254 #define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
02255 #define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
02256 #define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
02257 #define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
02258 #define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
02259 #define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
02260 #define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
02261 #define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
02262 #define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
02263 #define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
02264 #define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
02265 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
02266 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
02267 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
02268 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
02269 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
02270 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
02271 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
02272 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
02273 
02274 #define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
02275 #define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
02276 #define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
02277 #define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
02278 #define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
02279 #define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
02280 #define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
02281 #define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE  
02282 #define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
02283 #define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE  
02284 #define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
02285 #define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE  
02286 #define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
02287 #define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE  
02288 #define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
02289 #define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
02290 #define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
02291 #define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE  
02292 #define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
02293 #define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
02294 #define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
02295 #define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
02296 #define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
02297 #define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE  
02298 #define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
02299 #define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
02300 #define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
02301 #define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
02302 #define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
02303 #define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE  
02304 #define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
02305 #define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
02306 #define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
02307 #define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
02308 #define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
02309 #define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE  
02310 #define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
02311 #define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
02312 #define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
02313 #define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
02314 #define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE  
02315 #define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
02316 #define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE  
02317 #define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
02318 #define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE  
02319 #define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
02320 #define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE  
02321 #define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
02322 #define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE  
02323 #define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
02324 #define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE  
02325 #define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
02326 #define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE  
02327 #define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
02328 #define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
02329 #define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
02330 #define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE  
02331 #define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
02332 #define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE  
02333 #define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
02334 #define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
02335 #define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
02336 #define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
02337 #define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
02338 #define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE  
02339 #define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
02340 #define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
02341 #define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
02342 #define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
02343 #define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
02344 #define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE  
02345 #define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
02346 #define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
02347 #define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
02348 #define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
02349 #define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
02350 #define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE  
02351 #define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
02352 #define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
02353 #define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
02354 #define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
02355 #define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
02356 #define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE  
02357 #define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
02358 #define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
02359 #define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
02360 #define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
02361 #define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE  
02362 #define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
02363 #define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE  
02364 #define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
02365 #define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
02366 #define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
02367 #define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
02368 #define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
02369 #define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE  
02370 #define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
02371 #define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
02372 #define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
02373 #define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
02374 #define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
02375 #define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE  
02376 #define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
02377 #define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
02378 #define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
02379 #define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
02380 #define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
02381 #define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE  
02382 #define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
02383 #define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
02384 #define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
02385 #define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET  
02386 #define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
02387 #define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
02388 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
02389 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
02390 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
02391 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
02392 #define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
02393 #define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET  
02394 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
02395 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 
02396 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
02397 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED   
02398 #define __CRYP_FORCE_RESET             __HAL_RCC_CRYP_FORCE_RESET  
02399 #define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE  
02400 #define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
02401 #define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE  
02402 #define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
02403 #define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE  
02404 #define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
02405 #define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE  
02406 #define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
02407 #define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE  
02408 #define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
02409 #define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
02410 #define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
02411 #define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE  
02412 #define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
02413 #define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
02414 #define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
02415 #define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE  
02416 #define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
02417 #define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
02418 #define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
02419 #define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
02420 #define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
02421 #define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
02422 
02423 /* alias define maintained for legacy */
02424 #define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
02425 #define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
02426 
02427 #define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
02428 #define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
02429 #define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
02430 #define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
02431 #define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
02432 #define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
02433 #define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
02434 #define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
02435 #define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
02436 #define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
02437 #define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
02438 #define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
02439 #define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
02440 #define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
02441 #define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
02442 #define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
02443 #define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
02444 #define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
02445 #define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
02446 #define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
02447 #define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
02448 #define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
02449 
02450 #define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
02451 #define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
02452 #define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
02453 #define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
02454 #define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
02455 #define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
02456 #define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
02457 #define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
02458 #define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
02459 #define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
02460 #define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
02461 #define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
02462 #define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
02463 #define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
02464 #define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
02465 #define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
02466 #define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
02467 #define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
02468 #define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
02469 #define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
02470 #define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
02471 #define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
02472 
02473 #define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
02474 #define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
02475 #define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
02476 #define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
02477 #define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
02478 #define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
02479 #define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
02480 #define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
02481 #define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
02482 #define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
02483 #define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
02484 #define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
02485 #define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
02486 #define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
02487 #define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
02488 #define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
02489 #define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
02490 #define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
02491 #define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
02492 #define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
02493 #define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
02494 #define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
02495 #define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
02496 #define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
02497 #define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
02498 #define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
02499 #define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
02500 #define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
02501 #define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
02502 #define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
02503 #define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
02504 #define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
02505 #define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
02506 #define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
02507 #define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
02508 #define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
02509 #define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
02510 #define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
02511 #define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
02512 #define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
02513 #define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
02514 #define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
02515 #define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
02516 #define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
02517 #define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
02518 #define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
02519 #define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
02520 #define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
02521 #define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
02522 #define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
02523 #define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
02524 #define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
02525 #define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
02526 #define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
02527 #define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
02528 #define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
02529 #define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
02530 #define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
02531 #define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
02532 #define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
02533 #define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
02534 #define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
02535 #define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
02536 #define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
02537 #define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
02538 #define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
02539 #define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
02540 #define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
02541 #define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
02542 #define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
02543 #define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
02544 #define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
02545 #define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
02546 #define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
02547 #define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
02548 #define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
02549 #define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
02550 #define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
02551 #define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
02552 #define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
02553 #define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
02554 #define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
02555 #define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
02556 #define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
02557 #define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
02558 #define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
02559 #define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
02560 #define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
02561 #define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
02562 #define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
02563 #define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
02564 #define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
02565 #define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
02566 #define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
02567 #define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
02568 #define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
02569 #define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
02570 #define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
02571 #define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
02572 #define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
02573 #define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
02574 #define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
02575 #define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
02576 #define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
02577 #define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
02578 #define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
02579 #define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
02580 #define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
02581 #define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
02582 #define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
02583 #define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
02584 #define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
02585 #define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
02586 #define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
02587 #define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
02588 #define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
02589 
02590 #if defined(STM32F4)
02591 #define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
02592 #define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
02593 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
02594 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
02595 #define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
02596 #define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
02597 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
02598 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
02599 #define Sdmmc1ClockSelection               SdioClockSelection
02600 #define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
02601 #define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
02602 #define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
02603 #define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
02604 #define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
02605 #endif
02606 
02607 #if defined(STM32F7) || defined(STM32L4)
02608 #define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
02609 #define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
02610 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
02611 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
02612 #define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
02613 #define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
02614 #define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
02615 #define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
02616 #define SdioClockSelection                 Sdmmc1ClockSelection
02617 #define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
02618 #define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
02619 #define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE  
02620 #endif
02621 
02622 #if defined(STM32F7)
02623 #define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
02624 #define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
02625 #endif
02626 
02627 #define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
02628 #define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
02629 
02630 #define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
02631 
02632 #define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
02633 #define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
02634 #define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
02635 #define IS_RCC_HCLK_DIV             IS_RCC_PCLK
02636 #define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
02637 
02638 #define RCC_IT_HSI14                RCC_IT_HSI14RDY
02639 
02640 #if defined(STM32L0)
02641 #define RCC_IT_LSECSS              RCC_IT_CSSLSE 
02642 #define RCC_IT_CSS                 RCC_IT_CSSHSE
02643 #endif
02644 
02645 #define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
02646 #define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
02647 #define RCC_MCO_NODIV               RCC_MCODIV_1
02648 #define RCC_MCO_DIV1                RCC_MCODIV_1
02649 #define RCC_MCO_DIV2                RCC_MCODIV_2
02650 #define RCC_MCO_DIV4                RCC_MCODIV_4
02651 #define RCC_MCO_DIV8                RCC_MCODIV_8
02652 #define RCC_MCO_DIV16               RCC_MCODIV_16
02653 #define RCC_MCO_DIV32               RCC_MCODIV_32
02654 #define RCC_MCO_DIV64               RCC_MCODIV_64
02655 #define RCC_MCO_DIV128              RCC_MCODIV_128
02656 #define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
02657 #define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
02658 #define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
02659 #define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
02660 #define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
02661 #define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
02662 #define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
02663 #define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
02664 #define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
02665 #define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
02666 #define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
02667 
02668 #define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
02669 
02670 #define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
02671 #define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
02672 #define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
02673 #define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
02674 #define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
02675 #define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
02676 #define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
02677 #define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
02678 
02679 #define HSION_BitNumber        RCC_HSION_BIT_NUMBER
02680 #define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
02681 #define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
02682 #define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
02683 #define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
02684 #define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
02685 #define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
02686 #define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
02687 #define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
02688 #define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
02689 #define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
02690 #define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
02691 #define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
02692 #define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
02693 #define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
02694 #define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
02695 #define LSION_BitNumber        RCC_LSION_BIT_NUMBER
02696 #define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
02697 #define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
02698 #define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
02699 #define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
02700 #define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
02701 #define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
02702 #define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
02703 #define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
02704 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
02705 #define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
02706 #define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
02707 #define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
02708 #define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
02709 #define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
02710 #define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
02711 
02712 #define CR_HSION_BB            RCC_CR_HSION_BB
02713 #define CR_CSSON_BB            RCC_CR_CSSON_BB
02714 #define CR_PLLON_BB            RCC_CR_PLLON_BB
02715 #define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
02716 #define CR_MSION_BB            RCC_CR_MSION_BB
02717 #define CSR_LSION_BB           RCC_CSR_LSION_BB
02718 #define CSR_LSEON_BB           RCC_CSR_LSEON_BB
02719 #define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
02720 #define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
02721 #define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
02722 #define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
02723 #define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
02724 #define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
02725 #define CR_HSEON_BB            RCC_CR_HSEON_BB
02726 #define CSR_RMVF_BB            RCC_CSR_RMVF_BB
02727 #define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
02728 #define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
02729 
02730 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
02731 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
02732 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
02733 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
02734 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
02735 
02736 #define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
02737 
02738 #define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
02739 #define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
02740 
02741 #define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
02742 #define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
02743 #define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
02744 #define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
02745 #define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
02746 #define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
02747 
02748 #define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
02749 #define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
02750 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
02751 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
02752 #define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
02753 #define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
02754 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
02755 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
02756 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
02757 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
02758 #define DfsdmClockSelection         Dfsdm1ClockSelection
02759 #define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
02760 #define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK
02761 #define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
02762 #define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
02763 #define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
02764 
02765 /**
02766   * @}
02767   */
02768 
02769 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
02770   * @{
02771   */
02772 #define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)                                       
02773 
02774 /**
02775   * @}
02776   */
02777   
02778 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
02779   * @{
02780   */
02781   
02782 #define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
02783 #define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
02784 #define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
02785 
02786 #if defined (STM32F1)
02787 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
02788 
02789 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
02790 
02791 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
02792 
02793 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
02794 
02795 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
02796 #else
02797 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
02798                                                    (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
02799                                                       __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
02800 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
02801                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
02802                                                       __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
02803 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
02804                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
02805                                                       __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
02806 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
02807                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
02808                                                       __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
02809 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
02810                                                       (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
02811                                                           __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
02812 #endif   /* STM32F1 */
02813 
02814 #define IS_ALARM                                  IS_RTC_ALARM
02815 #define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
02816 #define IS_TAMPER                                 IS_RTC_TAMPER
02817 #define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
02818 #define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER 
02819 #define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
02820 #define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
02821 #define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
02822 #define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
02823 #define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
02824 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
02825 #define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
02826 #define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
02827 #define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
02828 
02829 #define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
02830 #define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
02831 
02832 /**
02833   * @}
02834   */
02835 
02836 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
02837   * @{
02838   */
02839 
02840 #define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
02841 #define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
02842 
02843 #if defined(STM32F4)
02844 #define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
02845 #define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY     
02846 #define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED   
02847 #define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION  
02848 #define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND   
02849 #define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT     
02850 #define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED   
02851 #define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE      
02852 #define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE     
02853 #define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE  
02854 #define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL  
02855 #define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT   
02856 #define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT  
02857 #define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG    
02858 #define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG  
02859 #define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT      
02860 #define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT    
02861 #define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS          
02862 #define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT           
02863 #define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
02864 /* alias CMSIS */
02865 #define  SDMMC1_IRQn                SDIO_IRQn
02866 #define  SDMMC1_IRQHandler          SDIO_IRQHandler
02867 #endif
02868 
02869 #if defined(STM32F7) || defined(STM32L4)
02870 #define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
02871 #define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY    
02872 #define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED  
02873 #define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
02874 #define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
02875 #define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
02876 #define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
02877 #define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
02878 #define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
02879 #define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
02880 #define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
02881 #define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
02882 #define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
02883 #define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
02884 #define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
02885 #define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
02886 #define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
02887 #define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
02888 #define  SDIO_CMD0TIMEOUT             SDMMC_CMD0TIMEOUT
02889 #define  SD_SDIO_SEND_IF_COND         SD_SDMMC_SEND_IF_COND
02890 /* alias CMSIS for compatibilities */
02891 #define  SDIO_IRQn                  SDMMC1_IRQn
02892 #define  SDIO_IRQHandler            SDMMC1_IRQHandler
02893 #endif
02894 /**
02895   * @}
02896   */
02897 
02898 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
02899   * @{
02900   */
02901 
02902 #define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
02903 #define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
02904 #define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
02905 #define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
02906 #define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
02907 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
02908 
02909 #define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
02910 #define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
02911 
02912 #define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE                  
02913 
02914 /**
02915   * @}
02916   */
02917 
02918 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
02919   * @{
02920   */
02921 #define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
02922 #define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
02923 #define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
02924 #define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
02925 #define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
02926 #define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
02927 #define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
02928 #define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
02929 /**
02930   * @}
02931   */
02932 
02933 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
02934   * @{
02935   */
02936 
02937 #define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
02938 #define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
02939 #define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
02940 
02941 /**
02942   * @}
02943   */
02944   
02945 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
02946   * @{
02947   */
02948 
02949 #define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
02950 #define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
02951 #define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
02952 #define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
02953 
02954 #define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
02955 
02956 #define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE                  
02957 #define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE                  
02958 
02959 /**
02960   * @}
02961   */
02962 
02963 
02964 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
02965   * @{
02966   */
02967 
02968 #define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
02969 #define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
02970 #define __USART_ENABLE                  __HAL_USART_ENABLE
02971 #define __USART_DISABLE                 __HAL_USART_DISABLE
02972 
02973 #define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
02974 #define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
02975 
02976 /**
02977   * @}
02978   */
02979 
02980 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
02981   * @{
02982   */
02983 #define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
02984 
02985 #define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
02986 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
02987 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
02988 #define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
02989 
02990 #define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
02991 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
02992 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
02993 #define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
02994 
02995 #define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
02996 #define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
02997 #define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
02998 #define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
02999 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
03000 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
03001 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
03002 
03003 #define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
03004 #define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
03005 #define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
03006 #define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
03007 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
03008 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
03009 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
03010 #define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
03011 
03012 #define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
03013 #define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
03014 #define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
03015 #define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
03016 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
03017 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
03018 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
03019 #define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
03020 
03021 #define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
03022 #define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
03023 
03024 #define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
03025 #define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
03026 /**
03027   * @}
03028   */
03029 
03030 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
03031   * @{
03032   */
03033 #define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
03034 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
03035 
03036 #define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
03037 #define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
03038 
03039 #define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
03040 
03041 #define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
03042 #define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
03043 #define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
03044 #define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
03045 #define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
03046 #define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
03047 #define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
03048 #define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
03049 #define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
03050 #define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
03051 #define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
03052 #define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
03053 
03054 #define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
03055 /**
03056   * @}
03057   */
03058 
03059 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
03060   * @{
03061   */
03062   
03063 #define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
03064 #define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
03065 #define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
03066 #define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
03067 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
03068 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
03069 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
03070 
03071 #define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE 
03072 #define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
03073 #define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
03074 /**
03075   * @}
03076   */
03077 
03078 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
03079   * @{
03080   */
03081 #define __HAL_LTDC_LAYER LTDC_LAYER
03082 /**
03083   * @}
03084   */
03085 
03086 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
03087   * @{
03088   */
03089 #define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
03090 #define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
03091 #define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
03092 #define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
03093 #define SAI_STREOMODE                     SAI_STEREOMODE
03094 #define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
03095 #define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
03096 #define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
03097 #define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
03098 #define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
03099 #define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
03100 #define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
03101 #define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
03102 #define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
03103 /**
03104   * @}
03105   */
03106 
03107 
03108 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
03109   * @{
03110   */
03111   
03112 /**
03113   * @}
03114   */
03115 
03116 #ifdef __cplusplus
03117 }
03118 #endif
03119 
03120 #endif /* ___STM32_HAL_LEGACY */
03121 
03122 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
03123