sdk.c

00001 /**
00002  * @file    sdk.c
00003  * @brief
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2017-2017, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 #include "stm32f1xx.h"
00023 #include "DAP_config.h"
00024 #include "gpio.h"
00025 #include "daplink.h"
00026 #include "util.h"
00027 #include "cortex_m.h"
00028 
00029 TIM_HandleTypeDef timer;
00030 uint32_t time_count;
00031 
00032 static uint32_t tim2_clk_div(uint32_t apb1clkdiv);
00033 
00034 /**
00035     * @brief  Switch the PLL source from HSI to HSE bypass, and select the PLL as SYSCLK
00036   *         source.
00037   *         The system Clock is configured as follow :
00038   *            System Clock source            = PLL (HSE bypass)
00039   *            SYSCLK(Hz)                     = 72000000
00040   *            HCLK(Hz)                       = 72000000
00041   *            AHB Prescaler                  = 1
00042   *            APB1 Prescaler                 = 2
00043   *            APB2 Prescaler                 = 1
00044   *            HSE Frequency(Hz)              = 8000000
00045   *            HSE PREDIV1                    = 1
00046   *            PLLMUL                         = 9
00047   *            Flash Latency(WS)              = 2
00048   * @param  None
00049   * @retval None
00050   */
00051 void sdk_init()
00052 {
00053     RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
00054     RCC_OscInitTypeDef RCC_OscInitStruct = {0};
00055 
00056     SystemCoreClockUpdate();
00057     HAL_Init();
00058 
00059     /* Select HSI as system clock source to allow modification of the PLL configuration */
00060     RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
00061     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
00062     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
00063         /* Initialization Error */
00064         util_assert(0);
00065     }
00066 
00067     /* Enable HSE bypass Oscillator, select it as PLL source and finally activate the PLL */
00068     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
00069     RCC_OscInitStruct.HSEState = RCC_CR_HSEON;
00070     RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
00071     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
00072     RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
00073     RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
00074     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
00075         /* Initialization Error */
00076         util_assert(0);
00077     }
00078 
00079     /* Select the PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
00080     RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
00081     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
00082     RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
00083     RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
00084     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
00085     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
00086         /* Initialization Error */
00087         util_assert(0);
00088     }
00089 }
00090 
00091 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
00092 {
00093     HAL_StatusTypeDef ret;
00094     RCC_ClkInitTypeDef clk_init;
00095     uint32_t unused;
00096     uint32_t prescaler;
00097     uint32_t source_clock;
00098 
00099     HAL_RCC_GetClockConfig(&clk_init, &unused);
00100 
00101     /* Compute the prescaler value to have TIMx counter clock equal to 4000 Hz */
00102     source_clock = SystemCoreClock / tim2_clk_div(clk_init.APB1CLKDivider);
00103     prescaler = (uint32_t)(source_clock / 4000) - 1;
00104 
00105     /* Set TIMx instance */
00106     timer.Instance = TIM2;
00107 
00108     timer.Init.Period            = 0xFFFF;
00109     timer.Init.Prescaler         = prescaler;
00110     timer.Init.ClockDivision     = 0;
00111     timer.Init.CounterMode       = TIM_COUNTERMODE_UP;
00112     timer.Init.RepetitionCounter = 0;
00113 
00114     __HAL_RCC_TIM2_CLK_ENABLE();
00115 
00116     ret = HAL_TIM_Base_DeInit(&timer);
00117     if (ret != HAL_OK) {
00118         return ret;
00119     }
00120 
00121     time_count = 0;
00122     ret = HAL_TIM_Base_Init(&timer);
00123     if (ret != HAL_OK) {
00124         return ret;
00125     }
00126 
00127     ret = HAL_TIM_Base_Start(&timer);
00128     if (ret != HAL_OK) {
00129         return ret;
00130     }
00131 
00132     return HAL_OK;
00133 }
00134 
00135 
00136 void HAL_IncTick(void)
00137 {
00138     // Do nothing
00139 }
00140 
00141 uint32_t HAL_GetTick(void)
00142 {
00143     cortex_int_state_t state;
00144     state = cortex_int_get_and_disable();
00145     const uint32_t ticks = __HAL_TIM_GET_COUNTER(&timer) / 4;
00146     time_count += (ticks - time_count) & 0x3FFF;
00147     cortex_int_restore(state);
00148     return time_count;
00149 }
00150 
00151 void HAL_SuspendTick(void)
00152 {
00153     HAL_TIM_Base_Start(&timer);
00154 }
00155 
00156 void HAL_ResumeTick(void)
00157 {
00158     HAL_TIM_Base_Stop(&timer);
00159 }
00160 
00161 static uint32_t tim2_clk_div(uint32_t apb1clkdiv)
00162 {
00163     switch (apb1clkdiv) {
00164         case RCC_CFGR_PPRE1_DIV2:
00165             return 1;
00166         case RCC_CFGR_PPRE1_DIV4:
00167             return 2;
00168         case RCC_CFGR_PPRE1_DIV8:
00169             return 4;
00170         case RCC_CFGR_PPRE1_DIV16:
00171             return 8;
00172         default:
00173             return 1;
00174     }
00175 }