DAP_config.h

00001 /**
00002  * @file    DAP_config.h
00003  * @brief
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 #ifndef __DAP_CONFIG_H__
00023 #define __DAP_CONFIG_H__
00024 
00025 #include "stm32f1xx.h"
00026 #include "stdint.h"
00027 #include "cmsis_os2.h"
00028 #include "IO_Config.h"
00029 #include "uart.h"
00030 //#include "debug_cm.h"
00031 //#include "swd_host.h"
00032 //**************************************************************************************************
00033 /**
00034 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
00035 \ingroup DAP_ConfigIO_gr
00036 @{
00037 Provides definitions about:
00038  - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
00039  - Debug Unit communication packet size.
00040  - Debug Access Port communication mode (JTAG or SWD).
00041  - Optional information about a connected Target Device (for Evaluation Boards).
00042 */
00043 
00044 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
00045 /// This value is used to calculate the SWD/JTAG clock speed.
00046 #define CPU_CLOCK               SystemCoreClock        ///< Specifies the CPU Clock in Hz
00047 
00048 /// Number of processor cycles for I/O Port write operations.
00049 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
00050 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
00051 /// requrie 2 processor cycles for a I/O Port Write operation.  If the Debug Unit uses
00052 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
00053 /// requrired.
00054 #define IO_PORT_WRITE_CYCLES    2               ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
00055 
00056 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
00057 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00058 #define DAP_SWD                 1               ///< SWD Mode:  1 = available, 0 = not available
00059 
00060 /// Indicate that JTAG communication mode is available at the Debug Port.
00061 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00062 #define DAP_JTAG                0               ///< JTAG Mode: 1 = available, 0 = not available.
00063 
00064 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
00065 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
00066 #define DAP_JTAG_DEV_CNT        0               ///< Maximum number of JTAG devices on scan chain
00067 
00068 /// Default communication mode on the Debug Access Port.
00069 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
00070 #define DAP_DEFAULT_PORT        1               ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
00071 
00072 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
00073 /// Used to initialize the default SWD/JTAG clock frequency.
00074 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
00075 #define DAP_DEFAULT_SWJ_CLOCK   5000000         ///< Default SWD/JTAG clock frequency in Hz.
00076 
00077 /// Maximum Package Size for Command and Response data.
00078 /// This configuration settings is used to optimized the communication performance with the
00079 /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
00080 #define DAP_PACKET_SIZE        64              ///< USB: 64 = Full-Speed, 1024 = High-Speed.
00081 
00082 /// Maximum Package Buffers for Command and Response data.
00083 /// This configuration settings is used to optimized the communication performance with the
00084 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
00085 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
00086 #define DAP_PACKET_COUNT       4              ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
00087 
00088 /// Indicate that UART Serial Wire Output (SWO) trace is available.
00089 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00090 #define SWO_UART                0               ///< SWO UART:  1 = available, 0 = not available
00091 
00092 /// Maximum SWO UART Baudrate
00093 #define SWO_UART_MAX_BAUDRATE   10000000U       ///< SWO UART Maximum Baudrate in Hz
00094 
00095 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
00096 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00097 #define SWO_MANCHESTER          0               ///< SWO Manchester:  1 = available, 0 = not available
00098 
00099 /// SWO Trace Buffer Size.
00100 #define SWO_BUFFER_SIZE         4096U           ///< SWO Trace Buffer Size in bytes (must be 2^n)
00101 
00102 /// SWO Streaming Trace.
00103 #define SWO_STREAM              0               ///< SWO Streaming Trace: 1 = available, 0 = not available.
00104 
00105 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
00106 #define TIMESTAMP_CLOCK         1000000U      ///< Timestamp clock in Hz (0 = timestamps not supported).
00107 
00108 
00109 /// Debug Unit is connected to fixed Target Device.
00110 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
00111 /// known device.  In this case a Device Vendor and Device Name string is stored which
00112 /// may be used by the debugger or IDE to configure device parameters.
00113 #define TARGET_DEVICE_FIXED     0               ///< Target Device: 1 = known, 0 = unknown;
00114 
00115 #if TARGET_DEVICE_FIXED
00116 #define TARGET_DEVICE_VENDOR    ""              ///< String indicating the Silicon Vendor
00117 #define TARGET_DEVICE_NAME      ""              ///< String indicating the Target Device
00118 #endif
00119 
00120 ///@}
00121 
00122 
00123 __STATIC_INLINE void pin_out_init(GPIO_TypeDef* GPIOx, uint8_t pin_bit)
00124 {
00125     if(pin_bit >= 8)
00126     {
00127         GPIOx->CRH &= ~(0x0000000F << ((pin_bit-8) << 2));
00128         GPIOx->CRH |= ( ((uint32_t)(0x00|0x03) & 0x0F) << ((pin_bit-8) << 2) );
00129     }
00130     else
00131     {
00132         GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
00133         GPIOx->CRL |= ( ((uint32_t)(0x00|0x03) & 0x0F) << ((pin_bit) << 2) );
00134     }
00135 }
00136 
00137 __STATIC_INLINE void pin_out_od_init(GPIO_TypeDef* GPIOx, uint8_t pin_bit)
00138 {
00139     if(pin_bit >= 8)
00140     {
00141         GPIOx->CRH &= ~(0x0000000F << ((pin_bit-8) << 2));
00142         GPIOx->CRH |= ( ((uint32_t)(0x04|0x03) & 0x0F) << ((pin_bit-8) << 2) );
00143     }
00144     else
00145     {
00146         GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
00147         GPIOx->CRL |= ( ((uint32_t)(0x04|0x03) & 0x0F) << ((pin_bit) << 2) );
00148     }
00149 }
00150 
00151 __STATIC_INLINE void pin_in_init(GPIO_TypeDef* GPIOx, uint8_t pin_bit, uint8_t mode)
00152 {
00153     uint8_t config;
00154     if(mode == 1)
00155         config = 0x08; //Up
00156     else if(mode == 2)
00157         config = 0x08; //down
00158     else
00159         config = 0x00; //GPIO_Mode_AIN
00160 
00161     if(pin_bit >= 8)
00162     {
00163         GPIOx->CRH &= ~(0x0000000F << ((pin_bit-8) << 2));
00164         GPIOx->CRH |= ( ((uint32_t)(config) & 0x0F) << ((pin_bit-8) << 2) );
00165         if(mode == 1)
00166             GPIOx->BSRR = (((uint32_t)0x01) << pin_bit);
00167         else if(mode == 2)
00168             GPIOx->BRR = (((uint32_t)0x01) << pin_bit);
00169     }
00170     else
00171     {
00172         GPIOx->CRL &= ~(0x0000000F << ((pin_bit) << 2));
00173         GPIOx->CRL |= ( ((uint32_t)(config) & 0x0F) << ((pin_bit) << 2) );
00174         if(mode == 1)
00175             GPIOx->BSRR = (((uint32_t)0x01) << pin_bit);
00176         else if(mode == 2)
00177             GPIOx->BRR = (((uint32_t)0x01) << pin_bit);
00178     }
00179 }
00180 //**************************************************************************************************
00181 /**
00182 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
00183 \ingroup DAP_ConfigIO_gr
00184 @{
00185 
00186 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
00187 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
00188 interface of a device. The following I/O Pins are provided:
00189 
00190 JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mode
00191 ---------------------------- | -------------------- | ---------------------------------------------
00192 TCK: Test Clock              | SWCLK: Clock         | Output Push/Pull
00193 TMS: Test Mode Select        | SWDIO: Data I/O      | Output Push/Pull; Input (for receiving data)
00194 TDI: Test Data Input         |                      | Output Push/Pull
00195 TDO: Test Data Output        |                      | Input
00196 nTRST: Test Reset (optional) |                      | Output Open Drain with pull-up resistor
00197 nRESET: Device Reset         | nRESET: Device Reset | Output Open Drain with pull-up resistor
00198 
00199 
00200 DAP Hardware I/O Pin Access Functions
00201 -------------------------------------
00202 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
00203 these I/O Pins.
00204 
00205 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
00206 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
00207 peripherals that can independently write/read a single I/O pin without affecting any other pins
00208 of the same I/O port. The following SWDIO I/O Pin functions are provided:
00209  - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
00210  - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
00211  - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
00212  - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
00213 */
00214 
00215 
00216 // Configure DAP I/O pins ------------------------------
00217 
00218 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
00219 Configures the DAP Hardware I/O pins for JTAG mode:
00220  - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
00221  - TDO to input mode.
00222 */
00223 __STATIC_INLINE void PORT_JTAG_SETUP(void)
00224 {
00225 #if (DAP_JTAG != 0)
00226 
00227 #endif
00228 }
00229 
00230 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
00231 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
00232  - SWCLK, SWDIO, nRESET to output mode and set to default high level.
00233  - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
00234 */
00235 __STATIC_INLINE void PORT_SWD_SETUP(void)
00236 {
00237     // Set SWCLK HIGH
00238     pin_out_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit);
00239     SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
00240     // Set SWDIO HIGH
00241     pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
00242     SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
00243 
00244     pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 1);
00245     // Set RESET HIGH
00246     pin_out_od_init(nRESET_PIN_PORT, nRESET_PIN_Bit);//TODO - fix reset logic
00247     nRESET_PIN_PORT->BSRR = nRESET_PIN;
00248 }
00249 
00250 /** Disable JTAG/SWD I/O Pins.
00251 Disables the DAP Hardware I/O pins which configures:
00252  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
00253 */
00254 __STATIC_INLINE void PORT_OFF(void)
00255 {
00256     pin_in_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit, 0);
00257     pin_in_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit, 0);
00258     pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 0);
00259 }
00260 
00261 // SWCLK/TCK I/O pin -------------------------------------
00262 
00263 /** SWCLK/TCK I/O pin: Get Input.
00264 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
00265 */
00266 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
00267 {
00268     return ((SWCLK_TCK_PIN_PORT->ODR & SWCLK_TCK_PIN) ? 1 : 0);
00269 }
00270 
00271 /** SWCLK/TCK I/O pin: Set Output to High.
00272 Set the SWCLK/TCK DAP hardware I/O pin to high level.
00273 */
00274 __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
00275 {
00276     SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
00277 }
00278 
00279 /** SWCLK/TCK I/O pin: Set Output to Low.
00280 Set the SWCLK/TCK DAP hardware I/O pin to low level.
00281 */
00282 __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
00283 {
00284     SWCLK_TCK_PIN_PORT->BRR = SWCLK_TCK_PIN;
00285 }
00286 
00287 // SWDIO/TMS Pin I/O --------------------------------------
00288 
00289 /** SWDIO/TMS I/O pin: Get Input.
00290 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
00291 */
00292 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
00293 {
00294     return ((SWDIO_IN_PIN_PORT->IDR & SWDIO_IN_PIN) ? 1 : 0);
00295 }
00296 
00297 /** SWDIO/TMS I/O pin: Set Output to High.
00298 Set the SWDIO/TMS DAP hardware I/O pin to high level.
00299 */
00300 __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
00301 {
00302     SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
00303 }
00304 
00305 /** SWDIO/TMS I/O pin: Set Output to Low.
00306 Set the SWDIO/TMS DAP hardware I/O pin to low level.
00307 */
00308 __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
00309 {
00310     SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
00311 }
00312 
00313 /** SWDIO I/O pin: Get Input (used in SWD mode only).
00314 \return Current status of the SWDIO DAP hardware I/O pin.
00315 */
00316 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
00317 {
00318     return ((SWDIO_IN_PIN_PORT->IDR & SWDIO_IN_PIN) ? 1 : 0);
00319 }
00320 
00321 /** SWDIO I/O pin: Set Output (used in SWD mode only).
00322 \param bit Output value for the SWDIO DAP hardware I/O pin.
00323 */
00324 __STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
00325 {
00326     if (bit & 1)
00327         SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
00328     else
00329         SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
00330 }
00331 
00332 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
00333 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
00334 called prior \ref PIN_SWDIO_OUT function calls.
00335 */
00336 __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
00337 {
00338     pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
00339     SWDIO_OUT_PIN_PORT->BRR = SWDIO_OUT_PIN;
00340 }
00341 
00342 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
00343 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
00344 called prior \ref PIN_SWDIO_IN function calls.
00345 */
00346 __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
00347 {
00348     pin_in_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit, 0);
00349     SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
00350 }
00351 
00352 
00353 // TDI Pin I/O ---------------------------------------------
00354 
00355 /** TDI I/O pin: Get Input.
00356 \return Current status of the TDI DAP hardware I/O pin.
00357 */
00358 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
00359 {
00360     return (0);   // Not available
00361 }
00362 
00363 /** TDI I/O pin: Set Output.
00364 \param bit Output value for the TDI DAP hardware I/O pin.
00365 */
00366 __STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
00367 {
00368     ;             // Not available
00369 }
00370 
00371 
00372 // TDO Pin I/O ---------------------------------------------
00373 
00374 /** TDO I/O pin: Get Input.
00375 \return Current status of the TDO DAP hardware I/O pin.
00376 */
00377 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
00378 {
00379     return (0);   // Not available
00380 }
00381 
00382 
00383 // nTRST Pin I/O -------------------------------------------
00384 
00385 /** nTRST I/O pin: Get Input.
00386 \return Current status of the nTRST DAP hardware I/O pin.
00387 */
00388 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
00389 {
00390     return (0);   // Not available
00391 }
00392 
00393 /** nTRST I/O pin: Set Output.
00394 \param bit JTAG TRST Test Reset pin status:
00395            - 0: issue a JTAG TRST Test Reset.
00396            - 1: release JTAG TRST Test Reset.
00397 */
00398 __STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
00399 {
00400     ;             // Not available
00401 }
00402 
00403 // nRESET Pin I/O------------------------------------------
00404 
00405 /** nRESET I/O pin: Get Input.
00406 \return Current status of the nRESET DAP hardware I/O pin.
00407 */
00408 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
00409 {
00410     return ((nRESET_PIN_PORT->IDR >> nRESET_PIN_Bit) & 1);
00411 }
00412 
00413 /** nRESET I/O pin: Set Output.
00414 \param bit target device hardware reset pin status:
00415            - 0: issue a device hardware reset.
00416            - 1: release device hardware reset.
00417 */
00418 // TODO - sw specific implementation should be created
00419 
00420 __STATIC_FORCEINLINE void     PIN_nRESET_OUT(uint32_t bit)
00421 {
00422     if (bit & 1)
00423         nRESET_PIN_PORT->BSRR = nRESET_PIN;
00424     else
00425         nRESET_PIN_PORT->BRR = nRESET_PIN;
00426 }
00427 
00428 //**************************************************************************************************
00429 /**
00430 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
00431 \ingroup DAP_ConfigIO_gr
00432 @{
00433 
00434 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
00435 
00436 It is recommended to provide the following LEDs for status indication:
00437  - Connect LED: is active when the DAP hardware is connected to a debugger.
00438  - Running LED: is active when the debugger has put the target device into running state.
00439 */
00440 
00441 /** Debug Unit: Set status of Connected LED.
00442 \param bit status of the Connect LED.
00443            - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
00444            - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
00445 */
00446 __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
00447 {
00448     if (bit & 1)
00449         CONNECTED_LED_PORT->BRR = CONNECTED_LED_PIN; // LED on
00450     else
00451         CONNECTED_LED_PORT->BSRR = CONNECTED_LED_PIN;// LED off
00452 }
00453 
00454 /** Debug Unit: Set status Target Running LED.
00455 \param bit status of the Target Running LED.
00456            - 1: Target Running LED ON: program execution in target started.
00457            - 0: Target Running LED OFF: program execution in target stopped.
00458 */
00459 __STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
00460 {
00461     ;             // Not available
00462 }
00463 
00464 ///@}
00465 
00466 
00467 //**************************************************************************************************
00468 /**
00469 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
00470 \ingroup DAP_ConfigIO_gr
00471 @{
00472 Access function for Test Domain Timer.
00473 
00474 The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
00475 default, the DWT timer is used.  The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
00476 
00477 */
00478 
00479 /** Get timestamp of Test Domain Timer.
00480 \return Current timestamp value.
00481 */
00482 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
00483   return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
00484 }
00485 
00486 ///@}
00487 
00488 
00489 //**************************************************************************************************
00490 /**
00491 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
00492 \ingroup DAP_ConfigIO_gr
00493 @{
00494 
00495 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
00496 */
00497 
00498 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
00499 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
00500 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
00501  - I/O clock system enabled.
00502  - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
00503  - for nTRST, nRESET a weak pull-up (if available) is enabled.
00504  - LED output pins are enabled and LEDs are turned off.
00505 */
00506 __STATIC_INLINE void DAP_SETUP(void)
00507 {
00508     /* Enable port clock */
00509     __HAL_RCC_GPIOA_CLK_ENABLE();
00510     __HAL_RCC_GPIOB_CLK_ENABLE();
00511     __HAL_RCC_GPIOC_CLK_ENABLE();
00512     __HAL_RCC_GPIOD_CLK_ENABLE();
00513     /* Configure I/O pin SWCLK */
00514     pin_out_init(SWCLK_TCK_PIN_PORT, SWCLK_TCK_PIN_Bit);
00515     SWCLK_TCK_PIN_PORT->BSRR = SWCLK_TCK_PIN;
00516 
00517     pin_out_init(SWDIO_OUT_PIN_PORT, SWDIO_OUT_PIN_Bit);
00518     SWDIO_OUT_PIN_PORT->BSRR = SWDIO_OUT_PIN;
00519 
00520     pin_in_init(SWDIO_IN_PIN_PORT, SWDIO_IN_PIN_Bit, 1);
00521 
00522     pin_out_od_init(nRESET_PIN_PORT, nRESET_PIN_Bit);
00523     nRESET_PIN_PORT->BSRR = nRESET_PIN;
00524 
00525     pin_out_init(CONNECTED_LED_PORT, CONNECTED_LED_PIN_Bit);
00526     CONNECTED_LED_PORT->BSRR = CONNECTED_LED_PIN;
00527 }
00528 
00529 /** Reset Target Device with custom specific I/O pin or command sequence.
00530 This function allows the optional implementation of a device specific reset sequence.
00531 It is called when the command \ref DAP_ResetTarget and is for example required
00532 when a device needs a time-critical unlock sequence that enables the debug port.
00533 \return 0 = no device specific reset sequence is implemented.\n
00534         1 = a device specific reset sequence is implemented.
00535 */
00536 __STATIC_INLINE uint32_t RESET_TARGET(void)
00537 {
00538     return (0);              // change to '1' when a device reset sequence is implemented
00539 }
00540 
00541 ///@}
00542 
00543 
00544 #endif /* __DAP_CONFIG_H__ */