sam3u2c.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) %copyright_year%, Atmel Corporation                                        */
00006 /*                                                                              */
00007 /* All rights reserved.                                                         */
00008 /*                                                                              */
00009 /* Redistribution and use in source and binary forms, with or without           */
00010 /* modification, are permitted provided that the following condition is met:    */
00011 /*                                                                              */
00012 /* - Redistributions of source code must retain the above copyright notice,     */
00013 /* this list of conditions and the disclaimer below.                            */
00014 /*                                                                              */
00015 /* Atmel's name may not be used to endorse or promote products derived from     */
00016 /* this software without specific prior written permission.                     */
00017 /*                                                                              */
00018 /* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
00028 /* ---------------------------------------------------------------------------- */
00029 
00030 #ifndef _SAM3U2C_
00031 #define _SAM3U2C_
00032 
00033 /** \addtogroup SAM3U2C_definitions SAM3U2C definitions
00034   This file defines all structures and symbols for SAM3U2C:
00035     - registers and bitfields
00036     - peripheral base address
00037     - peripheral ID
00038     - PIO definitions
00039 */
00040 /*@{*/
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif 
00045 
00046 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00047 #include "stdint.h"
00048 #ifndef __cplusplus
00049 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
00050 #else
00051 typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
00052 #endif
00053 typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
00054 typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
00055 #endif
00056 
00057 /* ************************************************************************** */
00058 /*   CMSIS DEFINITIONS FOR SAM3U2C */
00059 /* ************************************************************************** */
00060 /** \addtogroup SAM3U2C_cmsis CMSIS Definitions */
00061 /*@{*/
00062 
00063 /**< Interrupt Number Definition */
00064 typedef enum IRQn
00065 {
00066 /******  Cortex-M3 Processor Exceptions Numbers ******************************/
00067   NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
00068   MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
00069   BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
00070   UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
00071   SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
00072   DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
00073   PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
00074   SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
00075 /******  SAM3U2C specific Interrupt Numbers *********************************/
00076   
00077   SUPC_IRQn            =  0, /**<  0 SAM3U2C Supply Controller (SUPC) */
00078   RSTC_IRQn            =  1, /**<  1 SAM3U2C Reset Controller (RSTC) */
00079   RTC_IRQn             =  2, /**<  2 SAM3U2C Real Time Clock (RTC) */
00080   RTT_IRQn             =  3, /**<  3 SAM3U2C Real Time Timer (RTT) */
00081   WDT_IRQn             =  4, /**<  4 SAM3U2C Watchdog Timer (WDT) */
00082   PMC_IRQn             =  5, /**<  5 SAM3U2C Power Management Controller (PMC) */
00083   EFC0_IRQn            =  6, /**<  6 SAM3U2C Enhanced Embedded Flash Controller 0 (EFC0) */
00084   UART_IRQn            =  8, /**<  8 SAM3U2C Universal Asynchronous Receiver Transmitter (UART) */
00085   SMC_IRQn             =  9, /**<  9 SAM3U2C Static Memory Controller (SMC) */
00086   PIOA_IRQn            = 10, /**< 10 SAM3U2C Parallel I/O Controller A, (PIOA) */
00087   PIOB_IRQn            = 11, /**< 11 SAM3U2C Parallel I/O Controller B (PIOB) */
00088   USART0_IRQn          = 13, /**< 13 SAM3U2C USART 0 (USART0) */
00089   USART1_IRQn          = 14, /**< 14 SAM3U2C USART 1 (USART1) */
00090   USART2_IRQn          = 15, /**< 15 SAM3U2C USART 2 (USART2) */
00091   HSMCI_IRQn           = 17, /**< 17 SAM3U2C High Speed Multimedia Card Interface (HSMCI) */
00092   TWI0_IRQn            = 18, /**< 18 SAM3U2C Two-Wire Interface 0 (TWI0) */
00093   TWI1_IRQn            = 19, /**< 19 SAM3U2C Two-Wire Interface 1 (TWI1) */
00094   SPI_IRQn             = 20, /**< 20 SAM3U2C Serial Peripheral Interface (SPI) */
00095   SSC_IRQn             = 21, /**< 21 SAM3U2C Synchronous Serial Controller (SSC) */
00096   TC0_IRQn             = 22, /**< 22 SAM3U2C Timer Counter 0 (TC0) */
00097   TC1_IRQn             = 23, /**< 23 SAM3U2C Timer Counter 1 (TC1) */
00098   TC2_IRQn             = 24, /**< 24 SAM3U2C Timer Counter 2 (TC2) */
00099   PWM_IRQn             = 25, /**< 25 SAM3U2C Pulse Width Modulation Controller (PWM) */
00100   ADC12B_IRQn          = 26, /**< 26 SAM3U2C 12-bit ADC Controller (ADC12B) */
00101   ADC_IRQn             = 27, /**< 27 SAM3U2C 10-bit ADC Controller (ADC) */
00102   DMAC_IRQn            = 28, /**< 28 SAM3U2C DMA Controller (DMAC) */
00103   UDPHS_IRQn           = 29, /**< 29 SAM3U2C USB Device High Speed (UDPHS) */
00104 
00105   PERIPH_COUNT_IRQn    = 30  /**< Number of peripheral IDs */
00106 } IRQn_Type ;
00107 
00108 typedef struct _DeviceVectors
00109 {
00110   /* Stack pointer */
00111   void* pvStack;
00112   
00113   /* Cortex-M handlers */
00114   void* pfnReset_Handler;
00115   void* pfnNMI_Handler;
00116   void* pfnHardFault_Handler;
00117   void* pfnMemManage_Handler;
00118   void* pfnBusFault_Handler;
00119   void* pfnUsageFault_Handler;
00120   void* pfnReserved1_Handler;
00121   void* pfnReserved2_Handler;
00122   void* pfnReserved3_Handler;
00123   void* pfnReserved4_Handler;
00124   void* pfnSVC_Handler;
00125   void* pfnDebugMon_Handler;
00126   void* pfnReserved5_Handler;
00127   void* pfnPendSV_Handler;
00128   void* pfnSysTick_Handler;
00129 
00130   /* Peripheral handlers */
00131   void* pfnSUPC_Handler;   /*  0 Supply Controller */
00132   void* pfnRSTC_Handler;   /*  1 Reset Controller */
00133   void* pfnRTC_Handler;    /*  2 Real Time Clock */
00134   void* pfnRTT_Handler;    /*  3 Real Time Timer */
00135   void* pfnWDT_Handler;    /*  4 Watchdog Timer */
00136   void* pfnPMC_Handler;    /*  5 Power Management Controller */
00137   void* pfnEFC0_Handler;   /*  6 Enhanced Embedded Flash Controller 0 */
00138   void* pvReserved7;
00139   void* pfnUART_Handler;   /*  8 Universal Asynchronous Receiver Transmitter */
00140   void* pfnSMC_Handler;    /*  9 Static Memory Controller */
00141   void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A, */
00142   void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
00143   void* pvReserved12;
00144   void* pfnUSART0_Handler; /* 13 USART 0 */
00145   void* pfnUSART1_Handler; /* 14 USART 1 */
00146   void* pfnUSART2_Handler; /* 15 USART 2 */
00147   void* pvReserved16;
00148   void* pfnHSMCI_Handler;  /* 17 High Speed Multimedia Card Interface */
00149   void* pfnTWI0_Handler;   /* 18 Two-Wire Interface 0 */
00150   void* pfnTWI1_Handler;   /* 19 Two-Wire Interface 1 */
00151   void* pfnSPI_Handler;    /* 20 Serial Peripheral Interface */
00152   void* pfnSSC_Handler;    /* 21 Synchronous Serial Controller */
00153   void* pfnTC0_Handler;    /* 22 Timer Counter 0 */
00154   void* pfnTC1_Handler;    /* 23 Timer Counter 1 */
00155   void* pfnTC2_Handler;    /* 24 Timer Counter 2 */
00156   void* pfnPWM_Handler;    /* 25 Pulse Width Modulation Controller */
00157   void* pfnADC12B_Handler; /* 26 12-bit ADC Controller */
00158   void* pfnADC_Handler;    /* 27 10-bit ADC Controller */
00159   void* pfnDMAC_Handler;   /* 28 DMA Controller */
00160   void* pfnUDPHS_Handler;  /* 29 USB Device High Speed */
00161 } DeviceVectors;
00162 
00163 /* Cortex-M3 core handlers */
00164 void Reset_Handler      ( void );
00165 void NMI_Handler        ( void );
00166 void HardFault_Handler  ( void );
00167 void MemManage_Handler  ( void );
00168 void BusFault_Handler   ( void );
00169 void UsageFault_Handler ( void );
00170 void SVC_Handler        ( void );
00171 void DebugMon_Handler   ( void );
00172 void PendSV_Handler     ( void );
00173 void SysTick_Handler    ( void );
00174 
00175 /* Peripherals handlers */
00176 void ADC_Handler        ( void );
00177 void ADC12B_Handler     ( void );
00178 void DMAC_Handler       ( void );
00179 void EFC0_Handler       ( void );
00180 void HSMCI_Handler      ( void );
00181 void PIOA_Handler       ( void );
00182 void PIOB_Handler       ( void );
00183 void PMC_Handler        ( void );
00184 void PWM_Handler        ( void );
00185 void RSTC_Handler       ( void );
00186 void RTC_Handler        ( void );
00187 void RTT_Handler        ( void );
00188 void SMC_Handler        ( void );
00189 void SPI_Handler        ( void );
00190 void SSC_Handler        ( void );
00191 void SUPC_Handler       ( void );
00192 void TC0_Handler        ( void );
00193 void TC1_Handler        ( void );
00194 void TC2_Handler        ( void );
00195 void TWI0_Handler       ( void );
00196 void TWI1_Handler       ( void );
00197 void UART_Handler       ( void );
00198 void UDPHS_Handler      ( void );
00199 void USART0_Handler     ( void );
00200 void USART1_Handler     ( void );
00201 void USART2_Handler     ( void );
00202 void WDT_Handler        ( void );
00203 
00204 /**
00205  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
00206  */
00207 
00208 #define __CM3_REV              0x0200 /**< SAM3U2C core revision number ([15:8] revision number, [7:0] patch number) */
00209 #define __MPU_PRESENT          1      /**< SAM3U2C does provide a MPU */
00210 #define __NVIC_PRIO_BITS       4      /**< SAM3U2C uses 4 Bits for the Priority Levels */
00211 #define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
00212 
00213 /*
00214  * \brief CMSIS includes
00215  */
00216 
00217 #include "core_cm3.h"
00218 #if !defined DONT_USE_CMSIS_INIT
00219 #include "system_SAM3U.h"
00220 #endif /* DONT_USE_CMSIS_INIT */
00221 
00222 /*@}*/
00223 
00224 /* ************************************************************************** */
00225 /**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U2C */
00226 /* ************************************************************************** */
00227 /** \addtogroup SAM3U2C_api Peripheral Software API */
00228 /*@{*/
00229 
00230 #include "component/adc.h"
00231 #include "component/adc12b.h"
00232 #include "component/chipid.h"
00233 #include "component/dmac.h"
00234 #include "component/efc.h"
00235 #include "component/gpbr.h"
00236 #include "component/hsmci.h"
00237 #include "component/matrix.h"
00238 #include "component/pdc.h"
00239 #include "component/pio.h"
00240 #include "component/pmc.h"
00241 #include "component/pwm.h"
00242 #include "component/rstc.h"
00243 #include "component/rtc.h"
00244 #include "component/rtt.h"
00245 #include "component/smc.h"
00246 #include "component/spi.h"
00247 #include "component/ssc.h"
00248 #include "component/supc.h"
00249 #include "component/tc.h"
00250 #include "component/twi.h"
00251 #include "component/uart.h"
00252 #include "component/udphs.h"
00253 #include "component/usart.h"
00254 #include "component/wdt.h"
00255 /*@}*/
00256 
00257 /* ************************************************************************** */
00258 /*   REGISTER ACCESS DEFINITIONS FOR SAM3U2C */
00259 /* ************************************************************************** */
00260 /** \addtogroup SAM3U2C_reg Registers Access Definitions */
00261 /*@{*/
00262 
00263 #include "instance/hsmci.h"
00264 #include "instance/ssc.h"
00265 #include "instance/spi.h"
00266 #include "instance/tc0.h"
00267 #include "instance/twi0.h"
00268 #include "instance/twi1.h"
00269 #include "instance/pwm.h"
00270 #include "instance/usart0.h"
00271 #include "instance/usart1.h"
00272 #include "instance/usart2.h"
00273 #include "instance/udphs.h"
00274 #include "instance/adc12b.h"
00275 #include "instance/adc.h"
00276 #include "instance/dmac.h"
00277 #include "instance/smc.h"
00278 #include "instance/matrix.h"
00279 #include "instance/pmc.h"
00280 #include "instance/uart.h"
00281 #include "instance/chipid.h"
00282 #include "instance/efc0.h"
00283 #include "instance/pioa.h"
00284 #include "instance/piob.h"
00285 #include "instance/rstc.h"
00286 #include "instance/supc.h"
00287 #include "instance/rtt.h"
00288 #include "instance/wdt.h"
00289 #include "instance/rtc.h"
00290 #include "instance/gpbr.h"
00291 /*@}*/
00292 
00293 /* ************************************************************************** */
00294 /*   PERIPHERAL ID DEFINITIONS FOR SAM3U2C */
00295 /* ************************************************************************** */
00296 /** \addtogroup SAM3U2C_id Peripheral Ids Definitions */
00297 /*@{*/
00298 
00299 #define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
00300 #define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
00301 #define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
00302 #define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
00303 #define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
00304 #define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
00305 #define ID_EFC0   ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
00306 #define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
00307 #define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
00308 #define ID_PIOA   (10) /**< \brief Parallel I/O Controller A, (PIOA) */
00309 #define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
00310 #define ID_USART0 (13) /**< \brief USART 0 (USART0) */
00311 #define ID_USART1 (14) /**< \brief USART 1 (USART1) */
00312 #define ID_USART2 (15) /**< \brief USART 2 (USART2) */
00313 #define ID_HSMCI  (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
00314 #define ID_TWI0   (18) /**< \brief Two-Wire Interface 0 (TWI0) */
00315 #define ID_TWI1   (19) /**< \brief Two-Wire Interface 1 (TWI1) */
00316 #define ID_SPI    (20) /**< \brief Serial Peripheral Interface (SPI) */
00317 #define ID_SSC    (21) /**< \brief Synchronous Serial Controller (SSC) */
00318 #define ID_TC0    (22) /**< \brief Timer Counter 0 (TC0) */
00319 #define ID_TC1    (23) /**< \brief Timer Counter 1 (TC1) */
00320 #define ID_TC2    (24) /**< \brief Timer Counter 2 (TC2) */
00321 #define ID_PWM    (25) /**< \brief Pulse Width Modulation Controller (PWM) */
00322 #define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
00323 #define ID_ADC    (27) /**< \brief 10-bit ADC Controller (ADC) */
00324 #define ID_DMAC   (28) /**< \brief DMA Controller (DMAC) */
00325 #define ID_UDPHS  (29) /**< \brief USB Device High Speed (UDPHS) */
00326 
00327 #define ID_PERIPH_COUNT (30) /**< \brief Number of peripheral IDs */
00328 /*@}*/
00329 
00330 /* ************************************************************************** */
00331 /*   BASE ADDRESS DEFINITIONS FOR SAM3U2C */
00332 /* ************************************************************************** */
00333 /** \addtogroup SAM3U2C_base Peripheral Base Address Definitions */
00334 /*@{*/
00335 
00336 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00337 #define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
00338 #define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
00339 #define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
00340 #define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
00341 #define TWI0       (0x40084000U) /**< \brief (TWI0      ) Base Address */
00342 #define PDC_TWI0   (0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
00343 #define TWI1       (0x40088000U) /**< \brief (TWI1      ) Base Address */
00344 #define PDC_TWI1   (0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
00345 #define PWM        (0x4008C000U) /**< \brief (PWM       ) Base Address */
00346 #define PDC_PWM    (0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
00347 #define USART0     (0x40090000U) /**< \brief (USART0    ) Base Address */
00348 #define PDC_USART0 (0x40090100U) /**< \brief (PDC_USART0) Base Address */
00349 #define USART1     (0x40094000U) /**< \brief (USART1    ) Base Address */
00350 #define PDC_USART1 (0x40094100U) /**< \brief (PDC_USART1) Base Address */
00351 #define USART2     (0x40098000U) /**< \brief (USART2    ) Base Address */
00352 #define PDC_USART2 (0x40098100U) /**< \brief (PDC_USART2) Base Address */
00353 #define UDPHS      (0x400A4000U) /**< \brief (UDPHS     ) Base Address */
00354 #define ADC12B     (0x400A8000U) /**< \brief (ADC12B    ) Base Address */
00355 #define PDC_ADC12B (0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
00356 #define ADC        (0x400AC000U) /**< \brief (ADC       ) Base Address */
00357 #define PDC_ADC    (0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
00358 #define DMAC       (0x400B0000U) /**< \brief (DMAC      ) Base Address */
00359 #define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
00360 #define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
00361 #define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
00362 #define UART       (0x400E0600U) /**< \brief (UART      ) Base Address */
00363 #define PDC_UART   (0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
00364 #define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
00365 #define EFC0       (0x400E0800U) /**< \brief (EFC0      ) Base Address */
00366 #define PIOA       (0x400E0C00U) /**< \brief (PIOA      ) Base Address */
00367 #define PIOB       (0x400E0E00U) /**< \brief (PIOB      ) Base Address */
00368 #define RSTC       (0x400E1200U) /**< \brief (RSTC      ) Base Address */
00369 #define SUPC       (0x400E1210U) /**< \brief (SUPC      ) Base Address */
00370 #define RTT        (0x400E1230U) /**< \brief (RTT       ) Base Address */
00371 #define WDT        (0x400E1250U) /**< \brief (WDT       ) Base Address */
00372 #define RTC        (0x400E1260U) /**< \brief (RTC       ) Base Address */
00373 #define GPBR       (0x400E1290U) /**< \brief (GPBR      ) Base Address */
00374 #else
00375 #define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
00376 #define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
00377 #define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
00378 #define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
00379 #define TWI0       ((Twi    *)0x40084000U) /**< \brief (TWI0      ) Base Address */
00380 #define PDC_TWI0   ((Pdc    *)0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
00381 #define TWI1       ((Twi    *)0x40088000U) /**< \brief (TWI1      ) Base Address */
00382 #define PDC_TWI1   ((Pdc    *)0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
00383 #define PWM        ((Pwm    *)0x4008C000U) /**< \brief (PWM       ) Base Address */
00384 #define PDC_PWM    ((Pdc    *)0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
00385 #define USART0     ((Usart  *)0x40090000U) /**< \brief (USART0    ) Base Address */
00386 #define PDC_USART0 ((Pdc    *)0x40090100U) /**< \brief (PDC_USART0) Base Address */
00387 #define USART1     ((Usart  *)0x40094000U) /**< \brief (USART1    ) Base Address */
00388 #define PDC_USART1 ((Pdc    *)0x40094100U) /**< \brief (PDC_USART1) Base Address */
00389 #define USART2     ((Usart  *)0x40098000U) /**< \brief (USART2    ) Base Address */
00390 #define PDC_USART2 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART2) Base Address */
00391 #define UDPHS      ((Udphs  *)0x400A4000U) /**< \brief (UDPHS     ) Base Address */
00392 #define ADC12B     ((Adc12b *)0x400A8000U) /**< \brief (ADC12B    ) Base Address */
00393 #define PDC_ADC12B ((Pdc    *)0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
00394 #define ADC        ((Adc    *)0x400AC000U) /**< \brief (ADC       ) Base Address */
00395 #define PDC_ADC    ((Pdc    *)0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
00396 #define DMAC       ((Dmac   *)0x400B0000U) /**< \brief (DMAC      ) Base Address */
00397 #define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
00398 #define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
00399 #define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
00400 #define UART       ((Uart   *)0x400E0600U) /**< \brief (UART      ) Base Address */
00401 #define PDC_UART   ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
00402 #define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
00403 #define EFC0       ((Efc    *)0x400E0800U) /**< \brief (EFC0      ) Base Address */
00404 #define PIOA       ((Pio    *)0x400E0C00U) /**< \brief (PIOA      ) Base Address */
00405 #define PIOB       ((Pio    *)0x400E0E00U) /**< \brief (PIOB      ) Base Address */
00406 #define RSTC       ((Rstc   *)0x400E1200U) /**< \brief (RSTC      ) Base Address */
00407 #define SUPC       ((Supc   *)0x400E1210U) /**< \brief (SUPC      ) Base Address */
00408 #define RTT        ((Rtt    *)0x400E1230U) /**< \brief (RTT       ) Base Address */
00409 #define WDT        ((Wdt    *)0x400E1250U) /**< \brief (WDT       ) Base Address */
00410 #define RTC        ((Rtc    *)0x400E1260U) /**< \brief (RTC       ) Base Address */
00411 #define GPBR       ((Gpbr   *)0x400E1290U) /**< \brief (GPBR      ) Base Address */
00412 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00413 /*@}*/
00414 
00415 /* ************************************************************************** */
00416 /*   PIO DEFINITIONS FOR SAM3U2C */
00417 /* ************************************************************************** */
00418 /** \addtogroup SAM3U2C_pio Peripheral Pio Definitions */
00419 /*@{*/
00420 
00421 #include "pio/sam3u2c.h"
00422 /*@}*/
00423 
00424 /* ************************************************************************** */
00425 /*   MEMORY MAPPING DEFINITIONS FOR SAM3U2C */
00426 /* ************************************************************************** */
00427 
00428 #define IFLASH0_SIZE             (0x20000u)
00429 #define IFLASH0_PAGE_SIZE        (256u)
00430 #define IFLASH0_LOCK_REGION_SIZE (8192u)
00431 #define IFLASH0_NB_OF_PAGES      (64u)
00432 #define IFLASH0_NB_OF_LOCK_BITS  (32u)
00433 #define IRAM0_SIZE               (0x4000u)
00434 #define IRAM1_SIZE               (0x4000u)
00435 #define NFCRAM_SIZE              (0x1000u)
00436 #define IFLASH_SIZE              (IFLASH0_SIZE)
00437 #define IRAM_SIZE                (IRAM0_SIZE+IRAM1_SIZE)
00438 
00439 #define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
00440 #define IROM_ADDR      (0x00180000u) /**< Internal ROM base address */
00441 #define IRAM0_ADDR     (0x20000000u) /**< Internal RAM 0 base address */
00442 #define IRAM1_ADDR     (0x20080000u) /**< Internal RAM 1 base address */
00443 #define NFC_RAM_ADDR   (0x20100000u) /**< NAND Flash Controller RAM base address */
00444 #define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
00445 
00446 /* ************************************************************************** */
00447 /*   MISCELLANEOUS DEFINITIONS FOR SAM3U2C */
00448 /* ************************************************************************** */
00449 
00450 #define CHIP_JTAGID (0x05B2A01FUL)
00451 #define CHIP_CIDR (0x280A0760UL)
00452 #define CHIP_EXID (0x0UL)
00453 
00454 /* ************************************************************************** */
00455 /*   ELECTRICAL DEFINITIONS FOR SAM3U2C */
00456 /* ************************************************************************** */
00457 
00458 /* Device characteristics */
00459 #define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
00460 #define CHIP_FREQ_SLCK_RC               (32000UL)
00461 #define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
00462 #define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
00463 #define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
00464 #define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
00465 #define CHIP_FREQ_CPU_MAX               (96000000UL)
00466 #define CHIP_FREQ_XTAL_32K              (32768UL)
00467 #define CHIP_FREQ_XTAL_12M              (12000000UL)
00468 
00469 /* Embedded Flash Write Wait State */
00470 #define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
00471 
00472 /* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
00473 #define CHIP_FREQ_FWS_0                 (24000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
00474 #define CHIP_FREQ_FWS_1                 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
00475 #define CHIP_FREQ_FWS_2                 (72000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
00476 #define CHIP_FREQ_FWS_3                 (84000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
00477 
00478 #ifdef __cplusplus
00479 }
00480 #endif
00481 
00482 /*@}*/
00483 
00484 #endif /* _SAM3U2C_ */