rt_HAL_CM.h

00001 /**
00002  * @file    rt_HAL_CM.h
00003  * @brief   
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 /* Definitions */
00023 #define INITIAL_xPSR    0x01000000
00024 #define DEMCR_TRCENA    0x01000000
00025 #define ITM_ITMENA      0x00000001
00026 #define MAGIC_WORD      0xE25A2EA5
00027 
00028 // ARMCC has deprecated use for ldrex and strex functions
00029 // from C so do not used them on any devices.
00030 #if (0)
00031  #define __USE_EXCLUSIVE_ACCESS
00032 #else
00033  #undef  __USE_EXCLUSIVE_ACCESS
00034 #endif
00035 
00036 /* NVIC registers */
00037 #define NVIC_ST_CTRL    (*((volatile U32 *)0xE000E010))
00038 #define NVIC_ST_RELOAD  (*((volatile U32 *)0xE000E014))
00039 #define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
00040 #define NVIC_ISER         ((volatile U32 *)0xE000E100)
00041 #define NVIC_ICER         ((volatile U32 *)0xE000E180)
00042 #if (__TARGET_ARCH_6S_M)
00043 #define NVIC_IP           ((volatile U32 *)0xE000E400)
00044 #else
00045 #define NVIC_IP           ((volatile U8  *)0xE000E400)
00046 #endif
00047 #define NVIC_INT_CTRL   (*((volatile U32 *)0xE000ED04))
00048 #define NVIC_AIR_CTRL   (*((volatile U32 *)0xE000ED0C))
00049 #define NVIC_SYS_PRI2   (*((volatile U32 *)0xE000ED1C))
00050 #define NVIC_SYS_PRI3   (*((volatile U32 *)0xE000ED20))
00051 
00052 #define OS_PEND_IRQ()   NVIC_INT_CTRL  = (1<<28)
00053 #define OS_PENDING      ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
00054 #define OS_UNPEND(fl)   NVIC_INT_CTRL  = (*fl = OS_PENDING) << 25
00055 #define OS_PEND(fl,p)   NVIC_INT_CTRL  = (fl | p<<2) << 26
00056 #define OS_LOCK()       NVIC_ST_CTRL   =  0x0005
00057 #define OS_UNLOCK()     NVIC_ST_CTRL   =  0x0007
00058 
00059 #define OS_X_PENDING    ((NVIC_INT_CTRL >> 28) & 1)
00060 #define OS_X_UNPEND(fl) NVIC_INT_CTRL  = (*fl = OS_X_PENDING) << 27
00061 #define OS_X_PEND(fl,p) NVIC_INT_CTRL  = (fl | p) << 28
00062 #if (__TARGET_ARCH_6S_M)
00063 #define OS_X_INIT(n)    NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
00064                         NVIC_ISER[n>>5] = 1 << (n & 0x1F)
00065 #else
00066 #define OS_X_INIT(n)    NVIC_IP[n] = 0xFF; \
00067                         NVIC_ISER[n>>5] = 1 << (n & 0x1F)
00068 #endif
00069 #define OS_X_LOCK(n)    NVIC_ICER[n>>5] = 1 << (n & 0x1F)
00070 #define OS_X_UNLOCK(n)  NVIC_ISER[n>>5] = 1 << (n & 0x1F)
00071 
00072 /* Core Debug registers */
00073 #define DEMCR           (*((volatile U32 *)0xE000EDFC))
00074 
00075 /* ITM registers */
00076 #define ITM_CONTROL     (*((volatile U32 *)0xE0000E80))
00077 #define ITM_ENABLE      (*((volatile U32 *)0xE0000E00))
00078 #define ITM_PORT30_U32  (*((volatile U32 *)0xE0000078))
00079 #define ITM_PORT31_U32  (*((volatile U32 *)0xE000007C))
00080 #define ITM_PORT31_U16  (*((volatile U16 *)0xE000007C))
00081 #define ITM_PORT31_U8   (*((volatile U8  *)0xE000007C))
00082 
00083 /* Variables */
00084 extern BIT dbg_msg;
00085 
00086 /* Functions */
00087 #ifdef __USE_EXCLUSIVE_ACCESS
00088  #define rt_inc(p)     while(__strex((__ldrex(p)+1),p))
00089  #define rt_dec(p)     while(__strex((__ldrex(p)-1),p))
00090 #else
00091  #define rt_inc(p)     __disable_irq();(*p)++;__enable_irq();
00092  #define rt_dec(p)     __disable_irq();(*p)--;__enable_irq();
00093 #endif
00094 
00095 static inline U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
00096   U32 cnt,c2;
00097 #ifdef __USE_EXCLUSIVE_ACCESS
00098   do {
00099     if ((cnt = __ldrex(count)) == size) {
00100       __clrex();
00101       return (cnt); }
00102   } while (__strex(cnt+1, count));
00103   do {
00104     c2 = (cnt = __ldrex(first)) + 1;
00105     if (c2 == size) c2 = 0;
00106   } while (__strex(c2, first));
00107 #else
00108   __disable_irq();
00109   if ((cnt = *count) < size) {
00110     *count = cnt+1;
00111     c2 = (cnt = *first) + 1;
00112     if (c2 == size) c2 = 0;
00113     *first = c2;
00114   }
00115   __enable_irq ();
00116 #endif
00117   return (cnt);
00118 }
00119 
00120 static inline void rt_systick_init (void) {
00121   NVIC_ST_RELOAD  = os_trv;
00122   NVIC_ST_CURRENT = 0;
00123   NVIC_ST_CTRL    = 0x0007;
00124   NVIC_SYS_PRI3  |= 0xFF000000;
00125 }
00126 
00127 static inline void rt_svc_init (void) {
00128 #if !(__TARGET_ARCH_6S_M)
00129   int sh,prigroup;
00130 #endif
00131   NVIC_SYS_PRI3 |= 0x00FF0000;
00132 #if (__TARGET_ARCH_6S_M)
00133   NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
00134 #else
00135   sh       = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
00136   prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
00137   if (prigroup >= sh) {
00138     sh = prigroup + 1;
00139   }
00140   NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
00141 #endif
00142 }
00143 
00144 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
00145 extern void rt_set_PSP (U32 stack);
00146 extern U32  rt_get_PSP (void);
00147 extern void os_set_env (void);
00148 extern void *_alloc_box (void *box_mem);
00149 extern int  _free_box (void *box_mem, void *box);
00150 
00151 extern void dbg_init (void);
00152 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
00153 extern void dbg_task_switch (U32 task_id);
00154 
00155 #ifdef DBG_MSG
00156 #define DBG_INIT() dbg_init()
00157 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
00158 #define DBG_TASK_SWITCH(task_id)      if (dbg_msg && (os_tsk.new!=os_tsk.run)) \
00159                                                    dbg_task_switch(task_id)
00160 #else
00161 #define DBG_INIT()
00162 #define DBG_TASK_NOTIFY(p_tcb,create)
00163 #define DBG_TASK_SWITCH(task_id)
00164 #endif
00165 
00166 /*----------------------------------------------------------------------------
00167  * end of file
00168  *---------------------------------------------------------------------------*/
00169