pioc.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) %copyright_year%, Atmel Corporation                                        */
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00011 /*                                                                              */
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00016 /* this software without specific prior written permission.                     */
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00029 
00030 #ifndef _SAM3U_PIOC_INSTANCE_
00031 #define _SAM3U_PIOC_INSTANCE_
00032 
00033 /* ========== Register definition for PIOC peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035 #define REG_PIOC_PER             (0x400E1000U) /**< \brief (PIOC) PIO Enable Register */
00036 #define REG_PIOC_PDR             (0x400E1004U) /**< \brief (PIOC) PIO Disable Register */
00037 #define REG_PIOC_PSR             (0x400E1008U) /**< \brief (PIOC) PIO Status Register */
00038 #define REG_PIOC_OER             (0x400E1010U) /**< \brief (PIOC) Output Enable Register */
00039 #define REG_PIOC_ODR             (0x400E1014U) /**< \brief (PIOC) Output Disable Register */
00040 #define REG_PIOC_OSR             (0x400E1018U) /**< \brief (PIOC) Output Status Register */
00041 #define REG_PIOC_IFER            (0x400E1020U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
00042 #define REG_PIOC_IFDR            (0x400E1024U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
00043 #define REG_PIOC_IFSR            (0x400E1028U) /**< \brief (PIOC) Glitch Input Filter Status Register */
00044 #define REG_PIOC_SODR            (0x400E1030U) /**< \brief (PIOC) Set Output Data Register */
00045 #define REG_PIOC_CODR            (0x400E1034U) /**< \brief (PIOC) Clear Output Data Register */
00046 #define REG_PIOC_ODSR            (0x400E1038U) /**< \brief (PIOC) Output Data Status Register */
00047 #define REG_PIOC_PDSR            (0x400E103CU) /**< \brief (PIOC) Pin Data Status Register */
00048 #define REG_PIOC_IER             (0x400E1040U) /**< \brief (PIOC) Interrupt Enable Register */
00049 #define REG_PIOC_IDR             (0x400E1044U) /**< \brief (PIOC) Interrupt Disable Register */
00050 #define REG_PIOC_IMR             (0x400E1048U) /**< \brief (PIOC) Interrupt Mask Register */
00051 #define REG_PIOC_ISR             (0x400E104CU) /**< \brief (PIOC) Interrupt Status Register */
00052 #define REG_PIOC_MDER            (0x400E1050U) /**< \brief (PIOC) Multi-driver Enable Register */
00053 #define REG_PIOC_MDDR            (0x400E1054U) /**< \brief (PIOC) Multi-driver Disable Register */
00054 #define REG_PIOC_MDSR            (0x400E1058U) /**< \brief (PIOC) Multi-driver Status Register */
00055 #define REG_PIOC_PUDR            (0x400E1060U) /**< \brief (PIOC) Pull-up Disable Register */
00056 #define REG_PIOC_PUER            (0x400E1064U) /**< \brief (PIOC) Pull-up Enable Register */
00057 #define REG_PIOC_PUSR            (0x400E1068U) /**< \brief (PIOC) Pad Pull-up Status Register */
00058 #define REG_PIOC_ABSR            (0x400E1070U) /**< \brief (PIOC) Peripheral AB Select Register */
00059 #define REG_PIOC_SCIFSR          (0x400E1080U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
00060 #define REG_PIOC_DIFSR           (0x400E1084U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
00061 #define REG_PIOC_IFDGSR          (0x400E1088U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
00062 #define REG_PIOC_SCDR            (0x400E108CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
00063 #define REG_PIOC_OWER            (0x400E10A0U) /**< \brief (PIOC) Output Write Enable */
00064 #define REG_PIOC_OWDR            (0x400E10A4U) /**< \brief (PIOC) Output Write Disable */
00065 #define REG_PIOC_OWSR            (0x400E10A8U) /**< \brief (PIOC) Output Write Status Register */
00066 #define REG_PIOC_AIMER           (0x400E10B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
00067 #define REG_PIOC_AIMDR           (0x400E10B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
00068 #define REG_PIOC_AIMMR           (0x400E10B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
00069 #define REG_PIOC_ESR             (0x400E10C0U) /**< \brief (PIOC) Edge Select Register */
00070 #define REG_PIOC_LSR             (0x400E10C4U) /**< \brief (PIOC) Level Select Register */
00071 #define REG_PIOC_ELSR            (0x400E10C8U) /**< \brief (PIOC) Edge/Level Status Register */
00072 #define REG_PIOC_FELLSR          (0x400E10D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
00073 #define REG_PIOC_REHLSR          (0x400E10D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
00074 #define REG_PIOC_FRLHSR          (0x400E10D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
00075 #define REG_PIOC_LOCKSR          (0x400E10E0U) /**< \brief (PIOC) Lock Status */
00076 #define REG_PIOC_WPMR            (0x400E10E4U) /**< \brief (PIOC) Write Protect Mode Register */
00077 #define REG_PIOC_WPSR            (0x400E10E8U) /**< \brief (PIOC) Write Protect Status Register */
00078 #else
00079 #define REG_PIOC_PER    (*(WoReg*)0x400E1000U) /**< \brief (PIOC) PIO Enable Register */
00080 #define REG_PIOC_PDR    (*(WoReg*)0x400E1004U) /**< \brief (PIOC) PIO Disable Register */
00081 #define REG_PIOC_PSR    (*(RoReg*)0x400E1008U) /**< \brief (PIOC) PIO Status Register */
00082 #define REG_PIOC_OER    (*(WoReg*)0x400E1010U) /**< \brief (PIOC) Output Enable Register */
00083 #define REG_PIOC_ODR    (*(WoReg*)0x400E1014U) /**< \brief (PIOC) Output Disable Register */
00084 #define REG_PIOC_OSR    (*(RoReg*)0x400E1018U) /**< \brief (PIOC) Output Status Register */
00085 #define REG_PIOC_IFER   (*(WoReg*)0x400E1020U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
00086 #define REG_PIOC_IFDR   (*(WoReg*)0x400E1024U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
00087 #define REG_PIOC_IFSR   (*(RoReg*)0x400E1028U) /**< \brief (PIOC) Glitch Input Filter Status Register */
00088 #define REG_PIOC_SODR   (*(WoReg*)0x400E1030U) /**< \brief (PIOC) Set Output Data Register */
00089 #define REG_PIOC_CODR   (*(WoReg*)0x400E1034U) /**< \brief (PIOC) Clear Output Data Register */
00090 #define REG_PIOC_ODSR   (*(RwReg*)0x400E1038U) /**< \brief (PIOC) Output Data Status Register */
00091 #define REG_PIOC_PDSR   (*(RoReg*)0x400E103CU) /**< \brief (PIOC) Pin Data Status Register */
00092 #define REG_PIOC_IER    (*(WoReg*)0x400E1040U) /**< \brief (PIOC) Interrupt Enable Register */
00093 #define REG_PIOC_IDR    (*(WoReg*)0x400E1044U) /**< \brief (PIOC) Interrupt Disable Register */
00094 #define REG_PIOC_IMR    (*(RoReg*)0x400E1048U) /**< \brief (PIOC) Interrupt Mask Register */
00095 #define REG_PIOC_ISR    (*(RoReg*)0x400E104CU) /**< \brief (PIOC) Interrupt Status Register */
00096 #define REG_PIOC_MDER   (*(WoReg*)0x400E1050U) /**< \brief (PIOC) Multi-driver Enable Register */
00097 #define REG_PIOC_MDDR   (*(WoReg*)0x400E1054U) /**< \brief (PIOC) Multi-driver Disable Register */
00098 #define REG_PIOC_MDSR   (*(RoReg*)0x400E1058U) /**< \brief (PIOC) Multi-driver Status Register */
00099 #define REG_PIOC_PUDR   (*(WoReg*)0x400E1060U) /**< \brief (PIOC) Pull-up Disable Register */
00100 #define REG_PIOC_PUER   (*(WoReg*)0x400E1064U) /**< \brief (PIOC) Pull-up Enable Register */
00101 #define REG_PIOC_PUSR   (*(RoReg*)0x400E1068U) /**< \brief (PIOC) Pad Pull-up Status Register */
00102 #define REG_PIOC_ABSR   (*(RwReg*)0x400E1070U) /**< \brief (PIOC) Peripheral AB Select Register */
00103 #define REG_PIOC_SCIFSR (*(WoReg*)0x400E1080U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
00104 #define REG_PIOC_DIFSR  (*(WoReg*)0x400E1084U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
00105 #define REG_PIOC_IFDGSR (*(RoReg*)0x400E1088U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
00106 #define REG_PIOC_SCDR   (*(RwReg*)0x400E108CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
00107 #define REG_PIOC_OWER   (*(WoReg*)0x400E10A0U) /**< \brief (PIOC) Output Write Enable */
00108 #define REG_PIOC_OWDR   (*(WoReg*)0x400E10A4U) /**< \brief (PIOC) Output Write Disable */
00109 #define REG_PIOC_OWSR   (*(RoReg*)0x400E10A8U) /**< \brief (PIOC) Output Write Status Register */
00110 #define REG_PIOC_AIMER  (*(WoReg*)0x400E10B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
00111 #define REG_PIOC_AIMDR  (*(WoReg*)0x400E10B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
00112 #define REG_PIOC_AIMMR  (*(RoReg*)0x400E10B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
00113 #define REG_PIOC_ESR    (*(WoReg*)0x400E10C0U) /**< \brief (PIOC) Edge Select Register */
00114 #define REG_PIOC_LSR    (*(WoReg*)0x400E10C4U) /**< \brief (PIOC) Level Select Register */
00115 #define REG_PIOC_ELSR   (*(RoReg*)0x400E10C8U) /**< \brief (PIOC) Edge/Level Status Register */
00116 #define REG_PIOC_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
00117 #define REG_PIOC_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
00118 #define REG_PIOC_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
00119 #define REG_PIOC_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOC) Lock Status */
00120 #define REG_PIOC_WPMR   (*(RwReg*)0x400E10E4U) /**< \brief (PIOC) Write Protect Mode Register */
00121 #define REG_PIOC_WPSR   (*(RoReg*)0x400E10E8U) /**< \brief (PIOC) Write Protect Status Register */
00122 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00123 
00124 #endif /* _SAM3U_PIOC_INSTANCE_ */