DAP_config.h

00001 /**
00002  * @file    DAP_config.c
00003  * @brief
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 #ifndef __DAP_CONFIG_H__
00023 #define __DAP_CONFIG_H__
00024 
00025 
00026 //**************************************************************************************************
00027 /**
00028 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
00029 \ingroup DAP_ConfigIO_gr
00030 @{
00031 Provides definitions about:
00032  - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
00033  - Debug Unit communication packet size.
00034  - Debug Access Port communication mode (JTAG or SWD).
00035  - Optional information about a connected Target Device (for Evaluation Boards).
00036 */
00037 
00038 #include "LPC43xx.h"                            // Debug Unit Cortex-M Processor Header File
00039 #include "lpc43xx_scu.h"
00040 
00041 typedef unsigned int    BOOL;
00042 
00043 #ifndef __TRUE
00044  #define __TRUE         1
00045 #endif
00046 #ifndef __FALSE
00047  #define __FALSE        0
00048 #endif
00049 
00050 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
00051 /// This value is used to calculate the SWD/JTAG clock speed.
00052 #define CPU_CLOCK             SystemCoreClock        ///< Specifies the CPU Clock in Hz
00053 
00054 /// Number of processor cycles for I/O Port write operations.
00055 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
00056 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
00057 /// requrie 2 processor cycles for a I/O Port Write operation.  If the Debug Unit uses
00058 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
00059 /// required.
00060 #define IO_PORT_WRITE_CYCLES  2               ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
00061 
00062 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
00063 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00064 #define DAP_SWD               1               ///< SWD Mode:  1 = available, 0 = not available
00065 
00066 /// Indicate that JTAG communication mode is available at the Debug Port.
00067 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00068 #define DAP_JTAG              0               ///< JTAG Mode: 1 = available, 0 = not available.
00069 
00070 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
00071 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
00072 #define DAP_JTAG_DEV_CNT      0               ///< Maximum number of JTAG devices on scan chain
00073 
00074 /// Default communication mode on the Debug Access Port.
00075 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
00076 #define DAP_DEFAULT_PORT      1               ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
00077 
00078 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
00079 /// Used to initialize the default SWD/JTAG clock frequency.
00080 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
00081 #define DAP_DEFAULT_SWJ_CLOCK 5000000         ///< Default SWD/JTAG clock frequency in Hz.
00082 
00083 /// Maximum Package Size for Command and Response data.
00084 /// This configuration settings is used to optimized the communication performance with the
00085 /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
00086 #define DAP_PACKET_SIZE       64              ///< USB: 64 = Full-Speed, 1024 = High-Speed.
00087 
00088 /// Maximum Package Buffers for Command and Response data.
00089 /// This configuration settings is used to optimized the communication performance with the
00090 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
00091 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
00092 #define DAP_PACKET_COUNT      1              ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
00093 
00094 /// Indicate that UART Serial Wire Output (SWO) trace is available.
00095 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00096 #define SWO_UART                0               ///< SWO UART:  1 = available, 0 = not available
00097 
00098 /// Maximum SWO UART Baudrate
00099 #define SWO_UART_MAX_BAUDRATE   10000000U       ///< SWO UART Maximum Baudrate in Hz
00100 
00101 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
00102 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00103 #define SWO_MANCHESTER          0               ///< SWO Manchester:  1 = available, 0 = not available
00104 
00105 /// SWO Trace Buffer Size.
00106 #define SWO_BUFFER_SIZE         4096U           ///< SWO Trace Buffer Size in bytes (must be 2^n)
00107 
00108 /// SWO Streaming Trace.
00109 #define SWO_STREAM              0               ///< SWO Streaming Trace: 1 = available, 0 = not available.
00110 
00111 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
00112 #define TIMESTAMP_CLOCK         1000000U      ///< Timestamp clock in Hz (0 = timestamps not supported).
00113 
00114 
00115 /// Debug Unit is connected to fixed Target Device.
00116 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
00117 /// known device.  In this case a Device Vendor and Device Name string is stored which
00118 /// may be used by the debugger or IDE to configure device parameters.
00119 #define TARGET_DEVICE_FIXED   0               ///< Target Device: 1 = known, 0 = unknown;
00120 
00121 #if TARGET_DEVICE_FIXED
00122 #define TARGET_DEVICE_VENDOR  ""              ///< String indicating the Silicon Vendor
00123 #define TARGET_DEVICE_NAME    ""              ///< String indicating the Target Device
00124 #endif
00125 
00126 ///@}
00127 
00128 
00129 // LPC43xx peripheral register bit masks (used by macros)
00130 #define CCU_CLK_CFG_RUN       (1UL << 0)
00131 #define CCU_CLK_CFG_AUTO      (1UL << 1)
00132 #define CCU_CLK_STAT_RUN      (1UL << 0)
00133 
00134 // State of Reset Ouput Enable buffer
00135 extern BOOL gpio_reset_pin_is_input;
00136 
00137 // Debug Port I/O Pins
00138 
00139 // SWCLK Pin                  P1_17: GPIO0[12]
00140 #define PORT_SWCLK            0
00141 #define PIN_SWCLK_IN_BIT      12
00142 #define PIN_SWCLK             (1<<PIN_SWCLK_IN_BIT)
00143 
00144 // SWDIO Pin                  P1_6:  GPIO1[9]
00145 #define PORT_SWDIO            1
00146 #define PIN_SWDIO_IN_BIT      9
00147 #define PIN_SWDIO             (1<<PIN_SWDIO_IN_BIT)
00148 
00149 // SWDIO Output Enable Pin    P1_5:  GPIO1[8]
00150 #define PORT_SWDIO_TXE        1
00151 #define PIN_SWDIO_TXE_IN_BIT  8
00152 #define PIN_SWDIO_TXE         (1<<PIN_SWDIO_TXE_IN_BIT)
00153 
00154 // nRESET Pin                 P2_5:  GPIO5[5] note: HANI_IOT workaround: changing to GPIO0[7]
00155 #define PORT_nRESET           0
00156 #define PIN_nRESET_IN_BIT     7
00157 #define PIN_nRESET            (1<<PIN_nRESET_IN_BIT)
00158 
00159 // nRESET Output Enable Pin   P2_6:  GPIO5[6]
00160 #define PORT_RESET_TXE        5
00161 #define PIN_RESET_TXE_IN_BIT  6
00162 #define PIN_RESET_TXE         (1<<PIN_RESET_TXE_IN_BIT)
00163 
00164 // ISP Control Pin          P2_11:  GPIO1[11]
00165 #define ISPCTRL_PORT        1
00166 #define ISPCTRL_BIT         11
00167 
00168 #define X_SET(str)     LPC_GPIO_PORT->SET[PORT_##str] = PIN_##str
00169 #define X_CLR(str)     LPC_GPIO_PORT->CLR[PORT_##str] = PIN_##str
00170 #define X_DIR_OUT(str) LPC_GPIO_PORT->DIR[PORT_##str] |= (PIN_##str)
00171 #define X_DIR_IN(str)  LPC_GPIO_PORT->DIR[PORT_##str] &= ~(PIN_##str)
00172 #define X_BYTE(str)    LPC_GPIO_PORT->B[(PORT_##str << 5) + PIN_##str##_IN_BIT]
00173 
00174 
00175 //**************************************************************************************************
00176 /**
00177 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
00178 \ingroup DAP_ConfigIO_gr
00179 @{
00180 
00181 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
00182 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
00183 interface of a device. The following I/O Pins are provided:
00184 
00185 JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mode
00186 ---------------------------- | -------------------- | ---------------------------------------------
00187 TCK: Test Clock              | SWCLK: Clock         | Output Push/Pull
00188 TMS: Test Mode Select        | SWDIO: Data I/O      | Output Push/Pull; Input (for receiving data)
00189 TDI: Test Data Input         |                      | Output Push/Pull
00190 TDO: Test Data Output        |                      | Input
00191 nTRST: Test Reset (optional) |                      | Output Open Drain with pull-up resistor
00192 nRESET: Device Reset         | nRESET: Device Reset | Output Open Drain with pull-up resistor
00193 
00194 
00195 DAP Hardware I/O Pin Access Functions
00196 -------------------------------------
00197 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
00198 these I/O Pins.
00199 
00200 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
00201 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
00202 peripherals that can independently write/read a single I/O pin without affecting any other pins
00203 of the same I/O port. The following SWDIO I/O Pin functions are provided:
00204  - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
00205  - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
00206  - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
00207  - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
00208 */
00209 
00210 
00211 // Configure DAP I/O pins ------------------------------
00212 
00213 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
00214 Configures the DAP Hardware I/O pins for JTAG mode:
00215  - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
00216  - TDO to input mode.
00217 */
00218 __STATIC_INLINE void PORT_JTAG_SETUP(void) {}
00219 
00220 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
00221 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
00222  - SWCLK, SWDIO, nRESET to output mode and set to default high level.
00223  - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
00224 */
00225 __STATIC_INLINE void PORT_SWD_SETUP(void)
00226 {
00227     X_SET(SWCLK);
00228     X_SET(SWDIO);
00229     X_DIR_OUT(SWCLK);
00230     X_DIR_OUT(SWDIO);
00231     X_SET(SWDIO_TXE);
00232     X_DIR_OUT(SWDIO_TXE);
00233 }
00234 
00235 
00236 /** Disable JTAG/SWD I/O Pins.
00237 Disables the DAP Hardware I/O pins which configures:
00238  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
00239 */
00240 __STATIC_INLINE void PORT_OFF(void)
00241 {
00242     X_CLR(SWCLK);
00243     X_CLR(SWDIO);
00244     X_DIR_OUT(SWCLK);
00245     X_DIR_OUT(SWDIO);
00246     X_SET(SWDIO_TXE);
00247     X_DIR_OUT(SWDIO_TXE);
00248 }
00249 
00250 
00251 // SWCLK/TCK I/O pin -------------------------------------
00252 
00253 /** SWCLK/TCK I/O pin: Get Input.
00254 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
00255 */
00256 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
00257 {
00258     return (0);   // Not available
00259 }
00260 
00261 /** SWCLK/TCK I/O pin: Set Output to High.
00262 Set the SWCLK/TCK DAP hardware I/O pin to high level.
00263 */
00264 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_SET(void)
00265 {
00266     X_SET(SWCLK);
00267 }
00268 
00269 /** SWCLK/TCK I/O pin: Set Output to Low.
00270 Set the SWCLK/TCK DAP hardware I/O pin to low level.
00271 */
00272 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR(void)
00273 {
00274     X_CLR(SWCLK);
00275 }
00276 
00277 
00278 // SWDIO/TMS Pin I/O --------------------------------------
00279 
00280 /** SWDIO/TMS I/O pin: Get Input.
00281 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
00282 */
00283 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
00284 {
00285     return X_BYTE(SWDIO) & 0x1;
00286 }
00287 
00288 /** SWDIO/TMS I/O pin: Set Output to High.
00289 Set the SWDIO/TMS DAP hardware I/O pin to high level.
00290 */
00291 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_SET(void)
00292 {
00293     X_SET(SWDIO);
00294 }
00295 
00296 /** SWDIO/TMS I/O pin: Set Output to Low.
00297 Set the SWDIO/TMS DAP hardware I/O pin to low level.
00298 */
00299 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_CLR(void)
00300 {
00301     X_CLR(SWDIO);
00302 }
00303 
00304 /** SWDIO I/O pin: Get Input (used in SWD mode only).
00305 \return Current status of the SWDIO DAP hardware I/O pin.
00306 */
00307 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
00308 {
00309     return X_BYTE(SWDIO) & 0x1;
00310 }
00311 
00312 /** SWDIO I/O pin: Set Output (used in SWD mode only).
00313 \param bit Output value for the SWDIO DAP hardware I/O pin.
00314 */
00315 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT(uint32_t bit)
00316 {
00317     if (bit & 0x1) {
00318         X_SET(SWDIO);
00319     } else {
00320         X_CLR(SWDIO);
00321     }
00322 }
00323 
00324 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
00325 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
00326 called prior \ref PIN_SWDIO_OUT function calls.
00327 */
00328 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_ENABLE(void)
00329 {
00330     X_SET(SWDIO_TXE);
00331     X_DIR_OUT(SWDIO);
00332 }
00333 
00334 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
00335 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
00336 called prior \ref PIN_SWDIO_IN function calls.
00337 */
00338 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE(void)
00339 {
00340     X_DIR_IN(SWDIO);
00341     X_CLR(SWDIO_TXE);
00342 }
00343 
00344 
00345 // TDI Pin I/O ---------------------------------------------
00346 
00347 /** TDI I/O pin: Get Input.
00348 \return Current status of the TDI DAP hardware I/O pin.
00349 */
00350 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
00351 {
00352     return (0);   // Not available
00353 }
00354 
00355 /** TDI I/O pin: Set Output.
00356 \param bit Output value for the TDI DAP hardware I/O pin.
00357 */
00358 __STATIC_FORCEINLINE void     PIN_TDI_OUT(uint32_t bit)
00359 {
00360     ;             // Not available
00361 }
00362 
00363 
00364 // TDO Pin I/O ---------------------------------------------
00365 
00366 /** TDO I/O pin: Get Input.
00367 \return Current status of the TDO DAP hardware I/O pin.
00368 */
00369 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
00370 {
00371     return (0);   // Not available
00372 }
00373 
00374 
00375 // nTRST Pin I/O -------------------------------------------
00376 
00377 /** nTRST I/O pin: Get Input.
00378 \return Current status of the nTRST DAP hardware I/O pin.
00379 */
00380 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
00381 {
00382     return (0);   // Not available
00383 }
00384 
00385 /** nTRST I/O pin: Set Output.
00386 \param bit JTAG TRST Test Reset pin status:
00387            - 0: issue a JTAG TRST Test Reset.
00388            - 1: release JTAG TRST Test Reset.
00389 */
00390 __STATIC_FORCEINLINE void     PIN_nTRST_OUT(uint32_t bit)
00391 {
00392     ;             // Not available
00393 }
00394 
00395 // nRESET Pin I/O------------------------------------------
00396 
00397 /** nRESET I/O pin: Get Input.
00398 \return Current status of the nRESET DAP hardware I/O pin.
00399 */
00400 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
00401 {
00402     if (gpio_reset_pin_is_input) {
00403         return X_BYTE(nRESET) & 0x1;
00404     } else {
00405         return 0; // Always LOW when output
00406     }
00407 }
00408 
00409 /** nRESET I/O pin: Set Output.
00410 \param bit target device hardware reset pin status:
00411            - 0: issue a device hardware reset.
00412            - 1: release device hardware reset.
00413 */
00414 __STATIC_FORCEINLINE void     PIN_nRESET_OUT(uint32_t bit)
00415 {
00416     if (bit) {
00417         // release device hardware reset. (reset INPUT, reset oe LOW=INPUT)
00418         X_DIR_IN(nRESET);
00419         X_CLR(RESET_TXE);
00420         gpio_reset_pin_is_input = __TRUE;
00421         LPC_GPIO_PIN_INT->IST = 0x01;    // ACK any pending edge interrupt
00422         LPC_GPIO_PIN_INT->SIENF |= 0x1;  // Enable falling edge interrupt
00423     } else {
00424         // issue a device hardware reset. (reset OUTPUT+LOW, reset oe HIGH=OUTPUT)
00425         gpio_reset_pin_is_input = __FALSE;
00426         LPC_GPIO_PIN_INT->CIENF |= 0x1;  // Disable falling edge interrupt
00427         LPC_GPIO_PIN_INT->IST = 0x01;    // ACK any pending edge interrupt
00428         X_SET(RESET_TXE);
00429         X_CLR(nRESET);
00430         X_DIR_OUT(nRESET);
00431     }
00432 }
00433 
00434 ///@}
00435 
00436 
00437 //**************************************************************************************************
00438 /**
00439 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
00440 \ingroup DAP_ConfigIO_gr
00441 @{
00442 
00443 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
00444 
00445 It is recommended to provide the following LEDs for status indication:
00446  - Connect LED: is active when the DAP hardware is connected to a debugger.
00447  - Running LED: is active when the debugger has put the target device into running state.
00448 */
00449 
00450 /** Debug Unit: Set status of Connected LED.
00451 \param bit status of the Connect LED.
00452            - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
00453            - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
00454 */
00455 __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
00456 {
00457 }
00458 
00459 /** Debug Unit: Set status Target Running LED.
00460 \param bit status of the Target Running LED.
00461            - 1: Target Running LED ON: program execution in target started.
00462            - 0: Target Running LED OFF: program execution in target stopped.
00463 */
00464 __STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
00465 {
00466     ;             // Not available
00467 }
00468 
00469 ///@}
00470 
00471 
00472 //**************************************************************************************************
00473 /**
00474 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
00475 \ingroup DAP_ConfigIO_gr
00476 @{
00477 Access function for Test Domain Timer.
00478 
00479 The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
00480 default, the DWT timer is used.  The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
00481 
00482 */
00483 
00484 /** Get timestamp of Test Domain Timer.
00485 \return Current timestamp value.
00486 */
00487 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
00488   return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
00489 }
00490 
00491 ///@}
00492 
00493 
00494 //**************************************************************************************************
00495 /**
00496 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
00497 \ingroup DAP_ConfigIO_gr
00498 @{
00499 
00500 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
00501 */
00502 
00503 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
00504 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
00505 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
00506  - I/O clock system enabled.
00507  - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
00508  - for nTRST, nRESET a weak pull-up (if available) is enabled.
00509  - LED output pins are enabled and LEDs are turned off.
00510 */
00511 __STATIC_INLINE void DAP_SETUP(void)
00512 {
00513     /* Enable clock and init GPIO outputs */
00514     LPC_CCU1->CLK_M4_GPIO_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
00515 
00516     while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN));
00517 
00518     /* Configure I/O pins: function number, input buffer enabled,    */
00519     /*                     no pull-up/down                           */
00520     scu_pinmux(1, 17, GPIO_NOPULL, FUNC0);   /* SWCLK/TCK: GPIO0[12] */
00521     scu_pinmux(1,  6, GPIO_NOPULL, FUNC0);   /* SWDIO/TMS: GPIO1[9]  */
00522     scu_pinmux(1,  5, GPIO_NOPULL, FUNC0);   /* SWDIO_OE:  GPIO1[8]  */
00523 }
00524 
00525 /** Reset Target Device with custom specific I/O pin or command sequence.
00526 This function allows the optional implementation of a device specific reset sequence.
00527 It is called when the command \ref DAP_ResetTarget and is for example required
00528 when a device needs a time-critical unlock sequence that enables the debug port.
00529 \return 0 = no device specific reset sequence is implemented.\n
00530         1 = a device specific reset sequence is implemented.
00531 */
00532 __STATIC_INLINE uint32_t RESET_TARGET(void)
00533 {
00534     return (0);              // change to '1' when a device reset sequence is implemented
00535 }
00536 
00537 ///@}
00538 
00539 
00540 #endif /* __DAP_CONFIG_H__ */