DAP_config.h

00001 /**
00002  * @file    DAP_config.h
00003  * @brief
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 #ifndef __DAP_CONFIG_H__
00023 #define __DAP_CONFIG_H__
00024 
00025 
00026 //**************************************************************************************************
00027 /**
00028 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
00029 \ingroup DAP_ConfigIO_gr
00030 @{
00031 Provides definitions about:
00032  - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
00033  - Debug Unit communication packet size.
00034  - Debug Access Port communication mode (JTAG or SWD).
00035  - Optional information about a connected Target Device (for Evaluation Boards).
00036 */
00037 
00038 #include "IO_Config.h"
00039 
00040 // Board configuration options
00041 
00042 // Configure JTAG option
00043 #if defined(BOARD_BAMBINO_210) || defined(BOARD_BAMBINO_210E)
00044 // LPC43xx multicore targets require JTAG to debug slave cores
00045 #define CONF_JTAG
00046 #endif
00047 
00048 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
00049 /// This value is used to calculate the SWD/JTAG clock speed.
00050 #define CPU_CLOCK               48000000        ///< Specifies the CPU Clock in Hz
00051 
00052 /// Number of processor cycles for I/O Port write operations.
00053 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
00054 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
00055 /// requrie 2 processor cycles for a I/O Port Write operation.  If the Debug Unit uses
00056 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
00057 /// required.
00058 #define IO_PORT_WRITE_CYCLES    2               ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
00059 
00060 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
00061 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00062 #define DAP_SWD                 1               ///< SWD Mode:  1 = available, 0 = not available
00063 
00064 /// Indicate that JTAG communication mode is available at the Debug Port.
00065 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00066 #if defined(CONF_JTAG)
00067 #define DAP_JTAG                1               ///< JTAG Mode: 1 = available
00068 #else
00069 #define DAP_JTAG                0               ///< JTAG Mode: 0 = not available
00070 #endif
00071 
00072 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
00073 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
00074 #define DAP_JTAG_DEV_CNT        8               ///< Maximum number of JTAG devices on scan chain
00075 
00076 /// Default communication mode on the Debug Access Port.
00077 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
00078 #define DAP_DEFAULT_PORT        1               ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
00079 
00080 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
00081 /// Used to initialize the default SWD/JTAG clock frequency.
00082 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
00083 #define DAP_DEFAULT_SWJ_CLOCK   5000000         ///< Default SWD/JTAG clock frequency in Hz.
00084 
00085 /// Maximum Package Size for Command and Response data.
00086 /// This configuration settings is used to optimized the communication performance with the
00087 /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
00088 #define DAP_PACKET_SIZE         64              ///< USB: 64 = Full-Speed, 1024 = High-Speed.
00089 
00090 /// Maximum Package Buffers for Command and Response data.
00091 /// This configuration settings is used to optimized the communication performance with the
00092 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
00093 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
00094 #define DAP_PACKET_COUNT        1              ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
00095 
00096 /// Indicate that UART Serial Wire Output (SWO) trace is available.
00097 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00098 #define SWO_UART                0               ///< SWO UART:  1 = available, 0 = not available
00099 
00100 /// Maximum SWO UART Baudrate
00101 #define SWO_UART_MAX_BAUDRATE   10000000U       ///< SWO UART Maximum Baudrate in Hz
00102 
00103 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
00104 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00105 #define SWO_MANCHESTER          0               ///< SWO Manchester:  1 = available, 0 = not available
00106 
00107 /// SWO Trace Buffer Size.
00108 #define SWO_BUFFER_SIZE         4096U           ///< SWO Trace Buffer Size in bytes (must be 2^n)
00109 
00110 /// SWO Streaming Trace.
00111 #define SWO_STREAM              0               ///< SWO Streaming Trace: 1 = available, 0 = not available.
00112 
00113 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
00114 #define TIMESTAMP_CLOCK         0 //100000000U      ///< Timestamp clock in Hz (0 = timestamps not supported).
00115 
00116 /// Debug Unit is connected to fixed Target Device.
00117 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
00118 /// known device.  In this case a Device Vendor and Device Name string is stored which
00119 /// may be used by the debugger or IDE to configure device parameters.
00120 #define TARGET_DEVICE_FIXED     0               ///< Target Device: 1 = known, 0 = unknown;
00121 
00122 #if TARGET_DEVICE_FIXED
00123 #define TARGET_DEVICE_VENDOR    ""              ///< String indicating the Silicon Vendor
00124 #define TARGET_DEVICE_NAME      ""              ///< String indicating the Target Device
00125 #endif
00126 
00127 ///@}
00128 
00129 
00130 //**************************************************************************************************
00131 /**
00132 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
00133 \ingroup DAP_ConfigIO_gr
00134 @{
00135 
00136 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
00137 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
00138 interface of a device. The following I/O Pins are provided:
00139 
00140 JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mode
00141 ---------------------------- | -------------------- | ---------------------------------------------
00142 TCK: Test Clock              | SWCLK: Clock         | Output Push/Pull
00143 TMS: Test Mode Select        | SWDIO: Data I/O      | Output Push/Pull; Input (for receiving data)
00144 TDI: Test Data Input         |                      | Output Push/Pull
00145 TDO: Test Data Output        |                      | Input
00146 nTRST: Test Reset (optional) |                      | Output Open Drain with pull-up resistor
00147 nRESET: Device Reset         | nRESET: Device Reset | Output Open Drain with pull-up resistor
00148 
00149 
00150 DAP Hardware I/O Pin Access Functions
00151 -------------------------------------
00152 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
00153 these I/O Pins.
00154 
00155 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
00156 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
00157 peripherals that can independently write/read a single I/O pin without affecting any other pins
00158 of the same I/O port. The following SWDIO I/O Pin functions are provided:
00159  - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
00160  - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
00161  - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
00162  - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
00163 */
00164 
00165 
00166 // Configure DAP I/O pins ------------------------------
00167 
00168 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
00169 Configures the DAP Hardware I/O pins for JTAG mode:
00170  - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
00171  - TDO to input mode.
00172 */
00173 __STATIC_INLINE void PORT_JTAG_SETUP(void)
00174 {
00175 #if (DAP_JTAG != 0)
00176     LPC_GPIO->SET[PIN_TDI_PORT]  =  PIN_TDI;
00177     LPC_GPIO->DIR[PIN_TDI_PORT] |=  PIN_TDI;
00178     LPC_GPIO->DIR[PIN_TDO_PORT] &= ~PIN_TDO;
00179 #endif
00180 }
00181 
00182 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
00183 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
00184  - SWCLK, SWDIO, nRESET to output mode and set to default high level.
00185  - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
00186 */
00187 __STATIC_INLINE void PORT_SWD_SETUP(void)
00188 {
00189     LPC_GPIO->SET[PIN_SWCLK_PORT] = PIN_SWCLK;
00190     LPC_GPIO->SET[PIN_SWDIO_PORT] = PIN_SWDIO;
00191 #if !defined(PIN_nRESET_FET_DRIVE)
00192     // open drain logic
00193     LPC_GPIO->DIR[PIN_nRESET_PORT] &= ~PIN_nRESET;
00194     LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET;
00195 #else
00196     // FET drive logic
00197     LPC_GPIO->DIR[PIN_nRESET_PORT] |= PIN_nRESET;
00198     LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET;
00199 #endif
00200     LPC_GPIO->DIR[PIN_SWCLK_PORT] |= PIN_SWCLK;
00201     LPC_GPIO->DIR[PIN_SWDIO_PORT] |= PIN_SWDIO;
00202 }
00203 
00204 /** Disable JTAG/SWD I/O Pins.
00205 Disables the DAP Hardware I/O pins which configures:
00206  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
00207 */
00208 __STATIC_INLINE void PORT_OFF(void)
00209 {
00210 #if !defined(PIN_nRESET_FET_DRIVE)
00211     // open drain logic
00212     LPC_GPIO->DIR[PIN_nRESET_PORT] &= ~PIN_nRESET;
00213 #else
00214     // FET drive logic
00215     LPC_GPIO->DIR[PIN_nRESET_PORT] |= PIN_nRESET;
00216     LPC_GPIO->CLR[PIN_nRESET_PORT] = PIN_nRESET;
00217 #endif
00218     LPC_GPIO->DIR[PIN_SWCLK_PORT] &= ~PIN_SWCLK;
00219     LPC_GPIO->DIR[PIN_SWDIO_PORT] &= ~PIN_SWDIO;
00220 
00221 #if defined(TARGET_POWER_HOLD)
00222     //Release Target PowerHold
00223     LPC_GPIO->CLR[PIN_PWH_PORT] = PIN_PWH;
00224 #endif
00225 }
00226 
00227 
00228 // SWCLK/TCK I/O pin -------------------------------------
00229 
00230 /** SWCLK/TCK I/O pin: Get Input.
00231 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
00232 */
00233 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
00234 {
00235     return LPC_GPIO->B[PIN_SWCLK_BIT + PIN_SWCLK_PORT * 32] & 0x1;
00236 }
00237 
00238 /** SWCLK/TCK I/O pin: Set Output to High.
00239 Set the SWCLK/TCK DAP hardware I/O pin to high level.
00240 */
00241 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_SET(void)
00242 {
00243     LPC_GPIO->SET[PIN_SWCLK_PORT] = PIN_SWCLK;
00244 }
00245 
00246 /** SWCLK/TCK I/O pin: Set Output to Low.
00247 Set the SWCLK/TCK DAP hardware I/O pin to low level.
00248 */
00249 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR(void)
00250 {
00251     LPC_GPIO->CLR[PIN_SWCLK_PORT] = PIN_SWCLK;
00252 }
00253 
00254 
00255 // SWDIO/TMS Pin I/O --------------------------------------
00256 
00257 /** SWDIO/TMS I/O pin: Get Input.
00258 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
00259 */
00260 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
00261 {
00262     return LPC_GPIO->B[PIN_SWDIO_BIT + PIN_SWDIO_PORT * 32] & 0x1;
00263 }
00264 
00265 /** SWDIO/TMS I/O pin: Set Output to High.
00266 Set the SWDIO/TMS DAP hardware I/O pin to high level.
00267 */
00268 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_SET(void)
00269 {
00270     LPC_GPIO->SET[PIN_SWDIO_PORT] = PIN_SWDIO;
00271 }
00272 
00273 /** SWDIO/TMS I/O pin: Set Output to Low.
00274 Set the SWDIO/TMS DAP hardware I/O pin to low level.
00275 */
00276 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_CLR(void)
00277 {
00278     LPC_GPIO->CLR[PIN_SWDIO_PORT] = PIN_SWDIO;
00279 }
00280 
00281 /** SWDIO I/O pin: Get Input (used in SWD mode only).
00282 \return Current status of the SWDIO DAP hardware I/O pin.
00283 */
00284 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
00285 {
00286     return LPC_GPIO->B[PIN_SWDIO_BIT + PIN_SWDIO_PORT * 32] & 0x1;
00287 }
00288 
00289 /** SWDIO I/O pin: Set Output (used in SWD mode only).
00290 \param bit Output value for the SWDIO DAP hardware I/O pin.
00291 */
00292 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT(uint32_t bit)
00293 {
00294     if (bit & 0x1) {
00295         LPC_GPIO->SET[PIN_SWDIO_PORT] = PIN_SWDIO;
00296     } else {
00297         LPC_GPIO->CLR[PIN_SWDIO_PORT] = PIN_SWDIO;
00298     }
00299 }
00300 
00301 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
00302 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
00303 called prior \ref PIN_SWDIO_OUT function calls.
00304 */
00305 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_ENABLE(void)
00306 {
00307     LPC_GPIO->DIR[PIN_SWDIO_PORT]  |= PIN_SWDIO;
00308 }
00309 
00310 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
00311 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
00312 called prior \ref PIN_SWDIO_IN function calls.
00313 */
00314 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE(void)
00315 {
00316     LPC_GPIO->DIR[PIN_SWDIO_PORT]  &= ~(PIN_SWDIO);
00317 }
00318 
00319 
00320 // TDI Pin I/O ---------------------------------------------
00321 
00322 /** TDI I/O pin: Get Input.
00323 \return Current status of the TDI DAP hardware I/O pin.
00324 */
00325 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
00326 {
00327 #if (DAP_JTAG != 0)
00328     return LPC_GPIO->B[PIN_TDI_BIT + PIN_TDI_PORT * 32] & 0x1;
00329 #else
00330     return (0);   // Not available
00331 #endif
00332 }
00333 
00334 /** TDI I/O pin: Set Output.
00335 \param bit Output value for the TDI DAP hardware I/O pin.
00336 */
00337 __STATIC_FORCEINLINE void     PIN_TDI_OUT(uint32_t bit)
00338 {
00339 #if (DAP_JTAG != 0)
00340 
00341     if (bit & 0x1) {
00342         LPC_GPIO->SET[PIN_TDI_PORT] = PIN_TDI;
00343     } else {
00344         LPC_GPIO->CLR[PIN_TDI_PORT] = PIN_TDI;
00345     }
00346 
00347 #else
00348     ;             // Not available
00349 #endif
00350 }
00351 
00352 
00353 // TDO Pin I/O ---------------------------------------------
00354 
00355 /** TDO I/O pin: Get Input.
00356 \return Current status of the TDO DAP hardware I/O pin.
00357 */
00358 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
00359 {
00360 #if (DAP_JTAG != 0)
00361     return LPC_GPIO->B[PIN_TDO_BIT + PIN_TDO_PORT * 32] & 0x1;
00362 #else
00363     return (0);   // Not available
00364 #endif
00365 }
00366 
00367 
00368 // nTRST Pin I/O -------------------------------------------
00369 
00370 /** nTRST I/O pin: Get Input.
00371 \return Current status of the nTRST DAP hardware I/O pin.
00372 */
00373 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
00374 {
00375     return (0);   // Not available
00376 }
00377 
00378 /** nTRST I/O pin: Set Output.
00379 \param bit JTAG TRST Test Reset pin status:
00380            - 0: issue a JTAG TRST Test Reset.
00381            - 1: release JTAG TRST Test Reset.
00382 */
00383 __STATIC_FORCEINLINE void     PIN_nTRST_OUT(uint32_t bit)
00384 {
00385     ;             // Not available
00386 }
00387 
00388 // nRESET Pin I/O------------------------------------------
00389 
00390 /** nRESET I/O pin: Get Input.
00391 \return Current status of the nRESET DAP hardware I/O pin.
00392 */
00393 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
00394 {
00395     return LPC_GPIO->B[PIN_nRESET_BIT + PIN_nRESET_PORT * 32] & 0x1;
00396 }
00397 
00398 /** nRESET I/O pin: Set Output.
00399 \param bit target device hardware reset pin status:
00400            - 0: issue a device hardware reset.
00401            - 1: release device hardware reset.
00402 */
00403 __STATIC_FORCEINLINE void     PIN_nRESET_OUT(uint32_t bit)
00404 {
00405 #if !defined(PIN_nRESET_FET_DRIVE)
00406     // open drain logic
00407     if (bit) {
00408         LPC_GPIO->DIR[PIN_nRESET_PORT] &= ~PIN_nRESET;    // input (pulled high external)
00409     } else {
00410         LPC_GPIO->DIR[PIN_nRESET_PORT] |=  PIN_nRESET;    // output (low)
00411     }
00412 #else
00413     // FET drive logic
00414     if (bit) {
00415         LPC_GPIO->CLR[PIN_nRESET_PORT] = (PIN_nRESET);
00416     } else {
00417         LPC_GPIO->SET[PIN_nRESET_PORT] = (PIN_nRESET);
00418     }
00419 #endif
00420 }
00421 
00422 ///@}
00423 
00424 
00425 //**************************************************************************************************
00426 /**
00427 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
00428 \ingroup DAP_ConfigIO_gr
00429 @{
00430 
00431 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
00432 
00433 It is recommended to provide the following LEDs for status indication:
00434  - Connect LED: is active when the DAP hardware is connected to a debugger.
00435  - Running LED: is active when the debugger has put the target device into running state.
00436 */
00437 
00438 /** Debug Unit: Set status of Connected LED.
00439 \param bit status of the Connect LED.
00440            - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
00441            - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
00442 */
00443 __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
00444 {
00445 }
00446 
00447 /** Debug Unit: Set status Target Running LED.
00448 \param bit status of the Target Running LED.
00449            - 1: Target Running LED ON: program execution in target started.
00450            - 0: Target Running LED OFF: program execution in target stopped.
00451 */
00452 __STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
00453 {
00454     ;             // Not available
00455 }
00456 
00457 ///@}
00458 
00459 
00460 //**************************************************************************************************
00461 /**
00462 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
00463 \ingroup DAP_ConfigIO_gr
00464 @{
00465 Access function for Test Domain Timer.
00466 
00467 The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
00468 default, the DWT timer is used.  The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
00469 
00470 */
00471 
00472 /** Get timestamp of Test Domain Timer.
00473 \return Current timestamp value.
00474 */
00475 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
00476   return 0; //(DWT->CYCCNT);
00477 }
00478 
00479 ///@}
00480 
00481 
00482 //**************************************************************************************************
00483 /**
00484 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
00485 \ingroup DAP_ConfigIO_gr
00486 @{
00487 
00488 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
00489 */
00490 
00491 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
00492 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
00493 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
00494  - I/O clock system enabled.
00495  - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
00496  - for nTRST, nRESET a weak pull-up (if available) is enabled.
00497  - LED output pins are enabled and LEDs are turned off.
00498 */
00499 __STATIC_INLINE void DAP_SETUP(void)
00500 {
00501     // Configure I/O pins
00502     PIN_SWCLK_TCK_IOCON = PIN_SWCLK_TCK_IOCON_INIT;  // SWCLK/TCK
00503     PIN_SWDIO_TMS_IOCON = PIN_SWDIO_TMS_IOCON_INIT;  // SWDIO/TMS
00504     PIN_nRESET_IOCON    = PIN_nRESET_IOCON_INIT;        // nRESET
00505 #if (DAP_JTAG != 0)
00506     PIN_TDI_IOCON       = PIN_TDI_IOCON_INIT;  // TDI
00507     PIN_TDO_IOCON       = PIN_TDO_IOCON_INIT;  // TDO
00508 #endif
00509 }
00510 
00511 /** Reset Target Device with custom specific I/O pin or command sequence.
00512 This function allows the optional implementation of a device specific reset sequence.
00513 It is called when the command \ref DAP_ResetTarget and is for example required
00514 when a device needs a time-critical unlock sequence that enables the debug port.
00515 \return 0 = no device specific reset sequence is implemented.\n
00516         1 = a device specific reset sequence is implemented.
00517 */
00518 __STATIC_INLINE uint32_t RESET_TARGET(void)
00519 {
00520     return (0);              // change to '1' when a device reset sequence is implemented
00521 }
00522 
00523 ///@}
00524 
00525 
00526 #endif /* __DAP_CONFIG_H__ */