DAP_config.h

00001 /**
00002  * @file    DAP_config.h
00003  * @brief
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 #ifndef __DAP_CONFIG_H__
00023 #define __DAP_CONFIG_H__
00024 
00025 #include "stdint.h"
00026 #include "cmsis_os2.h"
00027 #include "IO_Config.h"
00028 #include "uart.h"
00029 //#include "debug_cm.h"
00030 //#include "swd_host.h"
00031 //**************************************************************************************************
00032 /**
00033 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
00034 \ingroup DAP_ConfigIO_gr
00035 @{
00036 Provides definitions about:
00037  - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
00038  - Debug Unit communication packet size.
00039  - Debug Access Port communication mode (JTAG or SWD).
00040  - Optional information about a connected Target Device (for Evaluation Boards).
00041 */
00042 
00043 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
00044 /// This value is used to calculate the SWD/JTAG clock speed.
00045 #define CPU_CLOCK               SystemCoreClock        ///< Specifies the CPU Clock in Hz
00046 
00047 /// Number of processor cycles for I/O Port write operations.
00048 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
00049 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
00050 /// requrie 2 processor cycles for a I/O Port Write operation.  If the Debug Unit uses
00051 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
00052 /// requrired.
00053 #define IO_PORT_WRITE_CYCLES    2               ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
00054 
00055 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
00056 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00057 #define DAP_SWD                 1               ///< SWD Mode:  1 = available, 0 = not available
00058 
00059 /// Indicate that JTAG communication mode is available at the Debug Port.
00060 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00061 #define DAP_JTAG                0               ///< JTAG Mode: 1 = available, 0 = not available.
00062 
00063 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
00064 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
00065 #define DAP_JTAG_DEV_CNT        0               ///< Maximum number of JTAG devices on scan chain
00066 
00067 /// Default communication mode on the Debug Access Port.
00068 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
00069 #define DAP_DEFAULT_PORT        1               ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
00070 
00071 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
00072 /// Used to initialize the default SWD/JTAG clock frequency.
00073 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
00074 #define DAP_DEFAULT_SWJ_CLOCK   5000000         ///< Default SWD/JTAG clock frequency in Hz.
00075 
00076 /// Maximum Package Size for Command and Response data.
00077 /// This configuration settings is used to optimized the communication performance with the
00078 /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
00079 #define DAP_PACKET_SIZE         64              ///< USB: 64 = Full-Speed, 1024 = High-Speed.
00080 
00081 /// Maximum Package Buffers for Command and Response data.
00082 /// This configuration settings is used to optimized the communication performance with the
00083 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
00084 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
00085 #define DAP_PACKET_COUNT        64              ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
00086 
00087 /// Indicate that UART Serial Wire Output (SWO) trace is available.
00088 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00089 #define SWO_UART                0               ///< SWO UART:  1 = available, 0 = not available
00090 
00091 /// Maximum SWO UART Baudrate
00092 #define SWO_UART_MAX_BAUDRATE   10000000U       ///< SWO UART Maximum Baudrate in Hz
00093 
00094 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
00095 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00096 #define SWO_MANCHESTER          0               ///< SWO Manchester:  1 = available, 0 = not available
00097 
00098 /// SWO Trace Buffer Size.
00099 #define SWO_BUFFER_SIZE         4096U           ///< SWO Trace Buffer Size in bytes (must be 2^n)
00100 
00101 /// SWO Streaming Trace.
00102 #define SWO_STREAM              0               ///< SWO Streaming Trace: 1 = available, 0 = not available.
00103 
00104 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
00105 #define TIMESTAMP_CLOCK         1000000U      ///< Timestamp clock in Hz (0 = timestamps not supported).
00106 
00107 /// Debug Unit is connected to fixed Target Device.
00108 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
00109 /// known device.  In this case a Device Vendor and Device Name string is stored which
00110 /// may be used by the debugger or IDE to configure device parameters.
00111 #define TARGET_DEVICE_FIXED     0               ///< Target Device: 1 = known, 0 = unknown;
00112 
00113 #if TARGET_DEVICE_FIXED
00114 #define TARGET_DEVICE_VENDOR    ""              ///< String indicating the Silicon Vendor
00115 #define TARGET_DEVICE_NAME      ""              ///< String indicating the Target Device
00116 #endif
00117 
00118 ///@}
00119 
00120 //**************************************************************************************************
00121 /**
00122 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
00123 \ingroup DAP_ConfigIO_gr
00124 @{
00125 
00126 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
00127 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
00128 interface of a device. The following I/O Pins are provided:
00129 
00130 JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mode
00131 ---------------------------- | -------------------- | ---------------------------------------------
00132 TCK: Test Clock              | SWCLK: Clock         | Output Push/Pull
00133 TMS: Test Mode Select        | SWDIO: Data I/O      | Output Push/Pull; Input (for receiving data)
00134 TDI: Test Data Input         |                      | Output Push/Pull
00135 TDO: Test Data Output        |                      | Input
00136 nTRST: Test Reset (optional) |                      | Output Open Drain with pull-up resistor
00137 nRESET: Device Reset         | nRESET: Device Reset | Output Open Drain with pull-up resistor
00138 
00139 
00140 DAP Hardware I/O Pin Access Functions
00141 -------------------------------------
00142 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
00143 these I/O Pins.
00144 
00145 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
00146 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
00147 peripherals that can independently write/read a single I/O pin without affecting any other pins
00148 of the same I/O port. The following SWDIO I/O Pin functions are provided:
00149  - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
00150  - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
00151  - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
00152  - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
00153 */
00154 
00155 
00156 // Configure DAP I/O pins ------------------------------
00157 
00158 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
00159 Configures the DAP Hardware I/O pins for JTAG mode:
00160  - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
00161  - TDO to input mode.
00162 */
00163 __STATIC_INLINE void PORT_JTAG_SETUP(void)
00164 {
00165 #if (DAP_JTAG != 0)
00166 #endif
00167 }
00168 
00169 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
00170 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
00171  - SWCLK, SWDIO, nRESET to output mode and set to default high level.
00172  - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
00173 */
00174 __STATIC_INLINE void PORT_SWD_SETUP(void)
00175 {
00176     SWD_DAT_IO = 1;
00177     SWD_CLK_IO = 1;
00178     DBG_RST_IO = 1;
00179     GPIO_SetMode(SWD_DAT_GRP, (1 << SWD_DAT_BIT), GPIO_MODE_OUTPUT);
00180     GPIO_SetMode(SWD_CLK_GRP, (1 << SWD_CLK_BIT), GPIO_MODE_OUTPUT);
00181     GPIO_SetMode(DBG_RST_GRP, (1 << DBG_RST_BIT), GPIO_MODE_OUTPUT);
00182 }
00183 
00184 /** Disable JTAG/SWD I/O Pins.
00185 Disables the DAP Hardware I/O pins which configures:
00186  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
00187 */
00188 __STATIC_INLINE void PORT_OFF(void)
00189 {
00190     GPIO_SetMode(SWD_DAT_GRP, (1 << SWD_DAT_BIT), GPIO_MODE_INPUT);
00191     GPIO_SetMode(SWD_CLK_GRP, (1 << SWD_CLK_BIT), GPIO_MODE_INPUT);
00192     GPIO_SetMode(DBG_RST_GRP, (1 << DBG_RST_BIT), GPIO_MODE_INPUT);
00193 }
00194 
00195 // SWCLK/TCK I/O pin -------------------------------------
00196 
00197 /** SWCLK/TCK I/O pin: Get Input.
00198 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
00199 */
00200 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
00201 {
00202     return SWD_CLK_IO;
00203 }
00204 
00205 /** SWCLK/TCK I/O pin: Set Output to High.
00206 Set the SWCLK/TCK DAP hardware I/O pin to high level.
00207 */
00208 __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void)
00209 {
00210     SWD_CLK_IO = 1;
00211 }
00212 
00213 /** SWCLK/TCK I/O pin: Set Output to Low.
00214 Set the SWCLK/TCK DAP hardware I/O pin to low level.
00215 */
00216 __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void)
00217 {
00218     SWD_CLK_IO = 0;
00219 }
00220 
00221 // SWDIO/TMS Pin I/O --------------------------------------
00222 
00223 /** SWDIO/TMS I/O pin: Get Input.
00224 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
00225 */
00226 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
00227 {
00228     return SWD_DAT_IO;
00229 }
00230 
00231 /** SWDIO/TMS I/O pin: Set Output to High.
00232 Set the SWDIO/TMS DAP hardware I/O pin to high level.
00233 */
00234 __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void)
00235 {
00236     SWD_DAT_IO = 1;
00237 }
00238 
00239 /** SWDIO/TMS I/O pin: Set Output to Low.
00240 Set the SWDIO/TMS DAP hardware I/O pin to low level.
00241 */
00242 __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void)
00243 {
00244     SWD_DAT_IO = 0;
00245 }
00246 
00247 /** SWDIO I/O pin: Get Input (used in SWD mode only).
00248 \return Current status of the SWDIO DAP hardware I/O pin.
00249 */
00250 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
00251 {
00252     return SWD_DAT_IO;
00253 }
00254 
00255 /** SWDIO I/O pin: Set Output (used in SWD mode only).
00256 \param bit Output value for the SWDIO DAP hardware I/O pin.
00257 */
00258 __STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit)
00259 {
00260     SWD_DAT_IO = bit;
00261 }
00262 
00263 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
00264 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
00265 called prior \ref PIN_SWDIO_OUT function calls.
00266 */
00267 __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void)
00268 {
00269     GPIO_SetMode(SWD_DAT_GRP, (1 << SWD_DAT_BIT), GPIO_MODE_OUTPUT);
00270 }
00271 
00272 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
00273 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
00274 called prior \ref PIN_SWDIO_IN function calls.
00275 */
00276 __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void)
00277 {
00278     GPIO_SetMode(SWD_DAT_GRP, (1 << SWD_DAT_BIT), GPIO_MODE_INPUT);
00279 }
00280 
00281 
00282 // TDI Pin I/O ---------------------------------------------
00283 
00284 /** TDI I/O pin: Get Input.
00285 \return Current status of the TDI DAP hardware I/O pin.
00286 */
00287 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
00288 {
00289     return (0);   // Not available
00290 }
00291 
00292 /** TDI I/O pin: Set Output.
00293 \param bit Output value for the TDI DAP hardware I/O pin.
00294 */
00295 __STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit)
00296 {
00297     ;             // Not available
00298 }
00299 
00300 
00301 // TDO Pin I/O ---------------------------------------------
00302 
00303 /** TDO I/O pin: Get Input.
00304 \return Current status of the TDO DAP hardware I/O pin.
00305 */
00306 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
00307 {
00308     return (0);   // Not available
00309 }
00310 
00311 
00312 // nTRST Pin I/O -------------------------------------------
00313 
00314 /** nTRST I/O pin: Get Input.
00315 \return Current status of the nTRST DAP hardware I/O pin.
00316 */
00317 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
00318 {
00319     return (0);   // Not available
00320 }
00321 
00322 /** nTRST I/O pin: Set Output.
00323 \param bit JTAG TRST Test Reset pin status:
00324            - 0: issue a JTAG TRST Test Reset.
00325            - 1: release JTAG TRST Test Reset.
00326 */
00327 __STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit)
00328 {
00329     ;             // Not available
00330 }
00331 
00332 // nRESET Pin I/O------------------------------------------
00333 
00334 /** nRESET I/O pin: Get Input.
00335 \return Current status of the nRESET DAP hardware I/O pin.
00336 */
00337 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
00338 {
00339     return DBG_RST_IO;
00340 }
00341 
00342 /** nRESET I/O pin: Set Output.
00343 \param bit target device hardware reset pin status:
00344            - 0: issue a device hardware reset.
00345            - 1: release device hardware reset.
00346 */
00347 // TODO - sw specific implementation should be created
00348 
00349 __STATIC_FORCEINLINE void     PIN_nRESET_OUT(uint32_t bit)
00350 {
00351     DBG_RST_IO = bit;
00352 }
00353 
00354 //**************************************************************************************************
00355 /**
00356 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
00357 \ingroup DAP_ConfigIO_gr
00358 @{
00359 
00360 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
00361 
00362 It is recommended to provide the following LEDs for status indication:
00363  - Connect LED: is active when the DAP hardware is connected to a debugger.
00364  - Running LED: is active when the debugger has put the target device into running state.
00365 */
00366 
00367 /** Debug Unit: Set status of Connected LED.
00368 \param bit status of the Connect LED.
00369            - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
00370            - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
00371 */
00372 __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
00373 {
00374     LED_ISP_IO = bit ? 0 : 1;
00375 }
00376 
00377 /** Debug Unit: Set status Target Running LED.
00378 \param bit status of the Target Running LED.
00379            - 1: Target Running LED ON: program execution in target started.
00380            - 0: Target Running LED OFF: program execution in target stopped.
00381 */
00382 __STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
00383 {
00384     LED_GRE_IO = bit ? 0 : 1;
00385 }
00386 
00387 ///@}
00388 
00389 
00390 //**************************************************************************************************
00391 /**
00392 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
00393 \ingroup DAP_ConfigIO_gr
00394 @{
00395 Access function for Test Domain Timer.
00396 
00397 The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
00398 default, the DWT timer is used.  The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
00399 
00400 */
00401 
00402 /** Get timestamp of Test Domain Timer.
00403 \return Current timestamp value.
00404 */
00405 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
00406   return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
00407 }
00408 
00409 ///@}
00410 
00411 
00412 //**************************************************************************************************
00413 /**
00414 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
00415 \ingroup DAP_ConfigIO_gr
00416 @{
00417 
00418 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
00419 */
00420 
00421 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
00422 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
00423 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
00424  - I/O clock system enabled.
00425  - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
00426  - for nTRST, nRESET a weak pull-up (if available) is enabled.
00427  - LED output pins are enabled and LEDs are turned off.
00428 */
00429 __STATIC_INLINE void DAP_SETUP(void)
00430 {
00431     GPIO_SetMode(LED_ICE_GRP, (1 << LED_ICE_BIT), GPIO_MODE_OUTPUT);
00432     GPIO_SetMode(LED_ISP_GRP, (1 << LED_ISP_BIT), GPIO_MODE_OUTPUT);
00433     GPIO_SetMode(LED_GRE_GRP, (1 << LED_GRE_BIT), GPIO_MODE_OUTPUT);
00434     LED_ICE_IO = 0;
00435     LED_ISP_IO = 1;
00436     LED_GRE_IO = 1;
00437 }
00438 
00439 /** Reset Target Device with custom specific I/O pin or command sequence.
00440 This function allows the optional implementation of a device specific reset sequence.
00441 It is called when the command \ref DAP_ResetTarget and is for example required
00442 when a device needs a time-critical unlock sequence that enables the debug port.
00443 \return 0 = no device specific reset sequence is implemented.\n
00444         1 = a device specific reset sequence is implemented.
00445 */
00446 __STATIC_INLINE uint32_t RESET_TARGET(void)
00447 {
00448     return (0);              // change to '1' when a device reset sequence is implemented
00449 }
00450 
00451 ///@}
00452 
00453 
00454 #endif /* __DAP_CONFIG_H__ */