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musca_b.c
00001 /** 00002 * @file musca_b.c 00003 * @brief board ID for the ARM MUSCA B board 00004 * 00005 * DAPLink Interface Firmware 00006 * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved 00007 * SPDX-License-Identifier: Apache-2.0 00008 * 00009 * Licensed under the Apache License, Version 2.0 (the "License"); you may 00010 * not use this file except in compliance with the License. 00011 * You may obtain a copy of the License at 00012 * 00013 * http://www.apache.org/licenses/LICENSE-2.0 00014 * 00015 * Unless required by applicable law or agreed to in writing, software 00016 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 00017 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00018 * See the License for the specific language governing permissions and 00019 * limitations under the License. 00020 */ 00021 00022 #include "stdbool.h" 00023 #include "virtual_fs.h" 00024 #include "flash_manager.h" 00025 #include "IO_Config.h" 00026 #include "target_board.h" 00027 #include "target_family.h" 00028 #include "power_ctrl.h" 00029 00030 uint8_t gpio_get_pbon_btn() 00031 { 00032 return LPC_GPIO->PIN[PIN_PBON_PORT] & PIN_PBON ? 0 : 1; 00033 } 00034 00035 static void prerun_board_config(void) 00036 { 00037 /* configure MUSCA specific gpio */ 00038 // configure PBON as input 00039 PIN_PBON_IOCON = PIN_PBON_IOCON_INIT; 00040 LPC_GPIO->DIR[PIN_PBON_PORT] &= ~PIN_PBON; 00041 // configure PWROK as output 00042 PIN_PWROK_IOCON = PIN_PWROK_IOCON_INIT; 00043 LPC_GPIO->CLR[PIN_PWROK_PORT] = PIN_PWROK; 00044 LPC_GPIO->DIR[PIN_PWROK_PORT] |= PIN_PWROK; 00045 // configure SHUTDOWN as input 00046 PIN_SHUTDOWN_IOCON = PIN_SHUTDOWN_IOCON_INIT; 00047 LPC_GPIO->DIR[PIN_SHUTDOWN_PORT] &= ~PIN_SHUTDOWN; 00048 // configure CB_nRST as output 00049 PIN_CB_nRST_IOCON = PIN_CB_nRST_IOCON_INIT; 00050 LPC_GPIO->CLR[PIN_CB_nRST_PORT] = PIN_CB_nRST; 00051 LPC_GPIO->DIR[PIN_CB_nRST_PORT] |= PIN_CB_nRST; 00052 // configure CFG_nRST as output 00053 PIN_CFG_nRST_IOCON = PIN_CFG_nRST_IOCON_INIT; 00054 LPC_GPIO->CLR[PIN_CFG_nRST_PORT] = PIN_CFG_nRST; 00055 LPC_GPIO->DIR[PIN_CFG_nRST_PORT] |= PIN_CFG_nRST; 00056 // configure SCC_LOAD as output 00057 PIN_SCC_LOAD_IOCON = PIN_SCC_LOAD_IOCON_INIT; 00058 LPC_GPIO->CLR[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD; 00059 LPC_GPIO->DIR[PIN_SCC_LOAD_PORT] |= PIN_SCC_LOAD; 00060 // configure SCC_WNR as output 00061 PIN_SCC_WNR_IOCON = PIN_SCC_WNR_IOCON_INIT; 00062 LPC_GPIO->CLR[PIN_SCC_WNR_PORT] = PIN_SCC_WNR; 00063 LPC_GPIO->DIR[PIN_SCC_WNR_PORT] |= PIN_SCC_WNR; 00064 // configure SCC_DATAIN as output 00065 PIN_SCC_DATAIN_IOCON = PIN_SCC_DATAIN_IOCON_INIT; 00066 LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN; 00067 LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT] |= PIN_SCC_DATAIN; 00068 // configure SCC_CLK as output 00069 PIN_SCC_CLK_IOCON = PIN_SCC_CLK_IOCON_INIT; 00070 LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK; 00071 LPC_GPIO->DIR[PIN_SCC_CLK_PORT] |= PIN_SCC_CLK; 00072 // configure SCC_DATAOUT as input 00073 PIN_SCC_DATAOUT_IOCON = PIN_SCC_DATAOUT_IOCON_INIT; 00074 LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT; 00075 // configure CS_nDET as input 00076 PIN_CS_nDET_IOCON = PIN_CS_nDET_IOCON_INIT; 00077 LPC_GPIO->DIR[PIN_CS_nDET_PORT] &= ~PIN_CS_nDET; 00078 // configure PIN_I2C_SCL as OC output 00079 PIN_I2C_SCL_IOCON = PIN_I2C_SCL_IOCON_INIT; 00080 LPC_GPIO->DIR[PIN_I2C_SCL_PORT] &= ~PIN_I2C_SCL; 00081 // configure PIN_I2C_SDA as OC output 00082 PIN_I2C_SDA_IOCON = PIN_I2C_SDA_IOCON_INIT; 00083 LPC_GPIO->DIR[PIN_I2C_SDA_PORT] &= ~PIN_I2C_SDA; 00084 00085 // Setup I2CIO expander 00086 i2cio_init(); 00087 00088 PIN_USART_IOCON = PIN_USART_IOCON_INIT; 00089 00090 // Turn ON power 00091 i2cio_power_on(); 00092 00093 power_on_sequence(); 00094 00095 flash_manager_set_page_erase(true); 00096 } 00097 00098 const board_info_t g_board_info = { 00099 .board_id = "5007", 00100 .daplink_drive_name = "MBED ", 00101 .target_cfg = &target_device, 00102 .prerun_board_config = prerun_board_config, 00103 };
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