syscon.h

00001 /**
00002  * @file    syscon.h
00003  * @brief   System Controller serial interface
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2017-2019, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 /* Define to prevent recursive inclusion ------------------------------------ */
00023 #ifndef __SYSCON_H
00024 #define __SYSCON_H
00025 
00026 /* SCC registers */
00027 #define SCC_RESET_CTRL     0x00                     // RESET Control register
00028 #define SCC_CLK_CTRL       0x04                     // CLOCK Control register
00029 #define SCC_PWR_CTRL       0x08                     // Power Control register
00030 #define SCC_PLL_CTRL       0x0C                     // System Clock divider register
00031 #define SCC_DBG_CTRL       0x10                     // Debug Security override
00032 #define SCC_SRAM_CTRL      0x14                     // SRAM Bank power gate enable
00033 #define SCC_INTR_CTRL      0x18                     // Combined interrupt mask
00034 #define SCC_CORDIO_CTRL    0x1C                     // REF to LLC Control and multiplex
00035 #define SCC_CPU0_VTOR_SRAM 0x20                     // CPU0 SRAM Boot vector
00036 #define SCC_SPARE0         0x24                     // CPU0 Spare
00037 #define SCC_CPU1_VTOR_SRAM 0x28                     // CPU1 SRAM Boot vector
00038 #define SCC_SPARE1         0x2C                     // CPU1 Spare
00039 
00040 void syscon_readreg(unsigned int addr, unsigned int *din);
00041 void syscon_writereg(unsigned int addr, unsigned int dout);
00042 
00043 #endif