musca_a.c

00001 /**
00002  * @file    musca_a.c
00003  * @brief   board ID for the ARM MUSCA A board
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2019, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 #include "stdbool.h"
00023 #include "virtual_fs.h"
00024 #include "flash_manager.h"
00025 #include "IO_Config.h"
00026 #include "target_board.h"
00027 #include "target_family.h"
00028 
00029 void power_on_sequence(void);
00030 
00031 uint8_t gpio_get_pbon_btn()
00032 {
00033     return LPC_GPIO->PIN[PIN_PBON_PORT] & PIN_PBON ? 0 : 1;
00034 }
00035 
00036 static void prerun_board_config(void)
00037 {
00038     /* configure MUSCA specific gpio */
00039     // configure PBON as input
00040     PIN_PBON_IOCON = PIN_PBON_IOCON_INIT;
00041     LPC_GPIO->DIR[PIN_PBON_PORT] &= ~PIN_PBON;
00042     // configure PSUON as output
00043     PIN_PSUON_IOCON = PIN_PSUON_IOCON_INIT;
00044     LPC_GPIO->CLR[PIN_PSUON_PORT] = PIN_PSUON;
00045     LPC_GPIO->DIR[PIN_PSUON_PORT] |= PIN_PSUON;
00046     // configure SHUTDOWN as input
00047     PIN_SHUTDOWN_IOCON = PIN_SHUTDOWN_IOCON_INIT;
00048     LPC_GPIO->DIR[PIN_SHUTDOWN_PORT] &= ~PIN_SHUTDOWN;
00049     // configure CB_nRST as output
00050     PIN_CB_nRST_IOCON = PIN_CB_nRST_IOCON_INIT;
00051     LPC_GPIO->CLR[PIN_CB_nRST_PORT] = PIN_CB_nRST;
00052     LPC_GPIO->DIR[PIN_CB_nRST_PORT] |= PIN_CB_nRST;
00053     // configure CFG_nRST as output
00054     PIN_CFG_nRST_IOCON = PIN_CFG_nRST_IOCON_INIT;
00055     LPC_GPIO->CLR[PIN_CFG_nRST_PORT] = PIN_CFG_nRST;
00056     LPC_GPIO->DIR[PIN_CFG_nRST_PORT] |= PIN_CFG_nRST;
00057     // configure SCC_LOAD as output
00058     PIN_SCC_LOAD_IOCON = PIN_SCC_LOAD_IOCON_INIT;
00059     LPC_GPIO->CLR[PIN_SCC_LOAD_PORT] = PIN_SCC_LOAD;
00060     LPC_GPIO->DIR[PIN_SCC_LOAD_PORT] |= PIN_SCC_LOAD;
00061     // configure SCC_WNR as output
00062     PIN_SCC_WNR_IOCON = PIN_SCC_WNR_IOCON_INIT;
00063     LPC_GPIO->CLR[PIN_SCC_WNR_PORT] = PIN_SCC_WNR;
00064     LPC_GPIO->DIR[PIN_SCC_WNR_PORT] |= PIN_SCC_WNR;
00065     // configure SCC_DATAIN as output
00066     PIN_SCC_DATAIN_IOCON = PIN_SCC_DATAIN_IOCON_INIT;
00067     LPC_GPIO->CLR[PIN_SCC_DATAIN_PORT] = PIN_SCC_DATAIN;
00068     LPC_GPIO->DIR[PIN_SCC_DATAIN_PORT] |= PIN_SCC_DATAIN;
00069     // configure SCC_CLK as output
00070     PIN_SCC_CLK_IOCON = PIN_SCC_CLK_IOCON_INIT;
00071     LPC_GPIO->CLR[PIN_SCC_CLK_PORT] = PIN_SCC_CLK;
00072     LPC_GPIO->DIR[PIN_SCC_CLK_PORT] |= PIN_SCC_CLK;
00073     // configure SCC_DATAOUT as input
00074     PIN_SCC_DATAOUT_IOCON = PIN_SCC_DATAOUT_IOCON_INIT;
00075     LPC_GPIO->DIR[PIN_SCC_DATAOUT_PORT] &= ~PIN_SCC_DATAOUT;
00076     // configure CS_nDET as input
00077     PIN_CS_nDET_IOCON = PIN_CS_nDET_IOCON_INIT;
00078     LPC_GPIO->DIR[PIN_CS_nDET_PORT] &= ~PIN_CS_nDET;
00079 
00080     PIN_USART_IOCON = PIN_USART_IOCON_INIT;
00081 
00082     // Switch on power supply - PSUON
00083     LPC_GPIO->SET[PIN_PSUON_PORT] = PIN_PSUON;
00084 
00085     power_on_sequence();
00086 
00087     flash_manager_set_page_erase(true);
00088 }
00089 
00090 const board_info_t g_board_info = {
00091     .board_id = "5006",
00092     .daplink_drive_name =     "MBED       ",
00093     .target_cfg = &target_device,
00094     .prerun_board_config = prerun_board_config,
00095 };