mpu_armv8.h

00001 /******************************************************************************
00002  * @file     mpu_armv8.h
00003  * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
00004  * @version  V5.1.1
00005  * @date     09. August 2019
00006  ******************************************************************************/
00007 /*
00008  * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
00009  *
00010  * SPDX-License-Identifier: Apache-2.0
00011  *
00012  * Licensed under the Apache License, Version 2.0 (the License); you may
00013  * not use this file except in compliance with the License.
00014  * You may obtain a copy of the License at
00015  *
00016  * www.apache.org/licenses/LICENSE-2.0
00017  *
00018  * Unless required by applicable law or agreed to in writing, software
00019  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00020  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00021  * See the License for the specific language governing permissions and
00022  * limitations under the License.
00023  */
00024 
00025 #if   defined ( __ICCARM__ )
00026   #pragma system_include         /* treat file as system include file for MISRA check */
00027 #elif defined (__clang__)
00028   #pragma clang system_header    /* treat file as system include file */
00029 #endif
00030 
00031 #ifndef ARM_MPU_ARMV8_H
00032 #define ARM_MPU_ARMV8_H
00033 
00034 /** \brief Attribute for device memory (outer only) */
00035 #define ARM_MPU_ATTR_DEVICE                           ( 0U )
00036 
00037 /** \brief Attribute for non-cacheable, normal memory */
00038 #define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
00039 
00040 /** \brief Attribute for normal memory (outer and inner)
00041 * \param NT Non-Transient: Set to 1 for non-transient data.
00042 * \param WB Write-Back: Set to 1 to use write-back update policy.
00043 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
00044 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
00045 */
00046 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
00047   ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
00048 
00049 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
00050 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
00051 
00052 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
00053 #define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
00054 
00055 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
00056 #define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
00057 
00058 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
00059 #define ARM_MPU_ATTR_DEVICE_GRE    (3U)
00060 
00061 /** \brief Memory Attribute
00062 * \param O Outer memory attributes
00063 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
00064 */
00065 #define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
00066 
00067 /** \brief Normal memory non-shareable  */
00068 #define ARM_MPU_SH_NON   (0U)
00069 
00070 /** \brief Normal memory outer shareable  */
00071 #define ARM_MPU_SH_OUTER (2U)
00072 
00073 /** \brief Normal memory inner shareable  */
00074 #define ARM_MPU_SH_INNER (3U)
00075 
00076 /** \brief Memory access permissions
00077 * \param RO Read-Only: Set to 1 for read-only memory.
00078 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
00079 */
00080 #define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
00081 
00082 /** \brief Region Base Address Register value
00083 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
00084 * \param SH Defines the Shareability domain for this memory region.
00085 * \param RO Read-Only: Set to 1 for a read-only memory region.
00086 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
00087 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
00088 */
00089 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
00090   (((BASE) & MPU_RBAR_BASE_Msk) | \
00091   (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
00092   ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
00093   (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
00094 
00095 /** \brief Region Limit Address Register value
00096 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
00097 * \param IDX The attribute index to be associated with this memory region.
00098 */
00099 #define ARM_MPU_RLAR(LIMIT, IDX) \
00100   (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
00101   (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
00102   (MPU_RLAR_EN_Msk))
00103 
00104 #if defined(MPU_RLAR_PXN_Pos)
00105   
00106 /** \brief Region Limit Address Register with PXN value
00107 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
00108 * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
00109 * \param IDX The attribute index to be associated with this memory region.
00110 */
00111 #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
00112   (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
00113   (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
00114   (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
00115   (MPU_RLAR_EN_Msk))
00116   
00117 #endif
00118 
00119 /**
00120 * Struct for a single MPU Region
00121 */
00122 typedef struct {
00123   uint32_t RBAR;                   /*!< Region Base Address Register value */
00124   uint32_t RLAR ;                   /*!< Region Limit Address Register value */
00125 } ARM_MPU_Region_t;
00126     
00127 /** Enable the MPU.
00128 * \param MPU_Control Default access permissions for unconfigured regions.
00129 */
00130 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
00131 {
00132   MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
00133 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
00134   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
00135 #endif
00136   __DSB();
00137   __ISB();
00138 }
00139 
00140 /** Disable the MPU.
00141 */
00142 __STATIC_INLINE void ARM_MPU_Disable(void)
00143 {
00144   __DMB();
00145 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
00146   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
00147 #endif
00148   MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
00149 }
00150 
00151 #ifdef MPU_NS
00152 /** Enable the Non-secure MPU.
00153 * \param MPU_Control Default access permissions for unconfigured regions.
00154 */
00155 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
00156 {
00157   MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
00158 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
00159   SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
00160 #endif
00161   __DSB();
00162   __ISB();
00163 }
00164 
00165 /** Disable the Non-secure MPU.
00166 */
00167 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
00168 {
00169   __DMB();
00170 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
00171   SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
00172 #endif
00173   MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
00174 }
00175 #endif
00176 
00177 /** Set the memory attribute encoding to the given MPU.
00178 * \param mpu Pointer to the MPU to be configured.
00179 * \param idx The attribute index to be set [0-7]
00180 * \param attr The attribute value to be set.
00181 */
00182 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
00183 {
00184   const uint8_t reg = idx / 4U;
00185   const uint32_t pos = ((idx % 4U) * 8U);
00186   const uint32_t mask = 0xFFU << pos;
00187   
00188   if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
00189     return; // invalid index
00190   }
00191   
00192   mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
00193 }
00194 
00195 /** Set the memory attribute encoding.
00196 * \param idx The attribute index to be set [0-7]
00197 * \param attr The attribute value to be set.
00198 */
00199 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
00200 {
00201   ARM_MPU_SetMemAttrEx(MPU, idx, attr);
00202 }
00203 
00204 #ifdef MPU_NS
00205 /** Set the memory attribute encoding to the Non-secure MPU.
00206 * \param idx The attribute index to be set [0-7]
00207 * \param attr The attribute value to be set.
00208 */
00209 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
00210 {
00211   ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
00212 }
00213 #endif
00214 
00215 /** Clear and disable the given MPU region of the given MPU.
00216 * \param mpu Pointer to MPU to be used.
00217 * \param rnr Region number to be cleared.
00218 */
00219 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
00220 {
00221   mpu->RNR = rnr;
00222   mpu->RLAR = 0U;
00223 }
00224 
00225 /** Clear and disable the given MPU region.
00226 * \param rnr Region number to be cleared.
00227 */
00228 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
00229 {
00230   ARM_MPU_ClrRegionEx(MPU, rnr);
00231 }
00232 
00233 #ifdef MPU_NS
00234 /** Clear and disable the given Non-secure MPU region.
00235 * \param rnr Region number to be cleared.
00236 */
00237 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
00238 {  
00239   ARM_MPU_ClrRegionEx(MPU_NS, rnr);
00240 }
00241 #endif
00242 
00243 /** Configure the given MPU region of the given MPU.
00244 * \param mpu Pointer to MPU to be used.
00245 * \param rnr Region number to be configured.
00246 * \param rbar Value for RBAR register.
00247 * \param rlar Value for RLAR register.
00248 */   
00249 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
00250 {
00251   mpu->RNR = rnr;
00252   mpu->RBAR = rbar;
00253   mpu->RLAR = rlar;
00254 }
00255 
00256 /** Configure the given MPU region.
00257 * \param rnr Region number to be configured.
00258 * \param rbar Value for RBAR register.
00259 * \param rlar Value for RLAR register.
00260 */   
00261 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
00262 {
00263   ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
00264 }
00265 
00266 #ifdef MPU_NS
00267 /** Configure the given Non-secure MPU region.
00268 * \param rnr Region number to be configured.
00269 * \param rbar Value for RBAR register.
00270 * \param rlar Value for RLAR register.
00271 */   
00272 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
00273 {
00274   ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
00275 }
00276 #endif
00277 
00278 /** Memcopy with strictly ordered memory access, e.g. for register targets.
00279 * \param dst Destination data is copied to.
00280 * \param src Source data is copied from.
00281 * \param len Amount of data words to be copied.
00282 */
00283 __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
00284 {
00285   uint32_t i;
00286   for (i = 0U; i < len; ++i) 
00287   {
00288     dst[i] = src[i];
00289   }
00290 }
00291 
00292 /** Load the given number of MPU regions from a table to the given MPU.
00293 * \param mpu Pointer to the MPU registers to be used.
00294 * \param rnr First region number to be configured.
00295 * \param table Pointer to the MPU configuration table.
00296 * \param cnt Amount of regions to be configured.
00297 */
00298 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
00299 {
00300   const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
00301   if (cnt == 1U) {
00302     mpu->RNR = rnr;
00303     ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
00304   } else {
00305     uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
00306     uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
00307     
00308     mpu->RNR = rnrBase;
00309     while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
00310       uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
00311       ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
00312       table += c;
00313       cnt -= c;
00314       rnrOffset = 0U;
00315       rnrBase += MPU_TYPE_RALIASES;
00316       mpu->RNR = rnrBase;
00317     }
00318     
00319     ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
00320   }
00321 }
00322 
00323 /** Load the given number of MPU regions from a table.
00324 * \param rnr First region number to be configured.
00325 * \param table Pointer to the MPU configuration table.
00326 * \param cnt Amount of regions to be configured.
00327 */
00328 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
00329 {
00330   ARM_MPU_LoadEx(MPU, rnr, table, cnt);
00331 }
00332 
00333 #ifdef MPU_NS
00334 /** Load the given number of MPU regions from a table to the Non-secure MPU.
00335 * \param rnr First region number to be configured.
00336 * \param table Pointer to the MPU configuration table.
00337 * \param cnt Amount of regions to be configured.
00338 */
00339 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
00340 {
00341   ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
00342 }
00343 #endif
00344 
00345 #endif
00346