mpu_armv7.h

00001 /******************************************************************************
00002  * @file     mpu_armv7.h
00003  * @brief    CMSIS MPU API for Armv7-M MPU
00004  * @version  V5.1.0
00005  * @date     08. March 2019
00006  ******************************************************************************/
00007 /*
00008  * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
00009  *
00010  * SPDX-License-Identifier: Apache-2.0
00011  *
00012  * Licensed under the Apache License, Version 2.0 (the License); you may
00013  * not use this file except in compliance with the License.
00014  * You may obtain a copy of the License at
00015  *
00016  * www.apache.org/licenses/LICENSE-2.0
00017  *
00018  * Unless required by applicable law or agreed to in writing, software
00019  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00020  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00021  * See the License for the specific language governing permissions and
00022  * limitations under the License.
00023  */
00024  
00025 #if   defined ( __ICCARM__ )
00026   #pragma system_include         /* treat file as system include file for MISRA check */
00027 #elif defined (__clang__)
00028   #pragma clang system_header    /* treat file as system include file */
00029 #endif
00030  
00031 #ifndef ARM_MPU_ARMV7_H
00032 #define ARM_MPU_ARMV7_H
00033 
00034 #define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
00035 #define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
00036 #define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
00037 #define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
00038 #define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
00039 #define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
00040 #define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
00041 #define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
00042 #define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
00043 #define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
00044 #define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
00045 #define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
00046 #define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
00047 #define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
00048 #define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
00049 #define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
00050 #define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
00051 #define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
00052 #define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
00053 #define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
00054 #define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
00055 #define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
00056 #define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
00057 #define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
00058 #define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
00059 #define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
00060 #define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
00061 #define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
00062 
00063 #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
00064 #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
00065 #define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
00066 #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
00067 #define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
00068 #define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
00069 
00070 /** MPU Region Base Address Register Value
00071 *
00072 * \param Region The region to be configured, number 0 to 15.
00073 * \param BaseAddress The base address for the region.
00074 */
00075 #define ARM_MPU_RBAR(Region, BaseAddress) \
00076   (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
00077    ((Region) & MPU_RBAR_REGION_Msk)    |  \
00078    (MPU_RBAR_VALID_Msk))
00079 
00080 /**
00081 * MPU Memory Access Attributes
00082 * 
00083 * \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
00084 * \param IsShareable       Region is shareable between multiple bus masters.
00085 * \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
00086 * \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
00087 */  
00088 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
00089   ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
00090    (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
00091    (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
00092    (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
00093 
00094 /**
00095 * MPU Region Attribute and Size Register Value
00096 * 
00097 * \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
00098 * \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
00099 * \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
00100 * \param SubRegionDisable  Sub-region disable field.
00101 * \param Size              Region size of the region to be configured, for example 4K, 8K.
00102 */
00103 #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
00104   ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
00105    (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
00106    (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
00107    (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
00108    (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
00109    (((MPU_RASR_ENABLE_Msk))))
00110 
00111 /**
00112 * MPU Region Attribute and Size Register Value
00113 * 
00114 * \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
00115 * \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
00116 * \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
00117 * \param IsShareable       Region is shareable between multiple bus masters.
00118 * \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
00119 * \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
00120 * \param SubRegionDisable  Sub-region disable field.
00121 * \param Size              Region size of the region to be configured, for example 4K, 8K.
00122 */                         
00123 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
00124   ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
00125 
00126 /**
00127 * MPU Memory Access Attribute for strongly ordered memory.
00128 *  - TEX: 000b
00129 *  - Shareable
00130 *  - Non-cacheable
00131 *  - Non-bufferable
00132 */ 
00133 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
00134 
00135 /**
00136 * MPU Memory Access Attribute for device memory.
00137 *  - TEX: 000b (if shareable) or 010b (if non-shareable)
00138 *  - Shareable or non-shareable
00139 *  - Non-cacheable
00140 *  - Bufferable (if shareable) or non-bufferable (if non-shareable)
00141 *
00142 * \param IsShareable Configures the device memory as shareable or non-shareable.
00143 */ 
00144 #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
00145 
00146 /**
00147 * MPU Memory Access Attribute for normal memory.
00148 *  - TEX: 1BBb (reflecting outer cacheability rules)
00149 *  - Shareable or non-shareable
00150 *  - Cacheable or non-cacheable (reflecting inner cacheability rules)
00151 *  - Bufferable or non-bufferable (reflecting inner cacheability rules)
00152 *
00153 * \param OuterCp Configures the outer cache policy.
00154 * \param InnerCp Configures the inner cache policy.
00155 * \param IsShareable Configures the memory as shareable or non-shareable.
00156 */ 
00157 #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
00158 
00159 /**
00160 * MPU Memory Access Attribute non-cacheable policy.
00161 */
00162 #define ARM_MPU_CACHEP_NOCACHE 0U
00163 
00164 /**
00165 * MPU Memory Access Attribute write-back, write and read allocate policy.
00166 */
00167 #define ARM_MPU_CACHEP_WB_WRA 1U
00168 
00169 /**
00170 * MPU Memory Access Attribute write-through, no write allocate policy.
00171 */
00172 #define ARM_MPU_CACHEP_WT_NWA 2U
00173 
00174 /**
00175 * MPU Memory Access Attribute write-back, no write allocate policy.
00176 */
00177 #define ARM_MPU_CACHEP_WB_NWA 3U
00178 
00179 
00180 /**
00181 * Struct for a single MPU Region
00182 */
00183 typedef struct {
00184   uint32_t RBAR; //!< The region base address register value (RBAR)
00185   uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
00186 } ARM_MPU_Region_t;
00187     
00188 /** Enable the MPU.
00189 * \param MPU_Control Default access permissions for unconfigured regions.
00190 */
00191 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
00192 {
00193   MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
00194 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
00195   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
00196 #endif
00197   __DSB();
00198   __ISB();
00199 }
00200 
00201 /** Disable the MPU.
00202 */
00203 __STATIC_INLINE void ARM_MPU_Disable(void)
00204 {
00205   __DMB();
00206 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
00207   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
00208 #endif
00209   MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
00210 }
00211 
00212 /** Clear and disable the given MPU region.
00213 * \param rnr Region number to be cleared.
00214 */
00215 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
00216 {
00217   MPU->RNR = rnr;
00218   MPU->RASR = 0U;
00219 }
00220 
00221 /** Configure an MPU region.
00222 * \param rbar Value for RBAR register.
00223 * \param rsar Value for RSAR register.
00224 */   
00225 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
00226 {
00227   MPU->RBAR = rbar;
00228   MPU->RASR = rasr;
00229 }
00230 
00231 /** Configure the given MPU region.
00232 * \param rnr Region number to be configured.
00233 * \param rbar Value for RBAR register.
00234 * \param rsar Value for RSAR register.
00235 */   
00236 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
00237 {
00238   MPU->RNR = rnr;
00239   MPU->RBAR = rbar;
00240   MPU->RASR = rasr;
00241 }
00242 
00243 /** Memcopy with strictly ordered memory access, e.g. for register targets.
00244 * \param dst Destination data is copied to.
00245 * \param src Source data is copied from.
00246 * \param len Amount of data words to be copied.
00247 */
00248 __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
00249 {
00250   uint32_t i;
00251   for (i = 0U; i < len; ++i) 
00252   {
00253     dst[i] = src[i];
00254   }
00255 }
00256 
00257 /** Load the given number of MPU regions from a table.
00258 * \param table Pointer to the MPU configuration table.
00259 * \param cnt Amount of regions to be configured.
00260 */
00261 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
00262 {
00263   const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
00264   while (cnt > MPU_TYPE_RALIASES) {
00265     ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
00266     table += MPU_TYPE_RALIASES;
00267     cnt -= MPU_TYPE_RALIASES;
00268   }
00269   ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
00270 }
00271 
00272 #endif