IO_Config.h

00001 /**
00002  * @file    IO_Config.h
00003  * @brief
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 #ifndef __IO_CONFIG_H__
00023 #define __IO_CONFIG_H__
00024 
00025 #include "max32625.h"
00026 
00027 #define EN_VDDIOH_PORT      3
00028 #define EN_VDDIOH_PIN       6
00029 
00030 // The MAX14689 is powered with this pin
00031 #define IOH_OW_EN_PORT      2
00032 #define IOH_OW_EN_PIN       2
00033 
00034 // Low selects NC pins HDR_OW and HDR_VIO
00035 // High selcts NO pins SWD_OW and SWD_VIO
00036 #define SWD_DIP_SEL_PORT    2
00037 #define SWD_DIP_SEL_PIN     3
00038 
00039 // UART Tx
00040 #define PIN_TX_PORT         2
00041 #define PIN_TX_PIN          0
00042 #define PIN_DIP_TX_PORT     0
00043 #define PIN_DIP_TX_PIN      0
00044 
00045 // UART Rx
00046 #define PIN_RX_PORT         2
00047 #define PIN_RX_PIN          1
00048 #define PIN_DIP_RX_PORT     0
00049 #define PIN_DIP_RX_PIN      1
00050 
00051 // DAP LED
00052 #define PIN_DAP_LED_PORT    2
00053 #define PIN_DAP_LED_PIN     5
00054 
00055 // MSD LED
00056 #define PIN_MSD_LED_PORT    2
00057 #define PIN_MSD_LED_PIN     4
00058 
00059 // CDC LED
00060 #define PIN_CDC_LED_PORT    2
00061 #define PIN_CDC_LED_PIN     6
00062 
00063 // Non-Forwarded Reset In Pin
00064 #define PIN_RESET_IN_NO_FWRD_PORT  2
00065 #define PIN_RESET_IN_NO_FWRD_PIN   7
00066 
00067 // nRESET
00068 #define PIN_nRESET_PORT     3
00069 #define PIN_nRESET_PIN      7
00070 #define PIN_DIP_nRESET_PORT 0
00071 #define PIN_DIP_nRESET_PIN  4
00072 
00073 // SWCLK
00074 #define PIN_SWCLK_PORT      3
00075 #define PIN_SWCLK_PIN       2
00076 #define PIN_DIP_SWCLK_PORT  0
00077 #define PIN_DIP_SWCLK_PIN   2
00078 
00079 // SWDIO
00080 #define PIN_SWDIO_PORT      3
00081 #define PIN_SWDIO_PIN       3
00082 #define PIN_DIP_SWDIO_PORT  0
00083 #define PIN_DIP_SWDIO_PIN   3
00084 
00085 // 1-Wire master I/O
00086 #define OWM_PORT            4
00087 #define OWM_PIN             0
00088 #define OWM_SUP_PORT        4
00089 #define OWM_SUP_PIN         1
00090 
00091 // ADC channels for target detection
00092 #define SWD_VIO_CH          5
00093 #define HDR_VIO_CH          4
00094 #define SWD_GNDDET_CH       3
00095 #define HDR_GNDDET_CH       2
00096 
00097 typedef enum {
00098     IO_SWD_EXT,
00099     IO_DIP_EXT
00100 } TARGET_INTERFACE;
00101 
00102 #define CDC_ACM_UART_SWD 2
00103 #define CDC_ACM_UART_DIP 0
00104 
00105 #endif