DAP_config.h

00001 /**
00002  * @file    DAP_config.h
00003  * @brief
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 #ifndef __DAP_CONFIG_H__
00023 #define __DAP_CONFIG_H__
00024 
00025 //**************************************************************************************************
00026 /**
00027 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
00028 \ingroup DAP_ConfigIO_gr
00029 @{
00030 Provides definitions about:
00031  - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
00032  - Debug Unit communication packet size.
00033  - Debug Access Port communication mode (JTAG or SWD).
00034  - Optional information about a connected Target Device (for Evaluation Boards).
00035 */
00036 
00037 #include <stdio.h>
00038 #include "max32625.h"
00039 #include "clkman_regs.h"
00040 #include "gpio_regs.h"
00041 #include "IO_Config.h"
00042 
00043 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
00044 /// This value is used to calculate the SWD/JTAG clock speed.
00045 #define CPU_CLOCK               SystemCoreClock        ///< Specifies the CPU Clock in Hz
00046 
00047 /// Number of processor cycles for I/O Port write operations.
00048 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
00049 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
00050 /// require 2 processor cycles for a I/O Port Write operation.  If the Debug Unit uses
00051 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
00052 /// required.
00053 #define IO_PORT_WRITE_CYCLES    2               ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
00054 
00055 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
00056 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00057 #define DAP_SWD                 1               ///< SWD Mode:  1 = available, 0 = not available
00058 
00059 /// Indicate that JTAG communication mode is available at the Debug Port.
00060 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00061 #define DAP_JTAG                0               ///< JTAG Mode: 1 = available, 0 = not available.
00062 
00063 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
00064 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
00065 #define DAP_JTAG_DEV_CNT        0               ///< Maximum number of JTAG devices on scan chain
00066 
00067 /// Default communication mode on the Debug Access Port.
00068 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
00069 #define DAP_DEFAULT_PORT        1               ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
00070 
00071 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
00072 /// Used to initialize the default SWD/JTAG clock frequency.
00073 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
00074 #define DAP_DEFAULT_SWJ_CLOCK   5000000         ///< Default SWD/JTAG clock frequency in Hz.
00075 
00076 /// Maximum Package Size for Command and Response data.
00077 /// This configuration settings is used to optimized the communication performance with the
00078 /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
00079 #define DAP_PACKET_SIZE         64              ///< USB: 64 = Full-Speed, 1024 = High-Speed.
00080 
00081 /// Maximum Package Buffers for Command and Response data.
00082 /// This configuration settings is used to optimized the communication performance with the
00083 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
00084 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
00085 #define DAP_PACKET_COUNT        4              ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
00086 
00087 /// Indicate that UART Serial Wire Output (SWO) trace is available.
00088 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00089 #define SWO_UART                0               ///< SWO UART:  1 = available, 0 = not available
00090 
00091 /// Maximum SWO UART Baudrate
00092 #define SWO_UART_MAX_BAUDRATE   10000000U       ///< SWO UART Maximum Baudrate in Hz
00093 
00094 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
00095 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00096 #define SWO_MANCHESTER          0               ///< SWO Manchester:  1 = available, 0 = not available
00097 
00098 /// SWO Trace Buffer Size.
00099 #define SWO_BUFFER_SIZE         4096U           ///< SWO Trace Buffer Size in bytes (must be 2^n)
00100 
00101 /// SWO Streaming Trace.
00102 #define SWO_STREAM              0               ///< SWO Streaming Trace: 1 = available, 0 = not available.
00103 
00104 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
00105 #define TIMESTAMP_CLOCK         1000000U      ///< Timestamp clock in Hz (0 = timestamps not supported).
00106 
00107 /// Debug Unit is connected to fixed Target Device.
00108 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
00109 /// known device.  In this case a Device Vendor and Device Name string is stored which
00110 /// may be used by the debugger or IDE to configure device parameters.
00111 #define TARGET_DEVICE_FIXED     0               ///< Target Device: 1 = known, 0 = unknown;
00112 
00113 #if TARGET_DEVICE_FIXED
00114 #define TARGET_DEVICE_VENDOR    ""              ///< String indicating the Silicon Vendor
00115 #define TARGET_DEVICE_NAME      ""              ///< String indicating the Target Device
00116 #endif
00117 
00118 ///@}
00119 
00120 //**************************************************************************************************
00121 /**
00122 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
00123 \ingroup DAP_ConfigIO_gr
00124 @{
00125 
00126 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
00127 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
00128 interface of a device. The following I/O Pins are provided:
00129 
00130 JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mode
00131 ---------------------------- | -------------------- | ---------------------------------------------
00132 TCK: Test Clock              | SWCLK: Clock         | Output Push/Pull
00133 TMS: Test Mode Select        | SWDIO: Data I/O      | Output Push/Pull; Input (for receiving data)
00134 TDI: Test Data Input         |                      | Output Push/Pull
00135 TDO: Test Data Output        |                      | Input
00136 nTRST: Test Reset (optional) |                      | Output Open Drain with pull-up resistor
00137 nRESET: Device Reset         | nRESET: Device Reset | Output Open Drain with pull-up resistor
00138 
00139 
00140 DAP Hardware I/O Pin Access Functions
00141 -------------------------------------
00142 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
00143 these I/O Pins.
00144 
00145 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
00146 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
00147 peripherals that can independently write/read a single I/O pin without affecting any other pins
00148 of the same I/O port. The following SWDIO I/O Pin functions are provided:
00149  - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
00150  - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
00151  - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
00152  - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
00153 */
00154 
00155 extern volatile uint32_t *tck_in;
00156 extern volatile uint32_t *tck_out;
00157 extern volatile uint32_t *tms_in;
00158 extern volatile uint32_t *tms_out;
00159 extern volatile uint32_t *rst_in;
00160 extern volatile uint32_t *rst_out;
00161 
00162 extern uint32_t swdio_port;
00163 extern uint32_t swdio_pin;
00164 extern uint32_t swclk_port;
00165 extern uint32_t swclk_pin;
00166 extern uint32_t nreset_port;
00167 extern uint32_t nreset_pin;
00168 
00169 // Configure DAP I/O pins ------------------------------
00170 
00171 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
00172 Configures the DAP Hardware I/O pins for JTAG mode:
00173  - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
00174  - TDO to input mode.
00175 */
00176 __STATIC_INLINE void PORT_JTAG_SETUP (void)
00177 {
00178 }
00179 
00180 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
00181 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
00182  - SWCLK, SWDIO, nRESET to output mode and set to default high level.
00183  - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
00184 */
00185 __STATIC_INLINE void PORT_SWD_SETUP (void)
00186 {
00187     uint32_t out_mode;
00188 
00189     // Ensure that the GPIO clock is enabled
00190     if (MXC_CLKMAN->sys_clk_ctrl_6_gpio == MXC_V_CLKMAN_CLK_SCALE_DISABLED) {
00191         MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_V_CLKMAN_CLK_SCALE_DIV_1;
00192     }
00193 
00194     // Initial state
00195     MXC_GPIO->out_val[swclk_port] |= (1 << swclk_pin);
00196     MXC_GPIO->out_val[swdio_port] |= (1 << swdio_pin);
00197     MXC_GPIO->out_val[nreset_port] |= (1 << nreset_pin);
00198 
00199     // Output mode
00200     out_mode = MXC_GPIO->out_mode[swclk_port];
00201     out_mode &= ~(0xFU << (4 * swclk_pin));
00202     out_mode |= (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * swclk_pin));
00203     MXC_GPIO->out_mode[swclk_port] = out_mode;
00204 
00205     out_mode = MXC_GPIO->out_mode[swdio_port];
00206     out_mode &= ~(0xFU << (4 * swdio_pin));
00207     out_mode |= (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * swdio_pin));
00208     MXC_GPIO->out_mode[swdio_port] = out_mode;
00209 
00210     out_mode = MXC_GPIO->out_mode[nreset_port];
00211     out_mode &= ~(0xFU << (4 * nreset_pin));
00212     out_mode |= (MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << (4 * nreset_pin));
00213     MXC_GPIO->out_mode[nreset_port] = out_mode;
00214 
00215     tck_in = (volatile uint32_t *)BITBAND(&MXC_GPIO->in_val[swclk_port], swclk_pin);
00216     tck_out = (volatile uint32_t *)BITBAND(&MXC_GPIO->out_val[swclk_port], swclk_pin);
00217     tms_in = (volatile uint32_t *)BITBAND(&MXC_GPIO->in_val[swdio_port], swdio_pin);
00218     tms_out = (volatile uint32_t *)BITBAND(&MXC_GPIO->out_val[swdio_port], swdio_pin);
00219     rst_in = (volatile uint32_t *)BITBAND(&MXC_GPIO->in_val[nreset_port], nreset_pin);
00220     rst_out = (volatile uint32_t *)BITBAND(&MXC_GPIO->out_val[nreset_port], nreset_pin);
00221 }
00222 
00223 /** Disable JTAG/SWD I/O Pins.
00224 Disables the DAP Hardware I/O pins which configures:
00225  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
00226 */
00227 __STATIC_INLINE void PORT_OFF (void)
00228 {
00229     uint32_t out_mode;
00230 
00231     // Disable weak pullup in high-z output mode
00232     MXC_GPIO->out_val[swclk_port] &= ~(1 << swclk_pin);
00233     MXC_GPIO->out_val[swdio_port] &= ~(1 << swdio_pin);
00234     MXC_GPIO->out_val[nreset_port] &= ~(1 << nreset_pin);
00235 
00236     // High-z output mode
00237     out_mode = MXC_GPIO->out_mode[swclk_port];
00238     out_mode &= ~(0xFU << (4 * swclk_pin));
00239     out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * swclk_pin));
00240     MXC_GPIO->out_mode[swclk_port] = out_mode;
00241 
00242     out_mode = MXC_GPIO->out_mode[swdio_port];
00243     out_mode &= ~(0xFU << (4 * swdio_pin));
00244     out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * swdio_pin));
00245     MXC_GPIO->out_mode[swdio_port] = out_mode;
00246 
00247     out_mode = MXC_GPIO->out_mode[nreset_port];
00248     out_mode &= ~(0xFU << (4 * nreset_pin));
00249     out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * nreset_pin));
00250     MXC_GPIO->out_mode[nreset_port] = out_mode;
00251 }
00252 
00253 // SWCLK/TCK I/O pin -------------------------------------
00254 
00255 /** SWCLK/TCK I/O pin: Get Input.
00256 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
00257 */
00258 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN  (void)
00259 {
00260     return *tck_in;
00261 }
00262 
00263 /** SWCLK/TCK I/O pin: Set Output to High.
00264 Set the SWCLK/TCK DAP hardware I/O pin to high level.
00265 */
00266 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_SET (void)
00267 {
00268     *tck_out = 1;
00269 }
00270 
00271 /** SWCLK/TCK I/O pin: Set Output to Low.
00272 Set the SWCLK/TCK DAP hardware I/O pin to low level.
00273 */
00274 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR (void)
00275 {
00276     *tck_out = 0;
00277 }
00278 
00279 // SWDIO/TMS Pin I/O --------------------------------------
00280 
00281 /** SWDIO/TMS I/O pin: Get Input.
00282 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
00283 */
00284 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN  (void)
00285 {
00286     return *tms_in;
00287 }
00288 
00289 /** SWDIO/TMS I/O pin: Set Output to High.
00290 Set the SWDIO/TMS DAP hardware I/O pin to high level.
00291 */
00292 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_SET (void)
00293 {
00294     *tms_out = 1;
00295 }
00296 
00297 /** SWDIO/TMS I/O pin: Set Output to Low.
00298 Set the SWDIO/TMS DAP hardware I/O pin to low level.
00299 */
00300 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_CLR (void)
00301 {
00302     *tms_out = 0;
00303 }
00304 
00305 /** SWDIO I/O pin: Get Input (used in SWD mode only).
00306 \return Current status of the SWDIO DAP hardware I/O pin.
00307 */
00308 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN  (void)
00309 {
00310     return *tms_in;
00311 }
00312 
00313 /** SWDIO I/O pin: Set Output (used in SWD mode only).
00314 \param bit Output value for the SWDIO DAP hardware I/O pin.
00315 */
00316 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT     (uint32_t bit)
00317 {
00318     *tms_out = bit & 1;
00319 }
00320 
00321 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
00322 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
00323 called prior \ref PIN_SWDIO_OUT function calls.
00324 */
00325 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_ENABLE  (void)
00326 {
00327     uint32_t out_mode;
00328 
00329     out_mode = MXC_GPIO->out_mode[swdio_port];
00330     out_mode &= ~(0xFU << (4 * swdio_pin));
00331     out_mode |= (MXC_V_GPIO_OUT_MODE_NORMAL << (4 * swdio_pin));
00332     MXC_GPIO->out_mode[swdio_port] = out_mode;
00333 }
00334 
00335 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
00336 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
00337 called prior \ref PIN_SWDIO_IN function calls.
00338 */
00339 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE (void)
00340 {
00341     uint32_t out_mode;
00342 
00343     out_mode = MXC_GPIO->out_mode[swdio_port];
00344     out_mode &= ~(0xFU << (4 * swdio_pin));
00345     MXC_GPIO->out_mode[swdio_port] = out_mode;
00346     MXC_GPIO->out_val[swdio_port] &= ~(1 << swdio_pin);
00347 }
00348 
00349 // TDI Pin I/O ---------------------------------------------
00350 
00351 /** TDI I/O pin: Get Input.
00352 \return Current status of the TDI DAP hardware I/O pin.
00353 */
00354 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN  (void)
00355 {
00356     return 0;
00357 }
00358 
00359 /** TDI I/O pin: Set Output.
00360 \param bit Output value for the TDI DAP hardware I/O pin.
00361 */
00362 __STATIC_FORCEINLINE void     PIN_TDI_OUT (uint32_t bit)
00363 {
00364 }
00365 
00366 // TDO Pin I/O ---------------------------------------------
00367 
00368 /** TDO I/O pin: Get Input.
00369 \return Current status of the TDO DAP hardware I/O pin.
00370 */
00371 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN  (void)
00372 {
00373     return 0;
00374 }
00375 
00376 // nTRST Pin I/O -------------------------------------------
00377 
00378 /** nTRST I/O pin: Get Input.
00379 \return Current status of the nTRST DAP hardware I/O pin.
00380 */
00381 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN   (void)
00382 {
00383     return 0;
00384 }
00385 
00386 /** nTRST I/O pin: Set Output.
00387 \param bit JTAG TRST Test Reset pin status:
00388            - 0: issue a JTAG TRST Test Reset.
00389            - 1: release JTAG TRST Test Reset.
00390 */
00391 __STATIC_FORCEINLINE void     PIN_nTRST_OUT  (uint32_t bit)
00392 {
00393 }
00394 
00395 // nRESET Pin I/O------------------------------------------
00396 
00397 /** nRESET I/O pin: Get Input.
00398 \return Current status of the nRESET DAP hardware I/O pin.
00399 */
00400 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN  (void)
00401 {
00402     return *rst_in;
00403 }
00404 
00405 /** nRESET I/O pin: Set Output.
00406 \param bit target device hardware reset pin status:
00407            - 0: issue a device hardware reset.
00408            - 1: release device hardware reset.
00409 */
00410 __STATIC_FORCEINLINE void     PIN_nRESET_OUT (uint32_t bit)
00411 {
00412     *rst_out = bit & 1;
00413 }
00414 
00415 ///@}
00416 
00417 
00418 //**************************************************************************************************
00419 /**
00420 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
00421 \ingroup DAP_ConfigIO_gr
00422 @{
00423 
00424 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
00425 
00426 It is recommended to provide the following LEDs for status indication:
00427  - Connect LED: is active when the DAP hardware is connected to a debugger.
00428  - Running LED: is active when the debugger has put the target device into running state.
00429 */
00430 
00431 /** Debug Unit: Set status of Connected LED.
00432 \param bit status of the Connect LED.
00433            - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
00434            - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
00435 */
00436 __STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit)
00437 {
00438 }
00439 
00440 /** Debug Unit: Set status Target Running LED.
00441 \param bit status of the Target Running LED.
00442            - 1: Target Running LED ON: program execution in target started.
00443            - 0: Target Running LED OFF: program execution in target stopped.
00444 */
00445 __STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit)
00446 {
00447 }
00448 
00449 ///@}
00450 
00451 //**************************************************************************************************
00452 /**
00453 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
00454 \ingroup DAP_ConfigIO_gr
00455 @{
00456 Access function for Test Domain Timer.
00457 
00458 The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
00459 default, the DWT timer is used.  The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
00460 
00461 */
00462 
00463 /** Get timestamp of Test Domain Timer.
00464 \return Current timestamp value.
00465 */
00466 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
00467   return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
00468 }
00469 
00470 ///@}
00471 
00472 
00473 //**************************************************************************************************
00474 /**
00475 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
00476 \ingroup DAP_ConfigIO_gr
00477 @{
00478 
00479 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
00480 */
00481 
00482 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
00483 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
00484 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
00485  - I/O clock system enabled.
00486  - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
00487  - for nTRST, nRESET a weak pull-up (if available) is enabled.
00488  - LED output pins are enabled and LEDs are turned off.
00489 */
00490 __STATIC_INLINE void DAP_SETUP (void)
00491 {
00492     uint32_t out_mode;
00493 
00494     // Weak pull-up disabled
00495     MXC_GPIO->out_val[swclk_port] &= ~(1 << swclk_pin);
00496     MXC_GPIO->out_val[swdio_port] &= ~(1 << swdio_pin);
00497     // Weak pull-up enabled
00498     MXC_GPIO->out_val[nreset_port] |= (1 << nreset_pin);
00499 
00500     // High-Z output mode
00501     out_mode = MXC_GPIO->out_mode[swclk_port];
00502     out_mode &= ~(0xFU << (4 * swclk_pin));
00503     out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * swclk_pin));
00504     MXC_GPIO->out_mode[swclk_port] = out_mode;
00505 
00506     out_mode = MXC_GPIO->out_mode[swdio_port];
00507     out_mode &= ~(0xFU << (4 * swdio_pin));
00508     out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * swdio_pin));
00509     MXC_GPIO->out_mode[swdio_port] = out_mode;
00510 
00511     out_mode = MXC_GPIO->out_mode[nreset_port];
00512     out_mode &= ~(0xFU << (4 * nreset_pin));
00513     out_mode |= (MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << (4 * nreset_pin));
00514     MXC_GPIO->out_mode[nreset_port] = out_mode;
00515 }
00516 
00517 /** Reset Target Device with custom specific I/O pin or command sequence.
00518 This function allows the optional implementation of a device specific reset sequence.
00519 It is called when the command \ref DAP_ResetTarget and is for example required
00520 when a device needs a time-critical unlock sequence that enables the debug port.
00521 \return 0 = no device specific reset sequence is implemented.\n
00522         1 = a device specific reset sequence is implemented.
00523 */
00524 __STATIC_INLINE uint32_t RESET_TARGET (void)
00525 {
00526     return (0);              // change to '1' when a device reset sequence is implemented
00527 }
00528 
00529 ///@}
00530 
00531 #endif /* __DAP_CONFIG_H__ */