DAP_config.h

00001 #ifndef __DAP_CONFIG_H__
00002 #define __DAP_CONFIG_H__
00003 
00004 //**************************************************************************************************
00005 /**
00006 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
00007 \ingroup DAP_ConfigIO_gr
00008 @{
00009 Provides definitions about:
00010  - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
00011  - Debug Unit communication packet size.
00012  - Debug Access Port communication mode (JTAG or SWD).
00013  - Optional information about a connected Target Device (for Evaluation Boards).
00014 */
00015 
00016 #include <stdio.h>
00017 #include "max32620.h"   // Debug Unit Cortex-M Processor Header File
00018 #include "clkman_regs.h"
00019 #include "gpio_regs.h"
00020 #include "IO_Config.h"
00021 
00022 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
00023 /// This value is used to calculate the SWD/JTAG clock speed.
00024 #define CPU_CLOCK               SystemCoreClock        ///< Specifies the CPU Clock in Hz
00025 
00026 /// Number of processor cycles for I/O Port write operations.
00027 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
00028 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
00029 /// requrie 2 processor cycles for a I/O Port Write operation.  If the Debug Unit uses
00030 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
00031 /// required.
00032 #define IO_PORT_WRITE_CYCLES    2               ///< I/O Cycles
00033 
00034 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
00035 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00036 #define DAP_SWD                 1               ///< SWD Mode:  1 = available, 0 = not available
00037 
00038 /// Indicate that JTAG communication mode is available at the Debug Port.
00039 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00040 #define DAP_JTAG                0               ///< JTAG Mode: 1 = available
00041 
00042 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
00043 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
00044 #define DAP_JTAG_DEV_CNT        8               ///< Maximum number of JTAG devices on scan chain
00045 
00046 /// Default communication mode on the Debug Access Port.
00047 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
00048 #define DAP_DEFAULT_PORT        1               ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
00049 
00050 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
00051 /// Used to initialize the default SWD/JTAG clock frequency.
00052 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
00053 #define DAP_DEFAULT_SWJ_CLOCK   3000000         ///< Default SWD/JTAG clock frequency in Hz.
00054 
00055 /// Maximum Package Size for Command and Response data.
00056 /// This configuration settings is used to optimized the communication performance with the
00057 /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
00058 #define DAP_PACKET_SIZE         64              ///< USB: 64 = Full-Speed, 1024 = High-Speed.
00059 
00060 /// Maximum Package Buffers for Command and Response data.
00061 /// This configuration settings is used to optimized the communication performance with the
00062 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
00063 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
00064 #define DAP_PACKET_COUNT        1              ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
00065 
00066 /// Indicate that UART Serial Wire Output (SWO) trace is available.
00067 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00068 #define SWO_UART                0               ///< SWO UART:  1 = available, 0 = not available
00069 
00070 /// Maximum SWO UART Baudrate
00071 #define SWO_UART_MAX_BAUDRATE   10000000U       ///< SWO UART Maximum Baudrate in Hz
00072 
00073 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
00074 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00075 #define SWO_MANCHESTER          0               ///< SWO Manchester:  1 = available, 0 = not available
00076 
00077 /// SWO Trace Buffer Size.
00078 #define SWO_BUFFER_SIZE         4096U           ///< SWO Trace Buffer Size in bytes (must be 2^n)
00079 
00080 /// SWO Streaming Trace.
00081 #define SWO_STREAM              0               ///< SWO Streaming Trace: 1 = available, 0 = not available.
00082 
00083 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
00084 #define TIMESTAMP_CLOCK         1000000U      ///< Timestamp clock in Hz (0 = timestamps not supported).
00085 
00086 /// Debug Unit is connected to fixed Target Device.
00087 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
00088 /// known device.  In this case a Device Vendor and Device Name string is stored which
00089 /// may be used by the debugger or IDE to configure device parameters.
00090 #define TARGET_DEVICE_FIXED     0               ///< Target Device: 1 = known, 0 = unknown;
00091 
00092 #if TARGET_DEVICE_FIXED
00093 #define TARGET_DEVICE_VENDOR    ""              ///< String indicating the Silicon Vendor
00094 #define TARGET_DEVICE_NAME      ""              ///< String indicating the Target Device
00095 #endif
00096 
00097 ///@}
00098 
00099 //**************************************************************************************************
00100 /**
00101 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
00102 \ingroup DAP_ConfigIO_gr
00103 @{
00104 
00105 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
00106 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
00107 interface of a device. The following I/O Pins are provided:
00108 
00109 JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mode
00110 ---------------------------- | -------------------- | ---------------------------------------------
00111 TCK: Test Clock              | SWCLK: Clock         | Output Push/Pull
00112 TMS: Test Mode Select        | SWDIO: Data I/O      | Output Push/Pull; Input (for receiving data)
00113 TDI: Test Data Input         |                      | Output Push/Pull
00114 TDO: Test Data Output        |                      | Input
00115 nTRST: Test Reset (optional) |                      | Output Open Drain with pull-up resistor
00116 nRESET: Device Reset         | nRESET: Device Reset | Output Open Drain with pull-up resistor
00117 
00118 
00119 DAP Hardware I/O Pin Access Functions
00120 -------------------------------------
00121 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
00122 these I/O Pins.
00123 
00124 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
00125 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
00126 peripherals that can independently write/read a single I/O pin without affecting any other pins
00127 of the same I/O port. The following SWDIO I/O Pin functions are provided:
00128  - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
00129  - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
00130  - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
00131  - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
00132 */
00133 
00134 
00135 // Configure DAP I/O pins ------------------------------
00136 
00137 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
00138 Configures the DAP Hardware I/O pins for JTAG mode:
00139  - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
00140  - TDO to input mode.
00141 */
00142 __STATIC_INLINE void PORT_JTAG_SETUP (void) {
00143 
00144   uint32_t out_mode;
00145 
00146   /* Ensure that the GPIO clock is enabled */
00147   if (MXC_CLKMAN->sys_clk_ctrl_6_gpio == MXC_V_CLKMAN_CLK_SCALE_DISABLED) {
00148       MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_V_CLKMAN_CLK_SCALE_DIV_1;
00149   }
00150 
00151   // Setup the JTAG/SWD pins
00152   MXC_GPIO->out_val[TRGT_PORT] = 0xFF;  // set all pins high
00153 
00154   out_mode = MXC_GPIO->out_mode[TRGT_PORT];
00155   out_mode &= ~(0xF << (4 * SRST_PIN));
00156   out_mode &= ~(0xF << (4 * RSTN_PIN));
00157   out_mode &= ~(0xF << (4 * TDI_PIN));
00158   out_mode &= ~(0xF << (4 * TCK_PIN));
00159   out_mode &= ~(0xF << (4 * TMS_PIN));
00160   out_mode &= ~(0xF << (4 * TDO_PIN));
00161 
00162   out_mode |= (MXC_E_GPIO_OUT_MODE_OPEN_DRAIN_W_PULLUP << (4 * RSTN_PIN));
00163   out_mode |= (MXC_E_GPIO_OUT_MODE_OPEN_DRAIN_W_PULLUP << (4 * SRST_PIN));
00164   out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * TCK_PIN));
00165   out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * TMS_PIN));
00166   out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * TDI_PIN));
00167   MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
00168 
00169   // Setup the BUFFEN pin
00170   MXC_GPIO->out_val[BUFFEN_PORT] = 0xFF;  // set all pins high
00171 
00172   out_mode = MXC_GPIO->out_mode[BUFFEN_PORT];
00173   out_mode &= ~(0xF << (4 * BUFFEN_PIN));
00174 
00175   out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * BUFFEN_PIN));
00176   MXC_GPIO->out_mode[BUFFEN_PIN] = out_mode;
00177 
00178 }
00179 
00180 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
00181 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
00182  - SWCLK, SWDIO, nRESET to output mode and set to default high level.
00183  - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
00184 */
00185 __STATIC_INLINE void PORT_SWD_SETUP (void) {
00186 
00187   uint32_t out_mode;
00188 
00189   /* Ensure that the GPIO clock is enabled */
00190   if (MXC_CLKMAN->sys_clk_ctrl_6_gpio == MXC_V_CLKMAN_CLK_SCALE_DISABLED) {
00191       MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_V_CLKMAN_CLK_SCALE_DIV_1;
00192   }
00193 
00194   // Setup the JTAG/SWD pins
00195   MXC_GPIO->out_val[TRGT_PORT] = 0xFF;  // set all pins high
00196 
00197   out_mode = MXC_GPIO->out_mode[TRGT_PORT];
00198   out_mode &= ~(0xF << (4 * SRST_PIN));
00199   out_mode &= ~(0xF << (4 * SWCLK_PIN));
00200   out_mode &= ~(0xF << (4 * SWDIO_PIN));
00201 
00202   out_mode |= (MXC_E_GPIO_OUT_MODE_OPEN_DRAIN_W_PULLUP << (4 * SRST_PIN));
00203   out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * SWCLK_PIN));
00204   out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * SWDIO_PIN));
00205   MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
00206 
00207   // Setup the BUFFEN pin
00208   MXC_GPIO->out_val[BUFFEN_PORT] = 0xFF;  // set all pins high
00209 
00210   out_mode = MXC_GPIO->out_mode[BUFFEN_PORT];
00211   out_mode &= ~(0xF << (4 * BUFFEN_PIN));
00212 
00213   out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * BUFFEN_PIN));
00214   MXC_GPIO->out_mode[BUFFEN_PORT] = out_mode;
00215 }
00216 
00217 /** Disable JTAG/SWD I/O Pins.
00218 Disables the DAP Hardware I/O pins which configures:
00219  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
00220 */
00221 __STATIC_INLINE void PORT_OFF (void) {
00222 
00223   uint32_t out_mode;
00224   out_mode = MXC_GPIO->out_mode[TRGT_PORT];
00225   out_mode &= ~(0xF << (4 * SRST_PIN));
00226   out_mode &= ~(0xF << (4 * RSTN_PIN));
00227   out_mode &= ~(0xF << (4 * TDI_PIN));
00228   out_mode &= ~(0xF << (4 * TCK_PIN));
00229   out_mode &= ~(0xF << (4 * TMS_PIN));
00230   out_mode &= ~(0xF << (4 * TDO_PIN));
00231 
00232   out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * SRST_PIN));
00233   out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * RSTN_PIN));
00234   out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TDI_PIN));
00235   out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TCK_PIN));
00236   out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TMS_PIN));
00237   out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TDO_PIN));
00238 
00239   MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
00240 }
00241 
00242 
00243 // SWCLK/TCK I/O pin -------------------------------------
00244 
00245 /** SWCLK/TCK I/O pin: Get Input.
00246 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
00247 */
00248 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN  (void) {
00249     return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], TCK_PIN);
00250 }
00251 
00252 /** SWCLK/TCK I/O pin: Set Output to High.
00253 Set the SWCLK/TCK DAP hardware I/O pin to high level.
00254 */
00255 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_SET (void) {
00256   MXC_SETBIT(&MXC_GPIO->out_val[TRGT_PORT], TCK_PIN);
00257 }
00258 
00259 /** SWCLK/TCK I/O pin: Set Output to Low.
00260 Set the SWCLK/TCK DAP hardware I/O pin to low level.
00261 */
00262 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR (void) {
00263   MXC_CLRBIT(&MXC_GPIO->out_val[TRGT_PORT], TCK_PIN);
00264 }
00265 
00266 
00267 // SWDIO/TMS Pin I/O --------------------------------------
00268 
00269 /** SWDIO/TMS I/O pin: Get Input.
00270 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
00271 */
00272 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN  (void) {
00273   return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], TMS_PIN);
00274 }
00275 
00276 /** SWDIO/TMS I/O pin: Set Output to High.
00277 Set the SWDIO/TMS DAP hardware I/O pin to high level.
00278 */
00279 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_SET (void) {
00280   MXC_SETBIT(&MXC_GPIO->out_val[TRGT_PORT], TMS_PIN);
00281 }
00282 
00283 /** SWDIO/TMS I/O pin: Set Output to Low.
00284 Set the SWDIO/TMS DAP hardware I/O pin to low level.
00285 */
00286 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_CLR (void) {
00287   MXC_CLRBIT(&MXC_GPIO->out_val[TRGT_PORT], TMS_PIN);
00288 }
00289 
00290 /** SWDIO I/O pin: Get Input (used in SWD mode only).
00291 \return Current status of the SWDIO DAP hardware I/O pin.
00292 */
00293 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN      (void) {
00294  return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], SWDIO_PIN);
00295 }
00296 
00297 /** SWDIO I/O pin: Set Output (used in SWD mode only).
00298 \param bit Output value for the SWDIO DAP hardware I/O pin.
00299 */
00300 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT     (uint32_t bit){
00301   if (bit & 1) {
00302     MXC_SETBIT(&MXC_GPIO->out_val[TRGT_PORT], SWDIO_PIN);
00303   } else {
00304     MXC_CLRBIT(&MXC_GPIO->out_val[TRGT_PORT], SWDIO_PIN);
00305   }
00306 }
00307 
00308 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
00309 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
00310 called prior \ref PIN_SWDIO_OUT function calls.
00311 */
00312 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_ENABLE  (void) {
00313   uint32_t out_mode;
00314 
00315   out_mode = MXC_GPIO->out_mode[TRGT_PORT];
00316   out_mode &= ~(0xF << (4 * SWDIO_PIN));
00317   out_mode |= (MXC_E_GPIO_OUT_MODE_NORMAL << (4 * SWDIO_PIN));
00318 
00319   MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
00320 }
00321 
00322 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
00323 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
00324 called prior \ref PIN_SWDIO_IN function calls.
00325 */
00326 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE (void) {
00327   uint32_t out_mode;
00328 
00329   out_mode = MXC_GPIO->out_mode[TRGT_PORT];
00330   out_mode &= ~(0xF << (4 * SWDIO_PIN));
00331 
00332   MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
00333 }
00334 
00335 
00336 // TDI Pin I/O ---------------------------------------------
00337 
00338 /** TDI I/O pin: Get Input.
00339 \return Current status of the TDI DAP hardware I/O pin.
00340 */
00341 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN  (void) {
00342     return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], TDI_PIN);
00343 }
00344 
00345 /** TDI I/O pin: Set Output.
00346 \param bit Output value for the TDI DAP hardware I/O pin.
00347 */
00348 __STATIC_FORCEINLINE void     PIN_TDI_OUT (uint32_t bit) {
00349   if (bit & 1) {
00350     MXC_SETBIT(&MXC_GPIO->out_val[TRGT_PORT], TDI_PIN);
00351   } else {
00352     MXC_CLRBIT(&MXC_GPIO->out_val[TRGT_PORT], TDI_PIN);
00353   }
00354 }
00355 
00356 
00357 // TDO Pin I/O ---------------------------------------------
00358 
00359 /** TDO I/O pin: Get Input.
00360 \return Current status of the TDO DAP hardware I/O pin.
00361 */
00362 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN  (void) {
00363     return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], TDO_PIN);
00364 }
00365 
00366 
00367 // nTRST Pin I/O -------------------------------------------
00368 
00369 /** nTRST I/O pin: Get Input.
00370 \return Current status of the nTRST DAP hardware I/O pin.
00371 */
00372 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN   (void) {
00373     return 0;
00374 }
00375 
00376 /** nTRST I/O pin: Set Output.
00377 \param bit JTAG TRST Test Reset pin status:
00378            - 0: issue a JTAG TRST Test Reset.
00379            - 1: release JTAG TRST Test Reset.
00380 */
00381 __STATIC_FORCEINLINE void     PIN_nTRST_OUT  (uint32_t bit) {
00382 }
00383 
00384 // nRESET Pin I/O------------------------------------------
00385 
00386 /** nRESET I/O pin: Get Input.
00387 \return Current status of the nRESET DAP hardware I/O pin.
00388 */
00389 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN  (void) {
00390     return MXC_GETBIT(&MXC_GPIO->in_val[TRGT_PORT], SRST_PIN);
00391 }
00392 
00393 /** nRESET I/O pin: Set Output.
00394 \param bit target device hardware reset pin status:
00395            - 0: issue a device hardware reset.
00396            - 1: release device hardware reset.
00397 */
00398 __STATIC_FORCEINLINE void     PIN_nRESET_OUT (uint32_t bit) {
00399   if (bit) {
00400     MXC_SETBIT(&MXC_GPIO->out_val[TRGT_PORT], SRST_PIN);
00401   } else {
00402     MXC_CLRBIT(&MXC_GPIO->out_val[TRGT_PORT], SRST_PIN);
00403   }
00404 }
00405 
00406 ///@}
00407 
00408 
00409 //**************************************************************************************************
00410 /**
00411 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
00412 \ingroup DAP_ConfigIO_gr
00413 @{
00414 
00415 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
00416 
00417 It is recommended to provide the following LEDs for status indication:
00418  - Connect LED: is active when the DAP hardware is connected to a debugger.
00419  - Running LED: is active when the debugger has put the target device into running state.
00420 */
00421 
00422 /** Debug Unit: Set status of Connected LED.
00423 \param bit status of the Connect LED.
00424            - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
00425            - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
00426 */
00427 __STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {
00428 }
00429 
00430 /** Debug Unit: Set status Target Running LED.
00431 \param bit status of the Target Running LED.
00432            - 1: Target Running LED ON: program execution in target started.
00433            - 0: Target Running LED OFF: program execution in target stopped.
00434 */
00435 __STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {
00436 }
00437 
00438 ///@}
00439 
00440 
00441 //**************************************************************************************************
00442 /**
00443 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
00444 \ingroup DAP_ConfigIO_gr
00445 @{
00446 Access function for Test Domain Timer.
00447 
00448 The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
00449 default, the DWT timer is used.  The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
00450 
00451 */
00452 
00453 /** Get timestamp of Test Domain Timer.
00454 \return Current timestamp value.
00455 */
00456 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
00457   return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
00458 }
00459 
00460 ///@}
00461 
00462 
00463 //**************************************************************************************************
00464 /**
00465 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
00466 \ingroup DAP_ConfigIO_gr
00467 @{
00468 
00469 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
00470 */
00471 
00472 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
00473 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
00474 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
00475  - I/O clock system enabled.
00476  - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
00477  - for nTRST, nRESET a weak pull-up (if available) is enabled.
00478  - LED output pins are enabled and LEDs are turned off.
00479 */
00480 __STATIC_INLINE void DAP_SETUP (void) {
00481   uint32_t out_mode;
00482   out_mode = MXC_GPIO->out_mode[TRGT_PORT];
00483   out_mode &= ~(0xF << (4 * SRST_PIN));
00484   out_mode &= ~(0xF << (4 * RSTN_PIN));
00485   out_mode &= ~(0xF << (4 * TDI_PIN));
00486   out_mode &= ~(0xF << (4 * TCK_PIN));
00487   out_mode &= ~(0xF << (4 * TMS_PIN));
00488   out_mode &= ~(0xF << (4 * TDO_PIN));
00489 
00490   out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * SRST_PIN));
00491   out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * RSTN_PIN));
00492   out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TDI_PIN));
00493   out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TCK_PIN));
00494   out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TMS_PIN));
00495   out_mode |= (MXC_E_GPIO_OUT_MODE_TRISTATE << (4 * TDO_PIN));
00496 
00497   MXC_GPIO->out_mode[TRGT_PORT] = out_mode;
00498 }
00499 
00500 /** Reset Target Device with custom specific I/O pin or command sequence.
00501 This function allows the optional implementation of a device specific reset sequence.
00502 It is called when the command \ref DAP_ResetTarget and is for example required
00503 when a device needs a time-critical unlock sequence that enables the debug port.
00504 \return 0 = no device specific reset sequence is implemented.\n
00505         1 = a device specific reset sequence is implemented.
00506 */
00507 __STATIC_INLINE uint32_t RESET_TARGET (void) {
00508   return (0);              // change to '1' when a device reset sequence is implemented
00509 }
00510 
00511 ///@}
00512 
00513 
00514 #endif /* __DAP_CONFIG_H__ */