max32625.h

00001 /*******************************************************************************
00002  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
00003  *
00004  * Permission is hereby granted, free of charge, to any person obtaining a
00005  * copy of this software and associated documentation files (the "Software"),
00006  * to deal in the Software without restriction, including without limitation
00007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
00008  * and/or sell copies of the Software, and to permit persons to whom the
00009  * Software is furnished to do so, subject to the following conditions:
00010  *
00011  * The above copyright notice and this permission notice shall be included
00012  * in all copies or substantial portions of the Software.
00013  *
00014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00016  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
00017  * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
00018  * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
00019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
00020  * OTHER DEALINGS IN THE SOFTWARE.
00021  *
00022  * Except as contained in this notice, the name of Maxim Integrated
00023  * Products, Inc. shall not be used except as stated in the Maxim Integrated
00024  * Products, Inc. Branding Policy.
00025  *
00026  * The mere transfer of this software does not imply any licenses
00027  * of trade secrets, proprietary technology, copyrights, patents,
00028  * trademarks, maskwork rights, or any other form of intellectual
00029  * property whatsoever. Maxim Integrated Products, Inc. retains all
00030  * ownership rights.
00031  *
00032  ******************************************************************************/
00033 
00034 #ifndef _MAX32625_H_
00035 #define _MAX32625_H_
00036 
00037 #include <stdint.h>
00038 
00039 #ifndef  FALSE
00040 #define  FALSE      (0)
00041 #endif
00042 
00043 #ifndef  TRUE
00044 #define  TRUE       (1)
00045 #endif
00046 
00047 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
00048 #if defined ( __GNUC__ )
00049 #define __weak __attribute__((weak))
00050 
00051 #elif defined ( __CC_ARM)
00052 
00053 #define inline __inline
00054 #pragma anon_unions
00055 
00056 #endif
00057 
00058 typedef enum {
00059     NonMaskableInt_IRQn    = -14,
00060     HardFault_IRQn         = -13,
00061     MemoryManagement_IRQn  = -12,
00062     BusFault_IRQn          = -11,
00063     UsageFault_IRQn        = -10,
00064     SVCall_IRQn            = -5,
00065     DebugMonitor_IRQn      = -4,
00066     PendSV_IRQn            = -2,
00067     SysTick_IRQn           = -1,
00068 
00069     /* Device-specific interrupt sources (external to ARM core)                  */
00070     /*                         table entry number                                */
00071     /*                         ||||                                              */
00072     /*                         ||||  table offset address                        */
00073     /*                         vvvv  vvvvvv                                      */
00074 
00075     CLKMAN_IRQn      = 0,   /* 0x10 0x0040,CLKMAN                                */
00076     PWRMAN_IRQn      = 1,   /* 0x11 0x0044 PWRMAN                                */
00077     FLC_IRQn         = 2,   /* 0x12 0x0048 Flash Controller                      */
00078     RTC0_IRQn        = 3,   /* 0x13 0x004C RTC Counter match with Compare 0      */
00079     RTC1_IRQn        = 4,   /* 0x14 0x0050 RTC Counter match with Compare 1      */
00080     RTC2_IRQn        = 5,   /* 0x15 0x0054 RTC Prescaler interval compare match  */
00081     RTC3_IRQn        = 6,   /* 0x16 0x0058 RTC Overflow                          */
00082     PMU_IRQn         = 7,   /* 0x17 0x005C Peripheral Management Unit (PMU/DMA)  */
00083     USB_IRQn          = 8,   /* 0x18 0x0060 USB                                   */
00084     AES_IRQn         = 9,   /* 0x19 0x0064 AES                                   */
00085     MAA_IRQn         = 10,  /* 0x1A 0x0068 MAA                                   */
00086     WDT0_IRQn        = 11,  /* 0x1B 0x006C Watchdog 0 timeout                    */
00087     WDT0_P_IRQn      = 12,  /* 0x1C 0x0070 Watchdog 0 pre-window (fed too early) */
00088     WDT1_IRQn        = 13,  /* 0x1D 0x0074 Watchdog 1 timeout                    */
00089     WDT1_P_IRQn      = 14,  /* 0x1E 0x0078 Watchdog 1 pre-window (fed too early) */
00090     GPIO_P0_IRQn     = 15,  /* 0x1F 0x007C GPIO Port 0                           */
00091     GPIO_P1_IRQn     = 16,  /* 0x20 0x0080 GPIO Port 1                           */
00092     GPIO_P2_IRQn     = 17,  /* 0x21 0x0084 GPIO Port 2                           */
00093     GPIO_P3_IRQn     = 18,  /* 0x22 0x0088 GPIO Port 3                           */
00094     GPIO_P4_IRQn     = 19,  /* 0x23 0x008C GPIO Port 4                           */
00095     // Reserved      = 20,  /* 0x24 0x0090 Reserved                              */
00096     // Reserved      = 21,  /* 0x25 0x0094 Reserved                              */
00097     TMR0_0_IRQn      = 22,  /* 0x26 0x0098 Timer 0 (32-bit, 16-bit #0)           */
00098     TMR0_1_IRQn      = 23,  /* 0x27 0x009C Timer 0         (16-bit #1)           */
00099     TMR1_0_IRQn      = 24,  /* 0x28 0x00A0 Timer 1 (32-bit, 16-bit #0)           */
00100     TMR1_1_IRQn      = 25,  /* 0x29 0x00A4 Timer 1         (16-bit #1)           */
00101     TMR2_0_IRQn      = 26,  /* 0x2A 0x00A8 Timer 2 (32-bit, 16-bit #0)           */
00102     TMR2_1_IRQn      = 27,  /* 0x2B 0x00AC Timer 2         (16-bit #1)           */
00103     TMR3_0_IRQn      = 28,  /* 0x2C 0x00B0 Timer 3 (32-bit, 16-bit #0)           */
00104     TMR3_1_IRQn      = 29,  /* 0x2D 0x00B4 Timer 3         (16-bit #1)           */
00105     TMR4_0_IRQn      = 30,  /* 0x2E 0x00B8 Timer 4 (32-bit, 16-bit #0)           */
00106     TMR4_1_IRQn      = 31,  /* 0x2F 0x00BC Timer 4         (16-bit #1)           */
00107     TMR5_0_IRQn      = 32,  /* 0x30 0x00C0 Timer 5 (32-bit, 16-bit #0)           */
00108     TMR5_1_IRQn      = 33,  /* 0x31 0x00C4 Timer 5         (16-bit #1)           */
00109     UART0_IRQn       = 34,  /* 0x32 0x00C8 UART 0                                */
00110     UART1_IRQn       = 35,  /* 0x33 0x00CC UART 1                                */
00111     UART2_IRQn       = 36,  /* 0x34 0x00D0 UART 2                                */
00112     UART3_IRQn        = 37,  /* 0x35 0x00D4 UART 3 (Unused)                       */
00113     PT_IRQn          = 38,  /* 0x36 0x00D8 Pulse Trains                          */
00114     I2CM0_IRQn       = 39,  /* 0x37 0x00DC I2C Master 0                          */
00115     I2CM1_IRQn       = 40,  /* 0x38 0x00E0 I2C Master 1                          */
00116     I2CM2_IRQn       = 41,  /* 0x39 0x00E4 I2C Master 2 (Unused)                 */
00117     I2CS_IRQn        = 42,  /* 0x3A 0x00E8 I2C Slave                             */
00118     SPIM0_IRQn       = 43,  /* 0x3B 0x00EC SPI Master 0                          */
00119     SPIM1_IRQn       = 44,  /* 0x3C 0x00F0 SPI Master 1                          */
00120     SPIM2_IRQn       = 45,  /* 0x3D 0x00F4 SPI Master 2                          */
00121     SPIB_IRQn        = 46,  /* 0x3E 0x00F8 SPI Bridge (Unused)                   */
00122     OWM_IRQn         = 47,  /* 0x3F 0x00FC 1-Wire Master                         */
00123     AFE_IRQn         = 48,  /* 0x40 0x0100 Analog Front End, ADC                 */
00124     SPIS_IRQn        = 49,  /* 0x41 0x0104 SPI Slave                             */
00125     MXC_IRQ_EXT_COUNT,
00126 } IRQn_Type ;
00127 
00128 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
00129 
00130 
00131 /* ================================================================================ */
00132 /* ================      Processor and Core Peripheral Section     ================ */
00133 /* ================================================================================ */
00134 
00135 /* ----------------------  Configuration of the Cortex-M Processor and Core Peripherals  ---------------------- */
00136 #define __CM4_REV                 0x0100            /*!< Cortex-M4 Core Revision                                */
00137 #define __MPU_PRESENT                  1            /*!< MPU present or not                                     */
00138 #define __NVIC_PRIO_BITS               3            /*!< Number of Bits used for Priority Levels                */
00139 #define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used           */
00140 #define __FPU_PRESENT                  1            /*!< FPU present or not                                     */
00141 
00142 #include <core_cm4.h>                               /*!< Cortex-M4 processor and core peripherals               */
00143 #include "system_max32625.h"                        /*!< System Header                                          */
00144 
00145 
00146 /* ================================================================================ */
00147 /* ==================       Device Specific Memory Section       ================== */
00148 /* ================================================================================ */
00149 
00150 #define MXC_FLASH_MEM_BASE         0x00000000UL
00151 #define MXC_FLASH_PAGE_SIZE        0x00002000UL
00152 #define MXC_FLASH_FULL_MEM_SIZE    0x00080000UL
00153 #define MXC_SYS_MEM_BASE           0x20000000UL
00154 #define MXC_SRAM_FULL_MEM_SIZE     0x00028000UL
00155 #define MXC_EXT_FLASH_MEM_BASE     0x10000000UL
00156 
00157 /* ================================================================================ */
00158 /* ================       Device Specific Peripheral Section       ================ */
00159 /* ================================================================================ */
00160 
00161 
00162 /*
00163    Base addresses and configuration settings for all MAX32625 peripheral modules.
00164 */
00165 
00166 
00167 /*******************************************************************************/
00168 /*                                                     System Manager Settings */
00169 
00170 #define MXC_BASE_SYSMAN                  ((uint32_t)0x40000000UL)
00171 #define MXC_SYSMAN                       ((mxc_sysman_regs_t *)MXC_BASE_SYSMAN)
00172 
00173 
00174 
00175 /*******************************************************************************/
00176 /*                                                        System Clock Manager */
00177 
00178 #define MXC_BASE_CLKMAN                  ((uint32_t)0x40000400UL)
00179 #define MXC_CLKMAN                       ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
00180 
00181 
00182 
00183 /*******************************************************************************/
00184 /*                                                        System Power Manager */
00185 
00186 #define MXC_BASE_PWRMAN                  ((uint32_t)0x40000800UL)
00187 #define MXC_PWRMAN                       ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
00188 
00189 
00190 
00191 /*******************************************************************************/
00192 /*                                                             Real Time Clock */
00193 
00194 #define MXC_BASE_RTCTMR                  ((uint32_t)0x40000A00UL)
00195 #define MXC_RTCTMR                       ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
00196 #define MXC_BASE_RTCCFG                  ((uint32_t)0x40000A70UL)
00197 #define MXC_RTCCFG                       ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
00198 
00199 #define MXC_RTCTMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? RTC0_IRQn :    \
00200                                           (i) == 1 ? RTC1_IRQn :    \
00201                                           (i) == 2 ? RTC2_IRQn :    \
00202                                           (i) == 3 ? RTC3_IRQn : 0)
00203 
00204 
00205 
00206 /*******************************************************************************/
00207 /*                                                             Power Sequencer */
00208 
00209 #define MXC_BASE_PWRSEQ                  ((uint32_t)0x40000A30UL)
00210 #define MXC_PWRSEQ                       ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
00211 
00212 
00213 
00214 /*******************************************************************************/
00215 /*                                                          System I/O Manager */
00216 
00217 #define MXC_BASE_IOMAN                   ((uint32_t)0x40000C00UL)
00218 #define MXC_IOMAN                        ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
00219 
00220 
00221 
00222 /*******************************************************************************/
00223 /*                                                       Shadow Trim Registers */
00224 
00225 #define MXC_BASE_TRIM                    ((uint32_t)0x40001000UL)
00226 #define MXC_TRIM                         ((mxc_trim_regs_t *)MXC_BASE_TRIM)
00227 
00228 
00229 
00230 /*******************************************************************************/
00231 /*                                                            Flash Controller */
00232 
00233 #define MXC_BASE_FLC                     ((uint32_t)0x40002000UL)
00234 #define MXC_FLC                          ((mxc_flc_regs_t *)MXC_BASE_FLC)
00235 
00236 #define MXC_FLC_PAGE_SIZE_SHIFT          (13)
00237 #define MXC_FLC_PAGE_SIZE                (1 << MXC_FLC_PAGE_SIZE_SHIFT)
00238 #define MXC_FLC_PAGE_ERASE_MSK           ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
00239 
00240 
00241 
00242 /*******************************************************************************/
00243 /*                                                           Instruction Cache */
00244 
00245 #define MXC_BASE_ICC                     ((uint32_t)0x40003000UL)
00246 #define MXC_ICC                          ((mxc_icc_regs_t *)MXC_BASE_ICC)
00247 
00248 
00249 
00250 /*******************************************************************************/
00251 /*                                                           SPI XIP Interface */
00252 
00253 #define MXC_BASE_SPIX                    ((uint32_t)0x40004000UL)
00254 #define MXC_SPIX                         ((mxc_spix_regs_t *)MXC_BASE_SPIX)
00255 
00256 
00257 
00258 /*******************************************************************************/
00259 /*                                                  Peripheral Management Unit */
00260 
00261 #define MXC_CFG_PMU_CHANNELS             (6)
00262 
00263 #define MXC_BASE_PMU0                    ((uint32_t)0x40005000UL)
00264 #define MXC_PMU0                         ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
00265 #define MXC_BASE_PMU1                    ((uint32_t)0x40005020UL)
00266 #define MXC_PMU1                         ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
00267 #define MXC_BASE_PMU2                    ((uint32_t)0x40005040UL)
00268 #define MXC_PMU2                         ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
00269 #define MXC_BASE_PMU3                    ((uint32_t)0x40005060UL)
00270 #define MXC_PMU3                         ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
00271 #define MXC_BASE_PMU4                    ((uint32_t)0x40005080UL)
00272 #define MXC_PMU4                         ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
00273 #define MXC_BASE_PMU5                    ((uint32_t)0x400050A0UL)
00274 #define MXC_PMU5                         ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
00275 
00276 #define MXC_PMU_GET_BASE(i)              ((i) == 0  ? MXC_BASE_PMU0 :          \
00277                                           (i) == 1  ? MXC_BASE_PMU1 :          \
00278                                           (i) == 2  ? MXC_BASE_PMU2 :          \
00279                                           (i) == 3  ? MXC_BASE_PMU3 :          \
00280                                           (i) == 4  ? MXC_BASE_PMU4 :          \
00281                                           (i) == 5  ? MXC_BASE_PMU5 : 0)
00282 
00283 #define MXC_PMU_GET_PMU(i)               ((i) == 0 ? MXC_PMU0 :                \
00284                                           (i) == 1 ? MXC_PMU1 :                \
00285                                           (i) == 2 ? MXC_PMU2 :                \
00286                                           (i) == 3 ? MXC_PMU3 :                \
00287                                           (i) == 4 ? MXC_PMU4 :                \
00288                                           (i) == 5 ? MXC_PMU5 : 0)
00289 
00290 #define MXC_PMU_GET_IDX(p)               ((p) == MXC_PMU0 ? 0 :                \
00291                                           (p) == MXC_PMU1 ? 1 :                \
00292                                           (p) == MXC_PMU2 ? 2 :                \
00293                                           (p) == MXC_PMU3 ? 3 :                \
00294                                           (p) == MXC_PMU4 ? 4 :                \
00295                                           (p) == MXC_PMU5 ? 5 : -1)
00296 
00297 /*******************************************************************************/
00298 /*                                                       USB Device Controller */
00299 
00300 #define MXC_BASE_USB                     ((uint32_t)0x40100000UL)
00301 #define MXC_USB                          ((mxc_usb_regs_t *)MXC_BASE_USB)
00302 
00303 #define MXC_USB_MAX_PACKET               (64)
00304 #define MXC_USB_NUM_EP                   (8)
00305 
00306 
00307 
00308 /*******************************************************************************/
00309 /*                                                        CRC-16/CRC-32 Engine */
00310 
00311 #define MXC_BASE_CRC                     ((uint32_t)0x40006000UL)
00312 #define MXC_CRC                          ((mxc_crc_regs_t *)MXC_BASE_CRC)
00313 #define MXC_BASE_CRC_DATA                ((uint32_t)0x40101000UL)
00314 #define MXC_CRC_DATA                     ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
00315 
00316 /*******************************************************************************/
00317 /*                                       Pseudo-random number generator (PRNG) */
00318 
00319 #define MXC_BASE_PRNG                     ((uint32_t)0x40007000UL)
00320 #define MXC_PRNG                          ((mxc_prng_regs_t *)MXC_BASE_PRNG)
00321 
00322 /*******************************************************************************/
00323 /*                                                    AES Cryptographic Engine */
00324 
00325 #define MXC_BASE_AES                     ((uint32_t)0x40007400UL)
00326 #define MXC_AES                          ((mxc_aes_regs_t *)MXC_BASE_AES)
00327 #define MXC_BASE_AES_MEM                 ((uint32_t)0x40102000UL)
00328 #define MXC_AES_MEM                      ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
00329 
00330 /*******************************************************************************/
00331 /*                                                    MAA Cryptographic Engine */
00332 
00333 #define MXC_BASE_MAA                     ((uint32_t)0x40007800UL)
00334 #define MXC_MAA                          ((mxc_maa_regs_t *)MXC_BASE_MAA)
00335 #define MXC_BASE_MAA_MEM                 ((uint32_t)0x40102800UL)
00336 #define MXC_MAA_MEM                      ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
00337 
00338 /*******************************************************************************/
00339 /*                                                 Trust Protection Unit (TPU) */
00340 
00341 #define MXC_BASE_TPU                     ((uint32_t)0x40007000UL)
00342 #define MXC_TPU                          ((mxc_tpu_regs_t *)MXC_BASE_TPU)
00343 #define MXC_BASE_TPU_TSR                 ((uint32_t)0x40007C00UL)
00344 #define MXC_TPU_TSR                      ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
00345 
00346 /*******************************************************************************/
00347 /*                                                             Watchdog Timers */
00348 
00349 #define MXC_CFG_WDT_INSTANCES            (2)
00350 
00351 #define MXC_BASE_WDT0                    ((uint32_t)0x40008000UL)
00352 #define MXC_WDT0                         ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
00353 #define MXC_BASE_WDT1                    ((uint32_t)0x40009000UL)
00354 #define MXC_WDT1                         ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
00355 
00356 #define MXC_WDT_GET_IRQ(i)    (IRQn_Type)((i) == 0 ? WDT0_IRQn :        \
00357                                           (i) == 1 ? WDT1_IRQn : 0)
00358 
00359 #define MXC_WDT_GET_IRQ_P(i)  (IRQn_Type)((i) == 0 ? WDT0_P_IRQn :      \
00360                                           (i) == 1 ? WDT1_P_IRQn : 0)
00361 
00362 #define MXC_WDT_GET_BASE(i)              ((i) == 0 ? MXC_BASE_WDT0 :    \
00363                                           (i) == 1 ? MXC_BASE_WDT1 : 0)
00364 
00365 #define MXC_WDT_GET_WDT(i)               ((i) == 0 ? MXC_WDT0 :         \
00366                                           (i) == 1 ? MXC_WDT1 : 0)
00367 
00368 #define MXC_WDT_GET_IDX(i)               ((i) == MXC_WDT0 ? 0:          \
00369                                           (i) == MXC_WDT1 ? 1: -1)
00370 
00371 
00372 /*******************************************************************************/
00373 /*                                                    Low-Level Watchdog Timer */
00374 
00375 #define MXC_BASE_WDT2                    ((uint32_t)0x40007C60UL)
00376 #define MXC_WDT2                         ((mxc_wdt2_regs_t *)MXC_BASE_WDT2)
00377 
00378 
00379 
00380 /*******************************************************************************/
00381 /*                                            General Purpose I/O Ports (GPIO) */
00382 
00383 #define MXC_GPIO_NUM_PORTS               (5)
00384 #define MXC_GPIO_MAX_PINS_PER_PORT       (8)
00385 
00386 #define MXC_BASE_GPIO                    ((uint32_t)0x4000A000UL)
00387 #define MXC_GPIO                         ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
00388 
00389 #define MXC_GPIO_GET_IRQ(i)   (IRQn_Type)((i) == 0 ? GPIO_P0_IRQn :      \
00390                                           (i) == 1 ? GPIO_P1_IRQn :      \
00391                                           (i) == 2 ? GPIO_P2_IRQn :      \
00392                                           (i) == 3 ? GPIO_P3_IRQn :      \
00393                                           (i) == 4 ? GPIO_P4_IRQn : 0)
00394 
00395 
00396 
00397 /*******************************************************************************/
00398 /*                                                    16/32 bit Timer/Counters */
00399 
00400 #define MXC_CFG_TMR_INSTANCES            (6)
00401 
00402 #define MXC_BASE_TMR0                    ((uint32_t)0x4000B000UL)
00403 #define MXC_TMR0                         ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
00404 #define MXC_BASE_TMR1                    ((uint32_t)0x4000C000UL)
00405 #define MXC_TMR1                         ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
00406 #define MXC_BASE_TMR2                    ((uint32_t)0x4000D000UL)
00407 #define MXC_TMR2                         ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
00408 #define MXC_BASE_TMR3                    ((uint32_t)0x4000E000UL)
00409 #define MXC_TMR3                         ((mxc_tmr_regs_t *)MXC_BASE_TMR3)
00410 #define MXC_BASE_TMR4                    ((uint32_t)0x4000F000UL)
00411 #define MXC_TMR4                         ((mxc_tmr_regs_t *)MXC_BASE_TMR4)
00412 #define MXC_BASE_TMR5                    ((uint32_t)0x40010000UL)
00413 #define MXC_TMR5                         ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
00414 
00415 #define MXC_TMR_GET_IRQ_32(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn :     \
00416                                           (i) == 1 ? TMR1_0_IRQn :     \
00417                                           (i) == 2 ? TMR2_0_IRQn :     \
00418                                           (i) == 3 ? TMR3_0_IRQn :     \
00419                                           (i) == 4 ? TMR4_0_IRQn :     \
00420                                           (i) == 5 ? TMR5_0_IRQn : 0)
00421 
00422 #define MXC_TMR_GET_IRQ_16(i) (IRQn_Type)((i) == 0  ? TMR0_0_IRQn :    \
00423                                           (i) == 1  ? TMR1_0_IRQn :    \
00424                                           (i) == 2  ? TMR2_0_IRQn :    \
00425                                           (i) == 3  ? TMR3_0_IRQn :    \
00426                                           (i) == 4  ? TMR4_0_IRQn :    \
00427                                           (i) == 5  ? TMR5_0_IRQn :    \
00428                                           (i) == 6  ? TMR0_1_IRQn :    \
00429                                           (i) == 7  ? TMR1_1_IRQn :    \
00430                                           (i) == 8  ? TMR2_1_IRQn :    \
00431                                           (i) == 9  ? TMR3_1_IRQn :    \
00432                                           (i) == 10 ? TMR4_1_IRQn :    \
00433                                           (i) == 11 ? TMR5_1_IRQn : 0)
00434 
00435 #define MXC_TMR_GET_BASE(i)              ((i) == 0 ? MXC_BASE_TMR0 :   \
00436                                           (i) == 1 ? MXC_BASE_TMR1 :   \
00437                                           (i) == 2 ? MXC_BASE_TMR2 :   \
00438                                           (i) == 3 ? MXC_BASE_TMR3 :   \
00439                                           (i) == 4 ? MXC_BASE_TMR4 :   \
00440                                           (i) == 5 ? MXC_BASE_TMR5 : 0)
00441 
00442 #define MXC_TMR_GET_TMR(i)               ((i) == 0 ? MXC_TMR0 :        \
00443                                           (i) == 1 ? MXC_TMR1 :        \
00444                                           (i) == 2 ? MXC_TMR2 :        \
00445                                           (i) == 3 ? MXC_TMR3 :        \
00446                                           (i) == 4 ? MXC_TMR4 :        \
00447                                           (i) == 5 ? MXC_TMR5 : 0)
00448 
00449 #define MXC_TMR_GET_IDX(p)               ((p) == MXC_TMR0 ? 0 :        \
00450                                           (p) == MXC_TMR1 ? 1 :        \
00451                                           (p) == MXC_TMR2 ? 2 :        \
00452                                           (p) == MXC_TMR3 ? 3 :        \
00453                                           (p) == MXC_TMR4 ? 4 :        \
00454                                           (p) == MXC_TMR5 ? 5 : -1)
00455 
00456 
00457 
00458 
00459 /*******************************************************************************/
00460 /*                                                      Pulse Train Generation */
00461 
00462 #define MXC_CFG_PT_INSTANCES             (16)
00463 
00464 #define MXC_BASE_PTG                     ((uint32_t)0x40011000UL)
00465 #define MXC_PTG                          ((mxc_ptg_regs_t *)MXC_BASE_PTG)
00466 #define MXC_BASE_PT0                     ((uint32_t)0x40011020UL)
00467 #define MXC_PT0                          ((mxc_pt_regs_t *)MXC_BASE_PT0)
00468 #define MXC_BASE_PT1                     ((uint32_t)0x40011040UL)
00469 #define MXC_PT1                          ((mxc_pt_regs_t *)MXC_BASE_PT1)
00470 #define MXC_BASE_PT2                     ((uint32_t)0x40011060UL)
00471 #define MXC_PT2                          ((mxc_pt_regs_t *)MXC_BASE_PT2)
00472 #define MXC_BASE_PT3                     ((uint32_t)0x40011080UL)
00473 #define MXC_PT3                          ((mxc_pt_regs_t *)MXC_BASE_PT3)
00474 #define MXC_BASE_PT4                     ((uint32_t)0x400110A0UL)
00475 #define MXC_PT4                          ((mxc_pt_regs_t *)MXC_BASE_PT4)
00476 #define MXC_BASE_PT5                     ((uint32_t)0x400110C0UL)
00477 #define MXC_PT5                          ((mxc_pt_regs_t *)MXC_BASE_PT5)
00478 #define MXC_BASE_PT6                     ((uint32_t)0x400110E0UL)
00479 #define MXC_PT6                          ((mxc_pt_regs_t *)MXC_BASE_PT6)
00480 #define MXC_BASE_PT7                     ((uint32_t)0x40011100UL)
00481 #define MXC_PT7                          ((mxc_pt_regs_t *)MXC_BASE_PT7)
00482 #define MXC_BASE_PT8                     ((uint32_t)0x40011120UL)
00483 #define MXC_PT8                          ((mxc_pt_regs_t *)MXC_BASE_PT8)
00484 #define MXC_BASE_PT9                     ((uint32_t)0x40011140UL)
00485 #define MXC_PT9                          ((mxc_pt_regs_t *)MXC_BASE_PT9)
00486 #define MXC_BASE_PT10                    ((uint32_t)0x40011160UL)
00487 #define MXC_PT10                         ((mxc_pt_regs_t *)MXC_BASE_PT10)
00488 #define MXC_BASE_PT11                    ((uint32_t)0x40011180UL)
00489 #define MXC_PT11                         ((mxc_pt_regs_t *)MXC_BASE_PT11)
00490 #define MXC_BASE_PT12                    ((uint32_t)0x400111A0UL)
00491 #define MXC_PT12                         ((mxc_pt_regs_t *)MXC_BASE_PT12)
00492 #define MXC_BASE_PT13                    ((uint32_t)0x400111C0UL)
00493 #define MXC_PT13                         ((mxc_pt_regs_t *)MXC_BASE_PT13)
00494 #define MXC_BASE_PT14                    ((uint32_t)0x400111E0UL)
00495 #define MXC_PT14                         ((mxc_pt_regs_t *)MXC_BASE_PT14)
00496 #define MXC_BASE_PT15                    ((uint32_t)0x40011200UL)
00497 #define MXC_PT15                         ((mxc_pt_regs_t *)MXC_BASE_PT15)
00498 
00499 #define MXC_PT_GET_BASE(i)               ((i) == 0  ? MXC_BASE_PT0  :           \
00500                                           (i) == 1  ? MXC_BASE_PT1  :           \
00501                                           (i) == 2  ? MXC_BASE_PT2  :           \
00502                                           (i) == 3  ? MXC_BASE_PT3  :           \
00503                                           (i) == 4  ? MXC_BASE_PT4  :           \
00504                                           (i) == 5  ? MXC_BASE_PT5  :           \
00505                                           (i) == 6  ? MXC_BASE_PT6  :           \
00506                                           (i) == 7  ? MXC_BASE_PT7  :           \
00507                                           (i) == 8  ? MXC_BASE_PT8  :           \
00508                                           (i) == 9  ? MXC_BASE_PT9  :           \
00509                                           (i) == 10 ? MXC_BASE_PT10 :           \
00510                                           (i) == 11 ? MXC_BASE_PT11 :           \
00511                                           (i) == 12 ? MXC_BASE_PT12 :           \
00512                                           (i) == 13 ? MXC_BASE_PT13 :           \
00513                                           (i) == 14 ? MXC_BASE_PT14 :           \
00514                                           (i) == 15 ? MXC_BASE_PT15 : 0)
00515 
00516 #define MXC_PT_GET_PT(i)                 ((i) == 0  ? MXC_PT0  :                \
00517                                           (i) == 1  ? MXC_PT1  :                \
00518                                           (i) == 2  ? MXC_PT2  :                \
00519                                           (i) == 3  ? MXC_PT3  :                \
00520                                           (i) == 4  ? MXC_PT4  :                \
00521                                           (i) == 5  ? MXC_PT5  :                \
00522                                           (i) == 6  ? MXC_PT6  :                \
00523                                           (i) == 7  ? MXC_PT7  :                \
00524                                           (i) == 8  ? MXC_PT8  :                \
00525                                           (i) == 9  ? MXC_PT9  :                \
00526                                           (i) == 10 ? MXC_PT10 :                \
00527                                           (i) == 11 ? MXC_PT11 :                \
00528                                           (i) == 12 ? MXC_PT12 :                \
00529                                           (i) == 13 ? MXC_PT13 :                \
00530                                           (i) == 14 ? MXC_PT14 :                \
00531                                           (i) == 15 ? MXC_PT15 : 0)
00532 
00533 #define MXC_PT_GET_IDX(p)                ((p) == MXC_PT0  ? 0  :                \
00534                                           (p) == MXC_PT1  ? 1  :                \
00535                                           (p) == MXC_PT2  ? 2  :                \
00536                                           (p) == MXC_PT3  ? 3  :                \
00537                                           (p) == MXC_PT4  ? 4  :                \
00538                                           (p) == MXC_PT5  ? 5  :                \
00539                                           (p) == MXC_PT6  ? 6  :                \
00540                                           (p) == MXC_PT7  ? 7  :                \
00541                                           (p) == MXC_PT8  ? 8  :                \
00542                                           (p) == MXC_PT9  ? 9  :                \
00543                                           (p) == MXC_PT10 ? 10 :                \
00544                                           (p) == MXC_PT11 ? 11 :                \
00545                                           (p) == MXC_PT12 ? 12 :                \
00546                                           (p) == MXC_PT13 ? 13 :                \
00547                                           (p) == MXC_PT14 ? 14 :                \
00548                                           (p) == MXC_PT15 ? 15 : -1)
00549 
00550 
00551 
00552 /*******************************************************************************/
00553 /*                                                UART / Serial Port Interface */
00554 
00555 #define MXC_CFG_UART_INSTANCES           (3)
00556 #define MXC_UART_FIFO_DEPTH              (32)
00557 
00558 #define MXC_BASE_UART0                   ((uint32_t)0x40012000UL)
00559 #define MXC_UART0                        ((mxc_uart_regs_t *)MXC_BASE_UART0)
00560 #define MXC_BASE_UART1                   ((uint32_t)0x40013000UL)
00561 #define MXC_UART1                        ((mxc_uart_regs_t *)MXC_BASE_UART1)
00562 #define MXC_BASE_UART2                   ((uint32_t)0x40014000UL)
00563 #define MXC_UART2                        ((mxc_uart_regs_t *)MXC_BASE_UART2)
00564 #define MXC_BASE_UART0_FIFO              ((uint32_t)0x40103000UL)
00565 #define MXC_UART0_FIFO                   ((mxc_uart_fifo_regs_t *)MXC_BASE_UART0_FIFO)
00566 #define MXC_BASE_UART1_FIFO              ((uint32_t)0x40104000UL)
00567 #define MXC_UART1_FIFO                   ((mxc_uart_fifo_regs_t *)MXC_BASE_UART1_FIFO)
00568 #define MXC_BASE_UART2_FIFO              ((uint32_t)0x40105000UL)
00569 #define MXC_UART2_FIFO                   ((mxc_uart_fifo_regs_t *)MXC_BASE_UART2_FIFO)
00570 
00571 #define MXC_UART_GET_IRQ(i)   (IRQn_Type)((i) == 0 ? UART0_IRQn :             \
00572                                           (i) == 1 ? UART1_IRQn :             \
00573                                           (i) == 2 ? UART2_IRQn : 0)
00574 
00575 #define MXC_UART_GET_BASE(i)             ((i) == 0 ? MXC_BASE_UART0 :         \
00576                                           (i) == 1 ? MXC_BASE_UART1 :         \
00577                                           (i) == 2 ? MXC_BASE_UART2 : 0)
00578 
00579 #define MXC_UART_GET_UART(i)             ((i) == 0 ? MXC_UART0 :              \
00580                                           (i) == 1 ? MXC_UART1 :              \
00581                                           (i) == 2 ? MXC_UART2 : 0)
00582 
00583 #define MXC_UART_GET_IDX(p)              ((p) == MXC_UART0 ? 0 :              \
00584                                           (p) == MXC_UART1 ? 1 :              \
00585                                           (p) == MXC_UART2 ? 2 : -1)
00586 
00587 #define MXC_UART_GET_BASE_FIFO(i)        ((i) == 0 ? MXC_BASE_UART0_FIFO :    \
00588                                           (i) == 1 ? MXC_BASE_UART1_FIFO :    \
00589                                           (i) == 2 ? MXC_BASE_UART2_FIFO : 0)
00590 
00591 #define MXC_UART_GET_FIFO(i)             ((i) == 0 ? MXC_UART0_FIFO :         \
00592                                           (i) == 1 ? MXC_UART1_FIFO :         \
00593                                           (i) == 2 ? MXC_UART2_FIFO : 0)
00594 
00595 
00596 
00597 /*******************************************************************************/
00598 /*                                                        I2C Master Interface */
00599 
00600 #define MXC_CFG_I2CM_INSTANCES           (2)
00601 #define MXC_I2CM_FIFO_DEPTH              (8)
00602 
00603 #define MXC_BASE_I2CM0                   ((uint32_t)0x40016000UL)
00604 #define MXC_I2CM0                        ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
00605 #define MXC_BASE_I2CM1                   ((uint32_t)0x40017000UL)
00606 #define MXC_I2CM1                        ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
00607 #define MXC_BASE_I2CM0_FIFO              ((uint32_t)0x40107000UL)
00608 #define MXC_I2CM0_FIFO                   ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM0_FIFO)
00609 #define MXC_BASE_I2CM1_FIFO              ((uint32_t)0x40108000UL)
00610 #define MXC_I2CM1_FIFO                   ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM1_FIFO)
00611 
00612 #define MXC_I2CM_GET_IRQ(i)   (IRQn_Type)((i) == 0 ? I2CM0_IRQn :              \
00613                                           (i) == 1 ? I2CM1_IRQn : 0)
00614 
00615 #define MXC_I2CM_GET_BASE(i)             ((i) == 0 ? MXC_BASE_I2CM0 :          \
00616                                           (i) == 1 ? MXC_BASE_I2CM1 : 0)
00617 
00618 #define MXC_I2CM_GET_I2CM(i)             ((i) == 0 ? MXC_I2CM0 :               \
00619                                           (i) == 1 ? MXC_I2CM1 : 0)
00620 
00621 #define MXC_I2CM_GET_IDX(p)              ((p) == MXC_I2CM0 ? 0 :               \
00622                                           (p) == MXC_I2CM1 ? 1 : -1)
00623 
00624 #define MXC_I2CM_GET_BASE_FIFO(i)        ((i) == 0 ? MXC_BASE_I2CM0_FIFO :     \
00625                                           (i) == 1 ? MXC_BASE_I2CM1_FIFO : 0)
00626 
00627 #define MXC_I2CM_GET_FIFO(i)             ((i) == 0 ? MXC_I2CM0_FIFO :          \
00628                                           (i) == 1 ? MXC_I2CM1_FIFO : 0)
00629 
00630 
00631 
00632 /*******************************************************************************/
00633 /*                                          I2C Slave Interface (Mailbox type) */
00634 
00635 #define MXC_CFG_I2CS_INSTANCES           (1)
00636 #define MXC_CFG_I2CS_BUFFER_SIZE         (32)
00637 
00638 #define MXC_BASE_I2CS                    ((uint32_t)0x40019000UL)
00639 #define MXC_I2CS                         ((mxc_i2cs_regs_t *)MXC_BASE_I2CS)
00640 
00641 #define MXC_I2CS_GET_IRQ(i)   (IRQn_Type)((i) == 0 ? I2CS_IRQn : 0)
00642 
00643 #define MXC_I2CS_GET_BASE(i)             ((i) == 0 ? MXC_BASE_I2CS : 0)
00644 
00645 #define MXC_I2CS_GET_I2CS(i)             ((i) == 0 ? MXC_I2CS : 0)
00646 
00647 #define MXC_I2CS_GET_IDX(p)              ((p) == MXC_I2CS ? 0 : -1)
00648 
00649 /*******************************************************************************/
00650 /*                                                        SPI Master Interface */
00651 
00652 #define MXC_CFG_SPIM_INSTANCES           (3)
00653 #define MXC_CFG_SPIM_FIFO_DEPTH          (16)
00654 
00655 #define MXC_BASE_SPIM0                   ((uint32_t)0x4001A000UL)
00656 #define MXC_SPIM0                        ((mxc_spim_regs_t *)MXC_BASE_SPIM0)
00657 #define MXC_BASE_SPIM1                   ((uint32_t)0x4001B000UL)
00658 #define MXC_SPIM1                        ((mxc_spim_regs_t *)MXC_BASE_SPIM1)
00659 #define MXC_BASE_SPIM2                   ((uint32_t)0x4001C000UL)
00660 #define MXC_SPIM2                        ((mxc_spim_regs_t *)MXC_BASE_SPIM2)
00661 #define MXC_BASE_SPIM0_FIFO              ((uint32_t)0x4010A000UL)
00662 #define MXC_SPIM0_FIFO                   ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM0_FIFO)
00663 #define MXC_BASE_SPIM1_FIFO              ((uint32_t)0x4010B000UL)
00664 #define MXC_SPIM1_FIFO                   ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM1_FIFO)
00665 #define MXC_BASE_SPIM2_FIFO              ((uint32_t)0x4010C000UL)
00666 #define MXC_SPIM2_FIFO                   ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM2_FIFO)
00667 
00668 #define MXC_SPIM_GET_IRQ(i)   (IRQn_Type)((i) == 0 ? SPIM0_IRQn :             \
00669                                           (i) == 1 ? SPIM1_IRQn :             \
00670                                           (i) == 2 ? SPIM2_IRQn : 0)
00671 
00672 #define MXC_SPIM_GET_BASE(i)             ((i) == 0 ? MXC_BASE_SPIM0 :         \
00673                                           (i) == 1 ? MXC_BASE_SPIM1 :         \
00674                                           (i) == 2 ? MXC_BASE_SPIM2 : 0)
00675 
00676 #define MXC_SPIM_GET_SPIM(i)             ((i) == 0 ? MXC_SPIM0 :              \
00677                                           (i) == 1 ? MXC_SPIM1 :              \
00678                                           (i) == 2 ? MXC_SPIM2 : 0)
00679 
00680 #define MXC_SPIM_GET_IDX(p)              ((p) == MXC_SPIM0 ? 0 :              \
00681                                           (p) == MXC_SPIM1 ? 1 :              \
00682                                           (p) == MXC_SPIM2 ? 2 : -1)
00683 
00684 #define MXC_SPIM_GET_BASE_FIFO(i)        ((i) == 0 ? MXC_BASE_SPIM0_FIFO :    \
00685                                           (i) == 1 ? MXC_BASE_SPIM1_FIFO :    \
00686                                           (i) == 2 ? MXC_BASE_SPIM2_FIFO : 0)
00687 
00688 #define MXC_SPIM_GET_SPIM_FIFO(i)        ((i) == 0 ? MXC_SPIM0_FIFO :         \
00689                                           (i) == 1 ? MXC_SPIM1_FIFO :         \
00690                                           (i) == 2 ? MXC_SPIM2_FIFO : 0)
00691 
00692 
00693 
00694 /*******************************************************************************/
00695 /*                                                     1-Wire Master Interface */
00696 
00697 #define MXC_CFG_OWM_INSTANCES            (1)
00698 
00699 #define MXC_BASE_OWM                     ((uint32_t)0x4001E000UL)
00700 #define MXC_OWM                          ((mxc_owm_regs_t *)MXC_BASE_OWM)
00701 
00702 #define MXC_OWM_GET_IRQ(i)               (IRQn_Type)((i) == 0 ? OWM_IRQn : 0)
00703 
00704 #define MXC_OWM_GET_BASE(i)              ((i) == 0 ? MXC_BASE_OWM : 0)
00705 
00706 #define MXC_OWM_GET_OWM(i)               ((i) == 0 ? MXC_OWM : 0)
00707 
00708 #define MXC_OWM_GET_IDX(p)               ((p) == MXC_OWM ? 0 : -1)
00709 
00710 /*******************************************************************************/
00711 /*                                                                   ADC / AFE */
00712 
00713 #define MXC_CFG_ADC_FIFO_DEPTH           (32)
00714 
00715 #define MXC_BASE_ADC                     ((uint32_t)0x4001F000UL)
00716 #define MXC_ADC                          ((mxc_adc_regs_t *)MXC_BASE_ADC)
00717 
00718 
00719 
00720 /*******************************************************************************/
00721 /*                                                         SPI Slave Interface */
00722 #define MXC_CFG_SPIS_INSTANCES           (1)
00723 #define MXC_CFG_SPIS_FIFO_DEPTH          (32)
00724 
00725 #define MXC_BASE_SPIS                    ((uint32_t)0x40020000UL)
00726 #define MXC_SPIS                         ((mxc_spis_regs_t *)MXC_BASE_SPIS)
00727 #define MXC_BASE_SPIS_FIFO               ((uint32_t)0x4010E000UL)
00728 #define MXC_SPIS_FIFO                    ((mxc_spis_fifo_regs_t *)MXC_BASE_SPIS_FIFO)
00729 
00730 #define MXC_SPIS_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? SPIS_IRQn : 0)
00731 
00732 #define MXC_SPIS_GET_BASE(i)             ((i) == 0 ? MXC_BASE_SPIS : 0)
00733 
00734 #define MXC_SPIS_GET_SPIS(i)             ((i) == 0 ? MXC_SPIS : 0)
00735 
00736 #define MXC_SPIS_GET_IDX(p)              ((p) == MXC_SPIS ? 0 : -1)
00737 
00738 #define MXC_SPIS_GET_BASE_FIFO(i)        ((i) == 0 ? MXC_BASE_SPIS_FIFO : 0)
00739 
00740 #define MXC_SPIS_GET_SPIS_FIFO(i)        ((i) == 0 ? MXC_SPIS_FIFO :0)
00741 
00742 /*******************************************************************************/
00743 /*                                                                Bit Shifting */
00744 
00745 #define MXC_F_BIT_0        (1 << 0)
00746 #define MXC_F_BIT_1        (1 << 1)
00747 #define MXC_F_BIT_2        (1 << 2)
00748 #define MXC_F_BIT_3        (1 << 3)
00749 #define MXC_F_BIT_4        (1 << 4)
00750 #define MXC_F_BIT_5        (1 << 5)
00751 #define MXC_F_BIT_6        (1 << 6)
00752 #define MXC_F_BIT_7        (1 << 7)
00753 #define MXC_F_BIT_8        (1 << 8)
00754 #define MXC_F_BIT_9        (1 << 9)
00755 #define MXC_F_BIT_10       (1 << 10)
00756 #define MXC_F_BIT_11       (1 << 11)
00757 #define MXC_F_BIT_12       (1 << 12)
00758 #define MXC_F_BIT_13       (1 << 13)
00759 #define MXC_F_BIT_14       (1 << 14)
00760 #define MXC_F_BIT_15       (1 << 15)
00761 #define MXC_F_BIT_16       (1 << 16)
00762 #define MXC_F_BIT_17       (1 << 17)
00763 #define MXC_F_BIT_18       (1 << 18)
00764 #define MXC_F_BIT_19       (1 << 19)
00765 #define MXC_F_BIT_20       (1 << 20)
00766 #define MXC_F_BIT_21       (1 << 21)
00767 #define MXC_F_BIT_22       (1 << 22)
00768 #define MXC_F_BIT_23       (1 << 23)
00769 #define MXC_F_BIT_24       (1 << 24)
00770 #define MXC_F_BIT_25       (1 << 25)
00771 #define MXC_F_BIT_26       (1 << 26)
00772 #define MXC_F_BIT_27       (1 << 27)
00773 #define MXC_F_BIT_28       (1 << 28)
00774 #define MXC_F_BIT_29       (1 << 29)
00775 #define MXC_F_BIT_30       (1 << 30)
00776 #define MXC_F_BIT_31       (1 << 31)
00777 
00778 
00779 /*******************************************************************************/
00780 
00781 #define BITBAND(reg, bit)      ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
00782 #define MXC_CLRBIT(reg, bit)   (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
00783 #define MXC_SETBIT(reg, bit)   (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
00784 #define MXC_GETBIT(reg, bit)   (*(volatile uint32_t *)BITBAND(reg, bit))
00785 
00786 
00787 /*******************************************************************************/
00788 
00789 /* SCB CPACR Register Definitions */
00790 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
00791 #define SCB_CPACR_CP10_Pos      20                              /*!< SCB CPACR: Coprocessor 10 Position */
00792 #define SCB_CPACR_CP10_Msk      (0x3UL << SCB_CPACR_CP10_Pos)   /*!< SCB CPACR: Coprocessor 10 Mask */
00793 #define SCB_CPACR_CP11_Pos      22                              /*!< SCB CPACR: Coprocessor 11 Position */
00794 #define SCB_CPACR_CP11_Msk      (0x3UL << SCB_CPACR_CP11_Pos)   /*!< SCB CPACR: Coprocessor 11 Mask */
00795 
00796 #endif  /* _MAX32625_H_ */