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ioman_regs.h
00001 /******************************************************************************* 00002 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. 00003 * 00004 * Permission is hereby granted, free of charge, to any person obtaining a 00005 * copy of this software and associated documentation files (the "Software"), 00006 * to deal in the Software without restriction, including without limitation 00007 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 00008 * and/or sell copies of the Software, and to permit persons to whom the 00009 * Software is furnished to do so, subject to the following conditions: 00010 * 00011 * The above copyright notice and this permission notice shall be included 00012 * in all copies or substantial portions of the Software. 00013 * 00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 00015 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00016 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 00017 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 00018 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 00019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 00020 * OTHER DEALINGS IN THE SOFTWARE. 00021 * 00022 * Except as contained in this notice, the name of Maxim Integrated 00023 * Products, Inc. shall not be used except as stated in the Maxim Integrated 00024 * Products, Inc. Branding Policy. 00025 * 00026 * The mere transfer of this software does not imply any licenses 00027 * of trade secrets, proprietary technology, copyrights, patents, 00028 * trademarks, maskwork rights, or any other form of intellectual 00029 * property whatsoever. Maxim Integrated Products, Inc. retains all 00030 * ownership rights. 00031 * 00032 ******************************************************************************/ 00033 00034 #ifndef _MXC_IOMAN_REGS_H_ 00035 #define _MXC_IOMAN_REGS_H_ 00036 00037 #ifdef __cplusplus 00038 extern "C" { 00039 #endif 00040 00041 #include <stdint.h> 00042 00043 /* 00044 If types are not defined elsewhere (CMSIS) define them here 00045 */ 00046 #ifndef __IO 00047 #define __IO volatile 00048 #endif 00049 #ifndef __I 00050 #define __I volatile const 00051 #endif 00052 #ifndef __O 00053 #define __O volatile 00054 #endif 00055 #ifndef __R 00056 #define __R volatile const 00057 #endif 00058 00059 00060 /* 00061 Bitfield structs for registers in this module 00062 */ 00063 00064 typedef struct { 00065 uint32_t wud_req_p0 : 8; 00066 uint32_t wud_req_p1 : 8; 00067 uint32_t wud_req_p2 : 8; 00068 uint32_t wud_req_p3 : 8; 00069 } mxc_ioman_wud_req0_t; 00070 00071 typedef struct { 00072 uint32_t wud_req_p4 : 8; 00073 uint32_t : 24; 00074 } mxc_ioman_wud_req1_t; 00075 00076 typedef struct { 00077 uint32_t wud_ack_p0 : 8; 00078 uint32_t wud_ack_p1 : 8; 00079 uint32_t wud_ack_p2 : 8; 00080 uint32_t wud_ack_p3 : 8; 00081 } mxc_ioman_wud_ack0_t; 00082 00083 typedef struct { 00084 uint32_t wud_ack_p4 : 8; 00085 uint32_t : 24; 00086 } mxc_ioman_wud_ack1_t; 00087 00088 typedef struct { 00089 uint32_t ali_req_p0 : 8; 00090 uint32_t ali_req_p1 : 8; 00091 uint32_t ali_req_p2 : 8; 00092 uint32_t ali_req_p3 : 8; 00093 } mxc_ioman_ali_req0_t; 00094 00095 typedef struct { 00096 uint32_t ali_req_p4 : 8; 00097 uint32_t : 24; 00098 } mxc_ioman_ali_req1_t; 00099 00100 typedef struct { 00101 uint32_t ali_ack_p0 : 8; 00102 uint32_t ali_ack_p1 : 8; 00103 uint32_t ali_ack_p2 : 8; 00104 uint32_t ali_ack_p3 : 8; 00105 } mxc_ioman_ali_ack0_t; 00106 00107 typedef struct { 00108 uint32_t ali_ack_p4 : 8; 00109 uint32_t : 24; 00110 } mxc_ioman_ali_ack1_t; 00111 00112 typedef struct { 00113 uint32_t : 4; 00114 uint32_t core_io_req : 1; 00115 uint32_t : 3; 00116 uint32_t ss0_io_req : 1; 00117 uint32_t ss1_io_req : 1; 00118 uint32_t ss2_io_req : 1; 00119 uint32_t : 1; 00120 uint32_t quad_io_req : 1; 00121 uint32_t : 3; 00122 uint32_t fast_mode : 1; 00123 uint32_t : 15; 00124 } mxc_ioman_spix_req_t; 00125 00126 typedef struct { 00127 uint32_t : 4; 00128 uint32_t core_io_ack : 1; 00129 uint32_t : 3; 00130 uint32_t ss0_io_ack : 1; 00131 uint32_t ss1_io_ack : 1; 00132 uint32_t ss2_io_ack : 1; 00133 uint32_t : 1; 00134 uint32_t quad_io_ack : 1; 00135 uint32_t : 3; 00136 uint32_t fast_mode : 1; 00137 uint32_t : 15; 00138 } mxc_ioman_spix_ack_t; 00139 00140 typedef struct { 00141 uint32_t io_map : 1; 00142 uint32_t cts_map : 1; 00143 uint32_t rts_map : 1; 00144 uint32_t : 1; 00145 uint32_t io_req : 1; 00146 uint32_t cts_io_req : 1; 00147 uint32_t rts_io_req : 1; 00148 uint32_t : 25; 00149 } mxc_ioman_uart0_req_t; 00150 00151 typedef struct { 00152 uint32_t io_map : 1; 00153 uint32_t cts_map : 1; 00154 uint32_t rts_map : 1; 00155 uint32_t : 1; 00156 uint32_t io_ack : 1; 00157 uint32_t cts_io_ack : 1; 00158 uint32_t rts_io_ack : 1; 00159 uint32_t : 25; 00160 } mxc_ioman_uart0_ack_t; 00161 00162 typedef struct { 00163 uint32_t io_map : 1; 00164 uint32_t cts_map : 1; 00165 uint32_t rts_map : 1; 00166 uint32_t : 1; 00167 uint32_t io_req : 1; 00168 uint32_t cts_io_req : 1; 00169 uint32_t rts_io_req : 1; 00170 uint32_t : 25; 00171 } mxc_ioman_uart1_req_t; 00172 00173 typedef struct { 00174 uint32_t io_map : 1; 00175 uint32_t cts_map : 1; 00176 uint32_t rts_map : 1; 00177 uint32_t : 1; 00178 uint32_t io_ack : 1; 00179 uint32_t cts_io_ack : 1; 00180 uint32_t rts_io_ack : 1; 00181 uint32_t : 25; 00182 } mxc_ioman_uart1_ack_t; 00183 00184 typedef struct { 00185 uint32_t io_map : 1; 00186 uint32_t cts_map : 1; 00187 uint32_t rts_map : 1; 00188 uint32_t : 1; 00189 uint32_t io_req : 1; 00190 uint32_t cts_io_req : 1; 00191 uint32_t rts_io_req : 1; 00192 uint32_t : 25; 00193 } mxc_ioman_uart2_req_t; 00194 00195 typedef struct { 00196 uint32_t io_map : 1; 00197 uint32_t cts_map : 1; 00198 uint32_t rts_map : 1; 00199 uint32_t : 1; 00200 uint32_t io_ack : 1; 00201 uint32_t cts_io_ack : 1; 00202 uint32_t rts_io_ack : 1; 00203 uint32_t : 25; 00204 } mxc_ioman_uart2_ack_t; 00205 00206 typedef struct { 00207 uint32_t : 4; 00208 uint32_t mapping_req : 1; 00209 uint32_t scl_push_pull : 1; 00210 uint32_t : 26; 00211 } mxc_ioman_i2cm0_req_t; 00212 00213 typedef struct { 00214 uint32_t : 4; 00215 uint32_t mapping_ack : 1; 00216 uint32_t : 27; 00217 } mxc_ioman_i2cm0_ack_t; 00218 00219 typedef struct { 00220 uint32_t : 4; 00221 uint32_t mapping_req : 1; 00222 uint32_t scl_push_pull : 1; 00223 uint32_t : 26; 00224 } mxc_ioman_i2cm1_req_t; 00225 00226 typedef struct { 00227 uint32_t : 4; 00228 uint32_t mapping_ack : 1; 00229 uint32_t : 27; 00230 } mxc_ioman_i2cm1_ack_t; 00231 00232 typedef struct { 00233 uint32_t io_sel : 2; 00234 uint32_t : 2; 00235 uint32_t mapping_req : 1; 00236 uint32_t : 27; 00237 } mxc_ioman_i2cs_req_t; 00238 00239 typedef struct { 00240 uint32_t io_sel : 2; 00241 uint32_t : 2; 00242 uint32_t mapping_ack : 1; 00243 uint32_t : 27; 00244 } mxc_ioman_i2cs_ack_t; 00245 00246 typedef struct { 00247 uint32_t : 4; 00248 uint32_t core_io_req : 1; 00249 uint32_t : 3; 00250 uint32_t ss0_io_req : 1; 00251 uint32_t ss1_io_req : 1; 00252 uint32_t ss2_io_req : 1; 00253 uint32_t ss3_io_req : 1; 00254 uint32_t ss4_io_req : 1; 00255 uint32_t : 7; 00256 uint32_t quad_io_req : 1; 00257 uint32_t : 3; 00258 uint32_t fast_mode : 1; 00259 uint32_t : 7; 00260 } mxc_ioman_spim0_req_t; 00261 00262 typedef struct { 00263 uint32_t : 4; 00264 uint32_t core_io_ack : 1; 00265 uint32_t : 3; 00266 uint32_t ss0_io_ack : 1; 00267 uint32_t ss1_io_ack : 1; 00268 uint32_t ss2_io_ack : 1; 00269 uint32_t ss3_io_ack : 1; 00270 uint32_t ss4_io_ack : 1; 00271 uint32_t : 7; 00272 uint32_t quad_io_ack : 1; 00273 uint32_t : 3; 00274 uint32_t fast_mode : 1; 00275 uint32_t : 7; 00276 } mxc_ioman_spim0_ack_t; 00277 00278 typedef struct { 00279 uint32_t : 4; 00280 uint32_t core_io_req : 1; 00281 uint32_t : 3; 00282 uint32_t ss0_io_req : 1; 00283 uint32_t ss1_io_req : 1; 00284 uint32_t ss2_io_req : 1; 00285 uint32_t : 9; 00286 uint32_t quad_io_req : 1; 00287 uint32_t : 3; 00288 uint32_t fast_mode : 1; 00289 uint32_t : 7; 00290 } mxc_ioman_spim1_req_t; 00291 00292 typedef struct { 00293 uint32_t : 4; 00294 uint32_t core_io_ack : 1; 00295 uint32_t : 3; 00296 uint32_t ss0_io_ack : 1; 00297 uint32_t ss1_io_ack : 1; 00298 uint32_t ss2_io_ack : 1; 00299 uint32_t : 9; 00300 uint32_t quad_io_ack : 1; 00301 uint32_t : 3; 00302 uint32_t fast_mode : 1; 00303 uint32_t : 7; 00304 } mxc_ioman_spim1_ack_t; 00305 00306 typedef struct { 00307 uint32_t mapping_req : 1; 00308 uint32_t : 3; 00309 uint32_t core_io_req : 1; 00310 uint32_t : 3; 00311 uint32_t ss0_io_req : 1; 00312 uint32_t ss1_io_req : 1; 00313 uint32_t ss2_io_req : 1; 00314 uint32_t : 5; 00315 uint32_t sr0_io_req : 1; 00316 uint32_t sr1_io_req : 1; 00317 uint32_t : 2; 00318 uint32_t quad_io_req : 1; 00319 uint32_t : 3; 00320 uint32_t fast_mode : 1; 00321 uint32_t : 7; 00322 } mxc_ioman_spim2_req_t; 00323 00324 typedef struct { 00325 uint32_t mapping_ack : 1; 00326 uint32_t : 3; 00327 uint32_t core_io_ack : 1; 00328 uint32_t : 3; 00329 uint32_t ss0_io_ack : 1; 00330 uint32_t ss1_io_ack : 1; 00331 uint32_t ss2_io_ack : 1; 00332 uint32_t : 5; 00333 uint32_t sr0_io_ack : 1; 00334 uint32_t sr1_io_ack : 1; 00335 uint32_t : 2; 00336 uint32_t quad_io_ack : 1; 00337 uint32_t : 3; 00338 uint32_t fast_mode : 1; 00339 uint32_t : 7; 00340 } mxc_ioman_spim2_ack_t; 00341 00342 typedef struct { 00343 uint32_t : 4; 00344 uint32_t mapping_req : 1; 00345 uint32_t epu_io_req : 1; 00346 uint32_t : 26; 00347 } mxc_ioman_owm_req_t; 00348 00349 typedef struct { 00350 uint32_t : 4; 00351 uint32_t mapping_ack : 1; 00352 uint32_t epu_io_ack : 1; 00353 uint32_t : 26; 00354 } mxc_ioman_owm_ack_t; 00355 00356 typedef struct { 00357 uint32_t : 4; 00358 uint32_t core_io_req : 1; 00359 uint32_t : 3; 00360 uint32_t quad_io_req : 1; 00361 uint32_t : 3; 00362 uint32_t fast_mode : 1; 00363 uint32_t : 19; 00364 } mxc_ioman_spis_req_t; 00365 00366 typedef struct { 00367 uint32_t : 4; 00368 uint32_t core_io_ack : 1; 00369 uint32_t : 3; 00370 uint32_t quad_io_ack : 1; 00371 uint32_t : 3; 00372 uint32_t fast_mode : 1; 00373 uint32_t : 19; 00374 } mxc_ioman_spis_ack_t; 00375 00376 typedef struct { 00377 uint32_t slow_mode : 1; 00378 uint32_t alt_rcvr_mode : 1; 00379 uint32_t : 30; 00380 } mxc_ioman_pad_mode_t; 00381 00382 00383 /* 00384 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit 00385 access to each register in module. 00386 */ 00387 00388 /* Offset Register Description 00389 ============= ============================================================================ */ 00390 typedef struct { 00391 __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 (P0/P1/P2/P3) */ 00392 __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 (P4) */ 00393 __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 (P0/P1/P2/P3) */ 00394 __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 (P4) */ 00395 __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 (P0/P1/P2/P3) */ 00396 __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 (P4) */ 00397 __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 (P0/P1/P2/P3) */ 00398 __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 (P4) */ 00399 __IO uint32_t ali_connect0; /* 0x0020 Analog I/O Connection Control Register 0 */ 00400 __IO uint32_t ali_connect1; /* 0x0024 Analog I/O Connection Control Register 1 */ 00401 __IO uint32_t spix_req; /* 0x0028 SPIX I/O Mode Request */ 00402 __IO uint32_t spix_ack; /* 0x002C SPIX I/O Mode Acknowledge */ 00403 __IO uint32_t uart0_req; /* 0x0030 UART0 I/O Mode Request */ 00404 __IO uint32_t uart0_ack; /* 0x0034 UART0 I/O Mode Acknowledge */ 00405 __IO uint32_t uart1_req; /* 0x0038 UART1 I/O Mode Request */ 00406 __IO uint32_t uart1_ack; /* 0x003C UART1 I/O Mode Acknowledge */ 00407 __IO uint32_t uart2_req; /* 0x0040 UART2 I/O Mode Request */ 00408 __IO uint32_t uart2_ack; /* 0x0044 UART2 I/O Mode Acknowledge */ 00409 __R uint32_t rsv048[2]; /* 0x0048-0x004C */ 00410 __IO uint32_t i2cm0_req; /* 0x0050 I2C Master 0 I/O Request */ 00411 __IO uint32_t i2cm0_ack; /* 0x0054 I2C Master 0 I/O Acknowledge */ 00412 __IO uint32_t i2cm1_req; /* 0x0058 I2C Master 1 I/O Request */ 00413 __IO uint32_t i2cm1_ack; /* 0x005C I2C Master 1 I/O Acknowledge */ 00414 __R uint32_t rsv060[2]; /* 0x0060-0x0064 */ 00415 __IO uint32_t i2cs_req; /* 0x0068 I2C Slave I/O Request */ 00416 __IO uint32_t i2cs_ack; /* 0x006C I2C Slave I/O Acknowledge */ 00417 __IO uint32_t spim0_req; /* 0x0070 SPI Master 0 I/O Mode Request */ 00418 __IO uint32_t spim0_ack; /* 0x0074 SPI Master 0 I/O Mode Acknowledge */ 00419 __IO uint32_t spim1_req; /* 0x0078 SPI Master 1 I/O Mode Request */ 00420 __IO uint32_t spim1_ack; /* 0x007C SPI Master 1 I/O Mode Acknowledge */ 00421 __IO uint32_t spim2_req; /* 0x0080 SPI Master 2 I/O Mode Request */ 00422 __IO uint32_t spim2_ack; /* 0x0084 SPI Master 2 I/O Mode Acknowledge */ 00423 __R uint32_t rsv088[2]; /* 0x0088-0x008C */ 00424 __IO uint32_t owm_req; /* 0x0090 1-Wire Master I/O Mode Request */ 00425 __IO uint32_t owm_ack; /* 0x0094 1-Wire Master I/O Mode Acknowledge */ 00426 __IO uint32_t spis_req; /* 0x0098 SPI Slave I/O Mode Request */ 00427 __IO uint32_t spis_ack; /* 0x009C SPI Slave I/O Mode Acknowledge */ 00428 __R uint32_t rsv0A0[24]; /* 0x00A0-0x00FC */ 00429 __IO uint32_t use_vddioh_0; /* 0x0100 Enable VDDIOH Register 0 */ 00430 __IO uint32_t use_vddioh_1; /* 0x0104 Enable VDDIOH Register 1 */ 00431 __R uint32_t rsv108[2]; /* 0x0108-0x010C */ 00432 __IO uint32_t pad_mode; /* 0x0110 Pad Mode Control Register */ 00433 } mxc_ioman_regs_t; 00434 00435 00436 /* 00437 Register offsets for module IOMAN. 00438 */ 00439 00440 #define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL) 00441 #define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL) 00442 #define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL) 00443 #define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL) 00444 #define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL) 00445 #define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL) 00446 #define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL) 00447 #define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL) 00448 #define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x00000020UL) 00449 #define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000024UL) 00450 #define MXC_R_IOMAN_OFFS_SPIX_REQ ((uint32_t)0x00000028UL) 00451 #define MXC_R_IOMAN_OFFS_SPIX_ACK ((uint32_t)0x0000002CUL) 00452 #define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000030UL) 00453 #define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x00000034UL) 00454 #define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000038UL) 00455 #define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x0000003CUL) 00456 #define MXC_R_IOMAN_OFFS_UART2_REQ ((uint32_t)0x00000040UL) 00457 #define MXC_R_IOMAN_OFFS_UART2_ACK ((uint32_t)0x00000044UL) 00458 #define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000050UL) 00459 #define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x00000054UL) 00460 #define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000058UL) 00461 #define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x0000005CUL) 00462 #define MXC_R_IOMAN_OFFS_I2CS_REQ ((uint32_t)0x00000068UL) 00463 #define MXC_R_IOMAN_OFFS_I2CS_ACK ((uint32_t)0x0000006CUL) 00464 #define MXC_R_IOMAN_OFFS_SPIM0_REQ ((uint32_t)0x00000070UL) 00465 #define MXC_R_IOMAN_OFFS_SPIM0_ACK ((uint32_t)0x00000074UL) 00466 #define MXC_R_IOMAN_OFFS_SPIM1_REQ ((uint32_t)0x00000078UL) 00467 #define MXC_R_IOMAN_OFFS_SPIM1_ACK ((uint32_t)0x0000007CUL) 00468 #define MXC_R_IOMAN_OFFS_SPIM2_REQ ((uint32_t)0x00000080UL) 00469 #define MXC_R_IOMAN_OFFS_SPIM2_ACK ((uint32_t)0x00000084UL) 00470 #define MXC_R_IOMAN_OFFS_OWM_REQ ((uint32_t)0x00000090UL) 00471 #define MXC_R_IOMAN_OFFS_OWM_ACK ((uint32_t)0x00000094UL) 00472 #define MXC_R_IOMAN_OFFS_SPIS_REQ ((uint32_t)0x00000098UL) 00473 #define MXC_R_IOMAN_OFFS_SPIS_ACK ((uint32_t)0x0000009CUL) 00474 #define MXC_R_IOMAN_OFFS_USE_VDDIOH_0 ((uint32_t)0x00000100UL) 00475 #define MXC_R_IOMAN_OFFS_USE_VDDIOH_1 ((uint32_t)0x00000104UL) 00476 #define MXC_R_IOMAN_OFFS_PAD_MODE ((uint32_t)0x00000110UL) 00477 00478 00479 /* 00480 Field positions and masks for module IOMAN. 00481 */ 00482 00483 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS 0 00484 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS)) 00485 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS 8 00486 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS)) 00487 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS 16 00488 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS)) 00489 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS 24 00490 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS)) 00491 00492 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS 0 00493 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS)) 00494 00495 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS 0 00496 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS)) 00497 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS 8 00498 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS)) 00499 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS 16 00500 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS)) 00501 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS 24 00502 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS)) 00503 00504 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS 0 00505 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS)) 00506 00507 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS 0 00508 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS)) 00509 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS 8 00510 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS)) 00511 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS 16 00512 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS)) 00513 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS 24 00514 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS)) 00515 00516 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS 0 00517 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS)) 00518 00519 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS 0 00520 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS)) 00521 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS 8 00522 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS)) 00523 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS 16 00524 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS)) 00525 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS 24 00526 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS)) 00527 00528 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS 0 00529 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS)) 00530 00531 #define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS 4 00532 #define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS)) 00533 #define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS 8 00534 #define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS)) 00535 #define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS 9 00536 #define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS)) 00537 #define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS 10 00538 #define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS)) 00539 #define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS 12 00540 #define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS)) 00541 #define MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS 16 00542 #define MXC_F_IOMAN_SPIX_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS)) 00543 00544 #define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS 4 00545 #define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS)) 00546 #define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS 8 00547 #define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS)) 00548 #define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS 9 00549 #define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS)) 00550 #define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS 10 00551 #define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS)) 00552 #define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS 12 00553 #define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS)) 00554 #define MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS 16 00555 #define MXC_F_IOMAN_SPIX_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS)) 00556 00557 #define MXC_F_IOMAN_UART0_REQ_IO_MAP_POS 0 00558 #define MXC_F_IOMAN_UART0_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS)) 00559 #define MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS 1 00560 #define MXC_F_IOMAN_UART0_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS)) 00561 #define MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS 2 00562 #define MXC_F_IOMAN_UART0_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS)) 00563 #define MXC_F_IOMAN_UART0_REQ_IO_REQ_POS 4 00564 #define MXC_F_IOMAN_UART0_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_REQ_POS)) 00565 #define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS 5 00566 #define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS)) 00567 #define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS 6 00568 #define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS)) 00569 00570 #define MXC_F_IOMAN_UART0_ACK_IO_MAP_POS 0 00571 #define MXC_F_IOMAN_UART0_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_MAP_POS)) 00572 #define MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS 1 00573 #define MXC_F_IOMAN_UART0_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS)) 00574 #define MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS 2 00575 #define MXC_F_IOMAN_UART0_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS)) 00576 #define MXC_F_IOMAN_UART0_ACK_IO_ACK_POS 4 00577 #define MXC_F_IOMAN_UART0_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_ACK_POS)) 00578 #define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS 5 00579 #define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS)) 00580 #define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS 6 00581 #define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS)) 00582 00583 #define MXC_F_IOMAN_UART1_REQ_IO_MAP_POS 0 00584 #define MXC_F_IOMAN_UART1_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_MAP_POS)) 00585 #define MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS 1 00586 #define MXC_F_IOMAN_UART1_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS)) 00587 #define MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS 2 00588 #define MXC_F_IOMAN_UART1_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS)) 00589 #define MXC_F_IOMAN_UART1_REQ_IO_REQ_POS 4 00590 #define MXC_F_IOMAN_UART1_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_REQ_POS)) 00591 #define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS 5 00592 #define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS)) 00593 #define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS 6 00594 #define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS)) 00595 00596 #define MXC_F_IOMAN_UART1_ACK_IO_MAP_POS 0 00597 #define MXC_F_IOMAN_UART1_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_MAP_POS)) 00598 #define MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS 1 00599 #define MXC_F_IOMAN_UART1_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS)) 00600 #define MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS 2 00601 #define MXC_F_IOMAN_UART1_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS)) 00602 #define MXC_F_IOMAN_UART1_ACK_IO_ACK_POS 4 00603 #define MXC_F_IOMAN_UART1_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_ACK_POS)) 00604 #define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS 5 00605 #define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS)) 00606 #define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS 6 00607 #define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS)) 00608 00609 #define MXC_F_IOMAN_UART2_REQ_IO_MAP_POS 0 00610 #define MXC_F_IOMAN_UART2_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_MAP_POS)) 00611 #define MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS 1 00612 #define MXC_F_IOMAN_UART2_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS)) 00613 #define MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS 2 00614 #define MXC_F_IOMAN_UART2_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS)) 00615 #define MXC_F_IOMAN_UART2_REQ_IO_REQ_POS 4 00616 #define MXC_F_IOMAN_UART2_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_REQ_POS)) 00617 #define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS 5 00618 #define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS)) 00619 #define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS 6 00620 #define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS)) 00621 00622 #define MXC_F_IOMAN_UART2_ACK_IO_MAP_POS 0 00623 #define MXC_F_IOMAN_UART2_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_MAP_POS)) 00624 #define MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS 1 00625 #define MXC_F_IOMAN_UART2_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS)) 00626 #define MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS 2 00627 #define MXC_F_IOMAN_UART2_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS)) 00628 #define MXC_F_IOMAN_UART2_ACK_IO_ACK_POS 4 00629 #define MXC_F_IOMAN_UART2_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_ACK_POS)) 00630 #define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS 5 00631 #define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS)) 00632 #define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS 6 00633 #define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS)) 00634 00635 #define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS 4 00636 #define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS)) 00637 #define MXC_F_IOMAN_I2CM0_REQ_SCL_PUSH_PULL_POS 5 00638 #define MXC_F_IOMAN_I2CM0_REQ_SCL_PUSH_PULL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_SCL_PUSH_PULL_POS)) 00639 00640 #define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS 4 00641 #define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS)) 00642 00643 #define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS 4 00644 #define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS)) 00645 #define MXC_F_IOMAN_I2CM1_REQ_SCL_PUSH_PULL_POS 5 00646 #define MXC_F_IOMAN_I2CM1_REQ_SCL_PUSH_PULL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_REQ_SCL_PUSH_PULL_POS)) 00647 00648 #define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS 4 00649 #define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS)) 00650 00651 #define MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS 0 00652 #define MXC_F_IOMAN_I2CS_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS)) 00653 #define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS 4 00654 #define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS)) 00655 00656 #define MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS 0 00657 #define MXC_F_IOMAN_I2CS_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS)) 00658 #define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS 4 00659 #define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS)) 00660 00661 #define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS 4 00662 #define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS)) 00663 #define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS 8 00664 #define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS)) 00665 #define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS 9 00666 #define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS)) 00667 #define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS 10 00668 #define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS)) 00669 #define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS 11 00670 #define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS)) 00671 #define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS 12 00672 #define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS)) 00673 #define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS 20 00674 #define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS)) 00675 #define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS 24 00676 #define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS)) 00677 00678 #define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS 4 00679 #define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS)) 00680 #define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS 8 00681 #define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS)) 00682 #define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS 9 00683 #define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS)) 00684 #define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS 10 00685 #define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS)) 00686 #define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS 11 00687 #define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS)) 00688 #define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS 12 00689 #define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS)) 00690 #define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS 20 00691 #define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS)) 00692 #define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS 24 00693 #define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS)) 00694 00695 #define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS 4 00696 #define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS)) 00697 #define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS 8 00698 #define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS)) 00699 #define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS 9 00700 #define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS)) 00701 #define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS 10 00702 #define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS)) 00703 #define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS 20 00704 #define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS)) 00705 #define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS 24 00706 #define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS)) 00707 00708 #define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS 4 00709 #define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS)) 00710 #define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS 8 00711 #define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS)) 00712 #define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS 9 00713 #define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS)) 00714 #define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS 10 00715 #define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS)) 00716 #define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS 20 00717 #define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS)) 00718 #define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS 24 00719 #define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS)) 00720 00721 #define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS 0 00722 #define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS)) 00723 #define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS 4 00724 #define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS)) 00725 #define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS 8 00726 #define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS)) 00727 #define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS 9 00728 #define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS)) 00729 #define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS 10 00730 #define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS)) 00731 #define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS 16 00732 #define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS)) 00733 #define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS 17 00734 #define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS)) 00735 #define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS 24 00736 #define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS)) 00737 00738 #define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS 0 00739 #define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS)) 00740 #define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS 4 00741 #define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS)) 00742 #define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS 8 00743 #define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS)) 00744 #define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS 9 00745 #define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS)) 00746 #define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS 10 00747 #define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS)) 00748 #define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS 16 00749 #define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS)) 00750 #define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS 17 00751 #define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS)) 00752 #define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS 24 00753 #define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS)) 00754 00755 #define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS 4 00756 #define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS)) 00757 #define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS 5 00758 #define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS)) 00759 00760 #define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS 4 00761 #define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS)) 00762 #define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS 5 00763 #define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS)) 00764 00765 #define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS 4 00766 #define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS)) 00767 #define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS 8 00768 #define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS)) 00769 #define MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS 12 00770 #define MXC_F_IOMAN_SPIS_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS)) 00771 00772 #define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS 4 00773 #define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS)) 00774 #define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS 8 00775 #define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS)) 00776 #define MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS 12 00777 #define MXC_F_IOMAN_SPIS_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS)) 00778 00779 #define MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS 0 00780 #define MXC_F_IOMAN_PAD_MODE_SLOW_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS)) 00781 #define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS 1 00782 #define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS)) 00783 00784 #define MXC_V_IOMAN_MAP_A ((uint32_t)0x00000000UL) 00785 #define MXC_V_IOMAN_MAP_B ((uint32_t)0x00000001UL) 00786 #define MXC_V_IOMAN_MAP_C ((uint32_t)0x00000002UL) 00787 #define MXC_V_IOMAN_MAP_D ((uint32_t)0x00000003UL) 00788 #define MXC_V_IOMAN_MAP_E ((uint32_t)0x00000004UL) 00789 #define MXC_V_IOMAN_MAP_F ((uint32_t)0x00000005UL) 00790 #define MXC_V_IOMAN_MAP_G ((uint32_t)0x00000006UL) 00791 00792 #ifdef __cplusplus 00793 } 00794 #endif 00795 00796 #endif /* _MXC_IOMAN_REGS_H_ */
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