icc_regs.h

00001 /* ****************************************************************************
00002  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
00003  *
00004  * Permission is hereby granted, free of charge, to any person obtaining a
00005  * copy of this software and associated documentation files (the "Software"),
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00009  * Software is furnished to do so, subject to the following conditions:
00010  *
00011  * The above copyright notice and this permission notice shall be included
00012  * in all copies or substantial portions of the Software.
00013  *
00014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00016  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
00017  * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
00018  * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
00019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
00020  * OTHER DEALINGS IN THE SOFTWARE.
00021  *
00022  * Except as contained in this notice, the name of Maxim Integrated
00023  * Products, Inc. shall not be used except as stated in the Maxim Integrated
00024  * Products, Inc. Branding Policy.
00025  *
00026  * The mere transfer of this software does not imply any licenses
00027  * of trade secrets, proprietary technology, copyrights, patents,
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00032  *************************************************************************** */
00033 
00034 /* Define to prevent redundant inclusion */
00035 #ifndef _MXC_ICC_REGS_H_
00036 #define _MXC_ICC_REGS_H_
00037 
00038 /* **** Includes **** */
00039 #include <stdint.h>
00040 
00041 #ifdef __cplusplus
00042 extern "C" {
00043 #endif
00044 
00045 /// @cond
00046 /*
00047     If types are not defined elsewhere (CMSIS) define them here
00048 */
00049 #ifndef __IO
00050 #define __IO volatile
00051 #endif
00052 #ifndef __I
00053 #define __I  volatile const
00054 #endif
00055 #ifndef __O
00056 #define __O  volatile
00057 #endif
00058 #ifndef __R
00059 #define __R  volatile const
00060 #endif
00061 ///@endcond
00062 
00063 /* **** Definitions **** */
00064 
00065 /**
00066  * @defgroup    icc_registers Registers
00067  * @brief       Registers, Bit Masks and Bit Positions for the ICC.
00068  * @ingroup     icc
00069  * @{
00070  */
00071 
00072 /**
00073  * Structure type to access the ICC Registers.
00074  */
00075 typedef struct {
00076     __IO uint32_t id;                                   /**< <tt>\b 0x0000: </tt> ICC_ID Register \warning INTERNAL USE ONLY, DO NOT MODIFY  */
00077     __IO uint32_t mem_cfg;                              /**< <tt>\b 0x0004: </tt> ICC_MEM_CFG Register                                       */
00078     __R  uint32_t rsv008[62];                           /**< <tt>\b 0x0008-0x00FC: </tt> RESERVED                                            */
00079     __IO uint32_t ctrl_stat;                            /**< <tt>\b 0x0100: </tt> ICC_CTRL_STAT Register                                     */
00080     __R  uint32_t rsv104[383];                          /**< <tt>\b 0x0104-0x06FC: </tt> RESERVED                                            */
00081     __IO uint32_t invdt_all;                            /**< <tt>\b 0x0700: </tt> ICC_INVDT_ALL Register                                     */
00082 } mxc_icc_regs_t;
00083 /**@} end of group icc_registers*/
00084 
00085 /*
00086    Register offsets for module ICC.
00087 */
00088 /**
00089  * @defgroup   ICC_Register_Offsets Register Offsets
00090  * @ingroup    icc_registers
00091  * @brief      Instruction Cache Controller Register Offsets from the ICC Base Address.
00092  * @{
00093  */
00094 #define MXC_R_ICC_OFFS_ID                                   ((uint32_t)0x00000000UL)  /**< Offset from ICC Base Address: <tt>\b 0x0000</tt>         */
00095 #define MXC_R_ICC_OFFS_MEM_CFG                              ((uint32_t)0x00000004UL)  /**< Offset from ICC Base Address: <tt>\b 0x0004</tt>         */
00096 #define MXC_R_ICC_OFFS_CTRL_STAT                            ((uint32_t)0x00000100UL)  /**< Offset from ICC Base Address: <tt>\b 0x0100</tt>         */
00097 #define MXC_R_ICC_OFFS_INVDT_ALL                            ((uint32_t)0x00000700UL)  /**< Offset from ICC Base Address: <tt>\b 0x0700</tt>         */
00098 /**@} end of group icc_registers */
00099 
00100 /*
00101    Field positions and masks for module ICC.
00102 */
00103 /**
00104  * @defgroup ICC_ID_Register ICC_ID
00105  * @brief    Field Positions and Bit Masks for the ICC_ID register
00106  * @ingroup  icc_registers
00107  * @{
00108  */
00109 #define MXC_F_ICC_ID_RTL_VERSION_POS                        0                                                                     /**< RTL_VERSION Position           */
00110 #define MXC_F_ICC_ID_RTL_VERSION                            ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS))            /**< RTL_VERSION Mask               */
00111 #define MXC_F_ICC_ID_PART_NUM_POS                           6                                                                     /**< PART_NUM Position              */
00112 #define MXC_F_ICC_ID_PART_NUM                               ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS))               /**< PART_NUM Mask                  */
00113 #define MXC_F_ICC_ID_CACHE_ID_POS                           10                                                                    /**< CACHE_ID Position              */
00114 #define MXC_F_ICC_ID_CACHE_ID                               ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS))               /**< CACHE_ID Mask                  */
00115 /**@} end of group ICC_ID_register */
00116 /**
00117  * @defgroup ICC_MEM_CFG_Register ICC_MEM_CFG
00118  * @brief    Field Positions and Bit Masks for the ICC_MEM_CFG register
00119  * @ingroup  icc_registers
00120  * @{
00121  */
00122 #define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS                    0                                                                     /**< CACHE_SIZE Position       */
00123 #define MXC_F_ICC_MEM_CFG_CACHE_SIZE                        ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS))        /**< CACHE_SIZE Mask           */
00124 #define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS              16                                                                    /**< MAIN_MEMORY_SIZE Position */
00125 #define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE                  ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS))  /**< MAIN_MEMORY_SIZE Mask     */
00126 /**@} end of group ICC_MEM_CFG_register */
00127 /**
00128  * @defgroup ICC_CTRL_STAT_Register ICC_CTRL_STAT
00129  * @brief    Field Positions and Bit Masks for the ICC_CTRL_STAT register
00130  * @ingroup  icc_registers
00131  * @{
00132  */
00133 #define MXC_F_ICC_CTRL_STAT_ENABLE_POS                      0                                                                     /**< ENABLE Position         */
00134 #define MXC_F_ICC_CTRL_STAT_ENABLE                          ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS))          /**< ENABLE Mask             */
00135 #define MXC_F_ICC_CTRL_STAT_READY_POS                       16                                                                    /**< READY Position          */
00136 #define MXC_F_ICC_CTRL_STAT_READY                           ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS))           /**< READY Mask              */
00137 /**@} end of group ICC_CTRL_STAT_register */
00138 
00139 #ifdef __cplusplus
00140 }
00141 #endif
00142 
00143 #endif   /* _MXC_ICC_REGS_H_ */