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flc_regs.h
00001 /* **************************************************************************** 00002 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. 00003 * 00004 * Permission is hereby granted, free of charge, to any person obtaining a 00005 * copy of this software and associated documentation files (the "Software"), 00006 * to deal in the Software without restriction, including without limitation 00007 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 00008 * and/or sell copies of the Software, and to permit persons to whom the 00009 * Software is furnished to do so, subject to the following conditions: 00010 * 00011 * The above copyright notice and this permission notice shall be included 00012 * in all copies or substantial portions of the Software. 00013 * 00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 00015 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00016 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 00017 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 00018 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 00019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 00020 * OTHER DEALINGS IN THE SOFTWARE. 00021 * 00022 * Except as contained in this notice, the name of Maxim Integrated 00023 * Products, Inc. shall not be used except as stated in the Maxim Integrated 00024 * Products, Inc. Branding Policy. 00025 * 00026 * The mere transfer of this software does not imply any licenses 00027 * of trade secrets, proprietary technology, copyrights, patents, 00028 * trademarks, Maskwork rights, or any other form of intellectual 00029 * property whatsoever. Maxim Integrated Products, Inc. retains all 00030 * ownership rights. 00031 * 00032 *************************************************************************** */ 00033 00034 /* Define to prevent redundant inclusion */ 00035 #ifndef _MXC_FLC_REGS_H_ 00036 #define _MXC_FLC_REGS_H_ 00037 00038 /* **** Includes **** */ 00039 #include <stdint.h> 00040 00041 #ifdef __cplusplus 00042 extern "C" { 00043 #endif 00044 00045 /// @cond 00046 /* 00047 If types are not defined elsewhere (CMSIS) define them here 00048 */ 00049 #ifndef __IO 00050 #define __IO volatile 00051 #endif 00052 #ifndef __I 00053 #define __I volatile const 00054 #endif 00055 #ifndef __O 00056 #define __O volatile 00057 #endif 00058 #ifndef __R 00059 #define __R volatile const 00060 #endif 00061 /// @endcond 00062 00063 /* **** Definitions **** */ 00064 /** 00065 * @defgroup flc_special_codes Flash Controller Codes/Keys. 00066 * @brief Required values to pass to the flash controller to perform restricted 00067 * operations. 00068 * @ingroup flc_registers 00069 * @{ 00070 */ 00071 #define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55) /**< Page Erase Code required to perform a page erase operation */ 00072 #define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA) /**< Mass Erase Code required to perform a page erase operation */ 00073 #define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2) /**< Unlock Code required to unlock the flash for erase and write functions */ 00074 /**@} end of flc_special_codes */ 00075 00076 /** 00077 * @defgroup flc_registers Registers 00078 * @brief Registers, Bit Masks, Bit Positions and Values for the FLC Peripheral Module. 00079 * @ingroup flc 00080 * @{ 00081 */ 00082 /* 00083 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit 00084 access to each register in module. 00085 */ 00086 00087 /** 00088 * Structure type to access the Flash Controller registers with direct 32-bit 00089 access to each. 00090 */ 00091 typedef struct { 00092 __IO uint32_t faddr; /**< <tt>\b 0x0000: </tt> FLC_FADDR Register - Flash Operation Address */ 00093 __IO uint32_t fckdiv; /**< <tt>\b 0x0004: </tt> FLC_FCKDIV Register - Flash Clock Pulse Divisor */ 00094 __IO uint32_t ctrl; /**< <tt>\b 0x0008: </tt> FLC_CTRL Register - Flash Control Register */ 00095 __R uint32_t rsv00C[6]; /**< <tt>\b 0x000C-0x0020:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ 00096 __IO uint32_t intr; /**< <tt>\b 0x0024: </tt> FLC_INTR Register - Flash Controller Interrupt Flags and Enable/Disable 0 */ 00097 __R uint32_t rsv028[2]; /**< <tt>\b 0x0028-0x002C:</tt> RESERVED */ 00098 __IO uint32_t fdata; /**< <tt>\b 0x0030: </tt> FLC_FDATA Register - Flash Operation Data Register */ 00099 __R uint32_t rsv034[7]; /**< <tt>\b 0x0034-0x004C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ 00100 __IO uint32_t perform; /**< <tt>\b 0x0050: </tt> FLC_PERFORM Register - Flash Performance Settings */ 00101 __IO uint32_t tacc; /**< <tt>\b 0x0054: </tt> FLC_TACC Register - Flash Read Cycle Config */ 00102 __IO uint32_t tprog; /**< <tt>\b 0x0058: </tt> FLC_TPROG Register - Flash Write Cycle Config */ 00103 __R uint32_t rsv05C[9]; /**< <tt>\b 0x005C-0x007C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ 00104 __IO uint32_t status; /**< <tt>\b 0x0080: </tt> FLC_STATUS Register - Security Status Flags */ 00105 __R uint32_t rsv084; /**< <tt>\b 0x0084: </tt> RESERVED \warning Do Not Modify Reserved Locations! */ 00106 __IO uint32_t security; /**< <tt>\b 0x0088: </tt> FLC_SECURITY Register - Flash Controller Security Settings */ 00107 __R uint32_t rsv08C[4]; /**< <tt>\b 0x008C-0x0098:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ 00108 __IO uint32_t bypass; /**< <tt>\b 0x009C: </tt> FLC_BYPASS Register - Status Flags for DSB Operations */ 00109 __R uint32_t rsv0A0[24]; /**< <tt>\b 0x00A0-0x00FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ 00110 __IO uint32_t user_option; /**< <tt>\b 0x0100: </tt> FLC_USER_OPTION Register - Used to set DSB Access code and Auto-Lock in info block */ 00111 __R uint32_t rsv104[15]; /**< <tt>\b 0x0104-0x013C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ 00112 __IO uint32_t ctrl2; /**< <tt>\b 0x0140: </tt> FLC_CTRL2 Register - Flash Control Register 2 */ 00113 __IO uint32_t intfl1; /**< <tt>\b 0x0144: </tt> FLC_INTFL1 Register - Interrupt Flags Register 1 */ 00114 __IO uint32_t inten1; /**< <tt>\b 0x0148: </tt> FLC_INTEN1 Register - Interrupt Enable/Disable Register 1 */ 00115 __R uint32_t rsv14C[9]; /**< <tt>\b 0x014C-0x016C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ 00116 __IO uint32_t bl_ctrl; /**< <tt>\b 0x0170: </tt> FLC_BL_CTRL Register - Bootloader Control Register */ 00117 __IO uint32_t twk; /**< <tt>\b 0x0174: </tt> FLC_TWK Register - PDM33 Register */ 00118 __R uint32_t rsv178; /**< <tt>\b 0x0178: </tt> RESERVED \warning Do Not Modify Reserved Locations! */ 00119 __IO uint32_t slm; /**< <tt>\b 0x017C: </tt> FLC_SLM Register - Sleep Mode Register */ 00120 __R uint32_t rsv180[32]; /**< <tt>\b 0x0180-0x01FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ 00121 __IO uint32_t disable_xr0; /**< <tt>\b 0x0200: </tt> FLC_DISABLE_XR0 Register - Disable Flash Page Exec/Read Register 0 */ 00122 __IO uint32_t disable_xr1; /**< <tt>\b 0x0204: </tt> FLC_DISABLE_XR1 Register - Disable Flash Page Exec/Read Register 1 */ 00123 __IO uint32_t disable_xr2; /**< <tt>\b 0x0208: </tt> FLC_DISABLE_XR2 Register - Disable Flash Page Exec/Read Register 2 */ 00124 __IO uint32_t disable_xr3; /**< <tt>\b 0x020C: </tt> FLC_DISABLE_XR3 Register - Disable Flash Page Exec/Read Register 3 */ 00125 __IO uint32_t disable_xr4; /**< <tt>\b 0x0210: </tt> FLC_DISABLE_XR4 Register - Disable Flash Page Exec/Read Register 4 */ 00126 __IO uint32_t disable_xr5; /**< <tt>\b 0x0214: </tt> FLC_DISABLE_XR5 Register - Disable Flash Page Exec/Read Register 5 */ 00127 __IO uint32_t disable_xr6; /**< <tt>\b 0x0218: </tt> FLC_DISABLE_XR6 Register - Disable Flash Page Exec/Read Register 6 */ 00128 __IO uint32_t disable_xr7; /**< <tt>\b 0x021C: </tt> FLC_DISABLE_XR7 Register - Disable Flash Page Exec/Read Register 7 */ 00129 __R uint32_t rsv220[56]; /**< <tt>\b 0x0220-0x02FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */ 00130 __IO uint32_t disable_we0; /**< <tt>\b 0x0300: </tt> FLC_DISABLE_WE0 Register - Disable Flash Page Write/Erase Register 0 */ 00131 __IO uint32_t disable_we1; /**< <tt>\b 0x0304: </tt> FLC_DISABLE_WE1 Register - Disable Flash Page Write/Erase Register 1 */ 00132 __IO uint32_t disable_we2; /**< <tt>\b 0x0308: </tt> FLC_DISABLE_WE2 Register - Disable Flash Page Write/Erase Register 2 */ 00133 __IO uint32_t disable_we3; /**< <tt>\b 0x030C: </tt> FLC_DISABLE_WE3 Register - Disable Flash Page Write/Erase Register 3 */ 00134 __IO uint32_t disable_we4; /**< <tt>\b 0x0310: </tt> FLC_DISABLE_WE4 Register - Disable Flash Page Write/Erase Register 4 */ 00135 __IO uint32_t disable_we5; /**< <tt>\b 0x0314: </tt> FLC_DISABLE_WE5 Register - Disable Flash Page Write/Erase Register 5 */ 00136 __IO uint32_t disable_we6; /**< <tt>\b 0x0318: </tt> FLC_DISABLE_WE6 Register - Disable Flash Page Write/Erase Register 6 */ 00137 __IO uint32_t disable_we7; /**< <tt>\b 0x031C: </tt> FLC_DISABLE_WE7 Register - Disable Flash Page Write/Erase Register 7 */ 00138 } mxc_flc_regs_t; 00139 /**@} end of group flc_registers */ 00140 /* 00141 Register offsets for module FLC. 00142 */ 00143 /** 00144 * @defgroup FLC_Register_Offsets Register Offsets 00145 * @ingroup flc_registers 00146 * @brief Flash Controller Register Offsets from the FLC Base Peripheral Address. 00147 * @{ 00148 */ 00149 #define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt>\b 0x0000</tt> */ 00150 #define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt>\b 0x0004</tt> */ 00151 #define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt>\b 0x0008</tt> */ 00152 #define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt>\b 0x0024</tt> */ 00153 #define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt>\b 0x0030</tt> */ 00154 #define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL) /**< Offset from FLC Base Address: <tt>\b 0x0050</tt> */ 00155 #define MXC_R_FLC_OFFS_TACC ((uint32_t)0x00000054UL) /**< Offset from FLC Base Address: <tt>\b 0x0054</tt> */ 00156 #define MXC_R_FLC_OFFS_TPROG ((uint32_t)0x00000058UL) /**< Offset from FLC Base Address: <tt>\b 0x0058</tt> */ 00157 #define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: <tt>\b 0x0080</tt> */ 00158 #define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: <tt>\b 0x0088</tt> */ 00159 #define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL) /**< Offset from FLC Base Address: <tt>\b 0x009C</tt> */ 00160 #define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL) /**< Offset from FLC Base Address: <tt>\b 0x0100</tt> */ 00161 #define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL) /**< Offset from FLC Base Address: <tt>\b 0x0140</tt> */ 00162 #define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL) /**< Offset from FLC Base Address: <tt>\b 0x0144</tt> */ 00163 #define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL) /**< Offset from FLC Base Address: <tt>\b 0x0148</tt> */ 00164 #define MXC_R_FLC_OFFS_BL_CTRL ((uint32_t)0x00000170UL) /**< Offset from FLC Base Address: <tt>\b 0x0170</tt> */ 00165 #define MXC_R_FLC_OFFS_TWK ((uint32_t)0x00000174UL) /**< Offset from FLC Base Address: <tt>\b 0x0174</tt> */ 00166 #define MXC_R_FLC_OFFS_SLM ((uint32_t)0x0000017CUL) /**< Offset from FLC Base Address: <tt>\b 0x017C</tt> */ 00167 #define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000200UL) /**< Offset from FLC Base Address: <tt>\b 0x0200</tt> */ 00168 #define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000204UL) /**< Offset from FLC Base Address: <tt>\b 0x0204</tt> */ 00169 #define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000208UL) /**< Offset from FLC Base Address: <tt>\b 0x0208</tt> */ 00170 #define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000020CUL) /**< Offset from FLC Base Address: <tt>\b 0x020C</tt> */ 00171 #define MXC_R_FLC_OFFS_DISABLE_XR4 ((uint32_t)0x00000210UL) /**< Offset from FLC Base Address: <tt>\b 0x0210</tt> */ 00172 #define MXC_R_FLC_OFFS_DISABLE_XR5 ((uint32_t)0x00000214UL) /**< Offset from FLC Base Address: <tt>\b 0x0214</tt> */ 00173 #define MXC_R_FLC_OFFS_DISABLE_XR6 ((uint32_t)0x00000218UL) /**< Offset from FLC Base Address: <tt>\b 0x0218</tt> */ 00174 #define MXC_R_FLC_OFFS_DISABLE_XR7 ((uint32_t)0x0000021CUL) /**< Offset from FLC Base Address: <tt>\b 0x021C</tt> */ 00175 #define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000300UL) /**< Offset from FLC Base Address: <tt>\b 0x0300</tt> */ 00176 #define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000304UL) /**< Offset from FLC Base Address: <tt>\b 0x0304</tt> */ 00177 #define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000308UL) /**< Offset from FLC Base Address: <tt>\b 0x0308</tt> */ 00178 #define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000030CUL) /**< Offset from FLC Base Address: <tt>\b 0x030C</tt> */ 00179 #define MXC_R_FLC_OFFS_DISABLE_WE4 ((uint32_t)0x00000310UL) /**< Offset from FLC Base Address: <tt>\b 0x0310</tt> */ 00180 #define MXC_R_FLC_OFFS_DISABLE_WE5 ((uint32_t)0x00000314UL) /**< Offset from FLC Base Address: <tt>\b 0x0314</tt> */ 00181 #define MXC_R_FLC_OFFS_DISABLE_WE6 ((uint32_t)0x00000318UL) /**< Offset from FLC Base Address: <tt>\b 0x0318</tt> */ 00182 #define MXC_R_FLC_OFFS_DISABLE_WE7 ((uint32_t)0x0000031CUL) /**< Offset from FLC Base Address: <tt>\b 0x031C</tt> */ 00183 /**@} end of group FLC_Register_Offsets */ 00184 /* 00185 Field positions and Masks for module FLC. 00186 */ 00187 /** 00188 * @defgroup FLC_FADDR_Register FLC_FADDR 00189 * @ingroup flc_registers 00190 * @brief Field Positions and Bit Masks for the FLC_FADDR register. 00191 * @{ 00192 */ 00193 #define MXC_F_FLC_FADDR_FADDR_POS 0 /**< FADDR Position */ 00194 #define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x003FFFFFUL << MXC_F_FLC_FADDR_FADDR_POS)) /**< FADDR Mask */ 00195 /**@} end of group FLC_FADDR */ 00196 /** 00197 * @defgroup FLC_FCKDIV_Register FLC_FCKDIV 00198 * @ingroup flc_registers 00199 * @brief Field Positions and Bit Masks for the FLC_FCKDIV register. 00200 * @{ 00201 */ 00202 #define MXC_F_FLC_FCKDIV_FCKDIV_POS /**< FCKDIV Position */ 00203 #define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000007FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS)) /**< FCKDIV Mask */ 00204 #define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS 16 /**< AUTO_FCKDIV_RESULT Position */ 00205 #define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS)) /**< AUTO_FCKDIV_RESULT Mask */ 00206 /**@} end of group FLC_FCKDIV */ 00207 /** 00208 * @defgroup FLC_CTRL_Register FLC_CTRL 00209 * @ingroup flc_registers 00210 * @brief Field Positions and Bit Masks for the FLC_CTRL register. 00211 * @{ 00212 */ 00213 #define MXC_F_FLC_CTRL_WRITE_POS 0 /**< WRITE Position */ 00214 #define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< WRITE Mask */ 00215 #define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< MASS_ERASE Position */ 00216 #define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< MASS_ERASE Mask */ 00217 #define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< PAGE_ERASE Position */ 00218 #define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< PAGE_ERASE Mask */ 00219 #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< ERASE_CODE Position */ 00220 #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< ERASE_CODE Mask */ 00221 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16 /**< INFO_BLOCK_UNLOCK Position */ 00222 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS)) /**< INFO_BLOCK_UNLOCK Mask */ 00223 #define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17 /**< WRITE_ENABLE Position */ 00224 #define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS)) /**< WRITE_ENABLE Mask */ 00225 #define MXC_F_FLC_CTRL_PENDING_POS 24 /**< PENDING Position */ 00226 #define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS)) /**< PENDING Mask */ 00227 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25 /**< INFO_BLOCK_VALID Position */ 00228 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS)) /**< INFO_BLOCK_VALID Mask */ 00229 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27 /**< AUTO_INCRE_MODE Position */ 00230 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS)) /**< AUTO_INCRE_MODE Mask */ 00231 #define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28 /**< FLSH_UNLOCK Position */ 00232 #define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS)) /**< FLSH_UNLOCK Mask */ 00233 /**@} end of group FLC_CTRL */ 00234 /** 00235 * @defgroup FLC_INTR_Register FLC_INTR 00236 * @ingroup flc_registers 00237 * @brief Field Positions and Bit Masks for the FLC_INTR register. 00238 * @{ 00239 */ 00240 #define MXC_F_FLC_INTR_FINISHED_IF_POS 0 /**< FINISHED_IF Position */ 00241 #define MXC_F_FLC_INTR_FINISHED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IF_POS)) /**< FINISHED_IF Mask */ 00242 #define MXC_F_FLC_INTR_FAILED_IF_POS 1 /**< FAILED_IF Position */ 00243 #define MXC_F_FLC_INTR_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IF_POS)) /**< FAILED_IF Mask */ 00244 #define MXC_F_FLC_INTR_FINISHED_IE_POS 8 /**< FINISHED_IE Position */ 00245 #define MXC_F_FLC_INTR_FINISHED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IE_POS)) /**< FINISHED_IE Mask */ 00246 #define MXC_F_FLC_INTR_FAILED_IE_POS 9 /**< FAILED_IE Position */ 00247 #define MXC_F_FLC_INTR_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IE_POS)) /**< FAILED_IE Mask */ 00248 #define MXC_F_FLC_INTR_FAIL_FLAGS_POS 16 /**< FAIL_FLAGS Position */ 00249 #define MXC_F_FLC_INTR_FAIL_FLAGS ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_INTR_FAIL_FLAGS_POS)) /**< FAIL_FLAGS Mask */ 00250 /**@} end of group FLC_INTR */ 00251 /** 00252 * @defgroup FLC_PERFORM_Register FLC_PERFORM 00253 * @ingroup flc_registers 00254 * @brief Field Positions and Bit Masks for the FLC_PERFORM register. 00255 * @{ 00256 */ 00257 #define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0 /**< DELAY_SE_EN Position */ 00258 #define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS)) /**< DELAY_SE_EN Mask */ 00259 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8 /**< FAST_READ_MODE_EN Position */ 00260 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS)) /**< FAST_READ_MODE_EN Mask */ 00261 #define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS 12 /**< EN_PREVENT_FAIL Position */ 00262 #define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS)) /**< EN_PREVENT_FAIL Mask */ 00263 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS 16 /**< EN_BACK2BACK_RDS Position */ 00264 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS)) /**< EN_BACK2BACK_RDS Mask */ 00265 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS 20 /**< EN_BACK2BACK_WRS Position */ 00266 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS)) /**< EN_BACK2BACK_WRS Mask */ 00267 #define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS 24 /**< EN_MERGE_GRAB_GNT Position */ 00268 #define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS)) /**< EN_MERGE_GRAB_GNT Mask */ 00269 #define MXC_F_FLC_PERFORM_AUTO_TACC_POS 28 /**< AUTO_TACC Position */ 00270 #define MXC_F_FLC_PERFORM_AUTO_TACC ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_TACC_POS)) /**< AUTO_TACC Mask */ 00271 #define MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS 29 /**< AUTO_CLKDIV Position */ 00272 #define MXC_F_FLC_PERFORM_AUTO_CLKDIV ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS)) /**< AUTO_CLKDIV Mask */ 00273 /**@} end of group FLC_PERFORM */ 00274 /** 00275 * @defgroup FLC_STATUS_Register FLC_STATUS 00276 * @ingroup flc_registers 00277 * @brief Field Positions and Bit Masks for the FLC_STATUS register. 00278 * @{ 00279 */ 00280 #define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS 0 /**< JTAG_LOCK_WINDOW Position */ 00281 #define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS)) /**< JTAG_LOCK_WINDOW Mask */ 00282 #define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS 1 /**< JTAG_LOCK_STATIC Position */ 00283 #define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS)) /**< JTAG_LOCK_STATIC Mask */ 00284 #define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3 /**< AUTO_LOCK Position */ 00285 #define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS)) /**< AUTO_LOCK Mask */ 00286 #define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS 29 /**< TRIM_UPDATE_DONE Position */ 00287 #define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */ 00288 #define MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS 30 /**< INFO_BLOCK_VALID Position */ 00289 #define MXC_F_FLC_STATUS_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS)) /**< INFO_BLOCK_VALID Mask */ 00290 /**@} end of group FLC_STATUS*/ 00291 /** 00292 * @defgroup FLC_SECURITY_Register FLC_SECURITY 00293 * @ingroup flc_registers 00294 * @brief Field Positions and Bit Masks for the FLC_SECURITY register. 00295 * @{ 00296 */ 00297 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0 /**< DEBUG_DISABLE Position */ 00298 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS)) /**< DEBUG_DISABLE Mask */ 00299 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8 /**< MASS_ERASE_LOCK Position */ 00300 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS)) /**< MASS_ERASE_LOCK Mask */ 00301 #define MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS 16 /**< DISABLE_AHB_WR Position */ 00302 #define MXC_F_FLC_SECURITY_DISABLE_AHB_WR ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS)) /**< DISABLE_AHB_WR Mask */ 00303 #define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS 24 /**< FLC_SETTINGS_LOCK Position */ 00304 #define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS)) /**< FLC_SETTINGS_LOCK Mask */ 00305 #define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 28 /**< SECURITY_LOCK Position */ 00306 #define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS)) /**< SECURITY_LOCK Mask */ 00307 /**@} end of group FLC_SECURITY */ 00308 /** 00309 * @defgroup FLC_BYPASS_Register FLC_BYPASS 00310 * @ingroup flc_registers 00311 * @brief Field Positions and Bit Masks for the FLC_BYPASS register. 00312 * @{ 00313 */ 00314 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0 /**< DESTRUCT_BYPASS_ERASE Position */ 00315 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS)) /**< DESTRUCT_BYPASS_ERASE Mask */ 00316 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1 /**< SUPERWIPE_ERASE Position */ 00317 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS)) /**< SUPERWIPE_ERASE Mask */ 00318 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2 /**< DESTRUCT_BYPASS_COMPLETE Position */ 00319 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS)) /**< DESTRUCT_BYPASS_COMPLETE Mask */ 00320 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3 /**< SUPERWIPE_COMPLETE Position */ 00321 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS)) /**< SUPERWIPE_COMPLETE Mask */ 00322 /**@} end of group FLC_BYPASS*/ 00323 /** 00324 * @defgroup FLC_CTRL2_Register FLC_CTRL2 00325 * @ingroup flc_registers 00326 * @brief Field Positions and Bit Masks for the FLC_CTRL2 register. 00327 * @{ 00328 */ 00329 #define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0 /**< FLASH_LVE Position */ 00330 #define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FLASH_LVE_POS)) /**< FLASH_LVE Mask */ 00331 #define MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS 1 /**< FRC_FCLK1_ON Position */ 00332 #define MXC_F_FLC_CTRL2_FRC_FCLK1_ON ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS)) /**< FRC_FCLK1_ON Mask */ 00333 #define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS 3 /**< EN_WRITE_ALL_ZEROES Position */ 00334 #define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS)) /**< EN_WRITE_ALL_ZEROES Mask */ 00335 #define MXC_F_FLC_CTRL2_EN_CHANGE_POS 4 /**< EN_CHANGE Position */ 00336 #define MXC_F_FLC_CTRL2_EN_CHANGE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_CHANGE_POS)) /**< EN_CHANGE Mask */ 00337 #define MXC_F_FLC_CTRL2_SLOW_CLK_POS 5 /**< SLOW_CLK Position */ 00338 #define MXC_F_FLC_CTRL2_SLOW_CLK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_SLOW_CLK_POS)) /**< SLOW_CLK Mask */ 00339 #define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS 6 /**< ENABLE_RAM_HRESP Position */ 00340 #define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS)) /**< ENABLE_RAM_HRESP Mask */ 00341 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8 /**< BYPASS_AHB_FAIL Position */ 00342 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS)) /**< BYPASS_AHB_FAIL Mask */ 00343 /**@} end of group FLC_CTRL2*/ 00344 /** 00345 * @defgroup FLC_INTFL1_Register FLC_INTFL1 00346 * @ingroup flc_registers 00347 * @brief Field Positions and Bit Masks for the FLC_INTFL1 register. 00348 * @{ 00349 */ 00350 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0 /**< SRAM_ADDR_WRAPPED Position */ 00351 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS)) /**< SRAM_ADDR_WRAPPED Mask */ 00352 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1 /**< INVALID_FLASH_ADDR Position */ 00353 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS)) /**< INVALID_FLASH_ADDR Mask */ 00354 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2 /**< FLASH_READ_LOCKED Position */ 00355 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS)) /**< FLASH_READ_LOCKED Mask */ 00356 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3 /**< TRIM_UPDATE_DONE Position */ 00357 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */ 00358 #define MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS 4 /**< FLC_STATE_DONE Position */ 00359 #define MXC_F_FLC_INTFL1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS)) /**< FLC_STATE_DONE Mask */ 00360 #define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS 5 /**< FLC_PROG_COMPLETE Position */ 00361 #define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS)) /**< FLC_PROG_COMPLETE Mask */ 00362 /**@} end of group FLC_INTFL1 */ 00363 /** 00364 * @defgroup FLC_INTEN1_Register FLC_INTEN1 00365 * @ingroup flc_registers 00366 * @brief Field Positions and Bit Masks for the FLC_INTEN1 register. 00367 * @{ 00368 */ 00369 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0 /**< SRAM_ADDR_WRAPPED Position */ 00370 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS)) /**< SRAM_ADDR_WRAPPED Mask */ 00371 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1 /**< INVALID_FLASH_ADDR Position */ 00372 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS)) /**< INVALID_FLASH_ADDR Mask */ 00373 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2 /**< FLASH_READ_LOCKED Position */ 00374 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS)) /**< FLASH_READ_LOCKED Mask */ 00375 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3 /**< TRIM_UPDATE_DONE Position */ 00376 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */ 00377 #define MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS 4 /**< FLC_STATE_DONE Position */ 00378 #define MXC_F_FLC_INTEN1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS)) /**< FLC_STATE_DONE Mask */ 00379 #define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS 5 /**< FLC_PROG_COMPLETE Position */ 00380 #define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS)) /**< FLC_PROG_COMPLETE Mask */ 00381 /**@} end of group FLC_INTEN1*/ 00382 00383 #ifdef __cplusplus 00384 } 00385 #endif 00386 00387 #endif /* _MXC_FLC_REGS_H_ */
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