max32620.h

00001 /*******************************************************************************
00002  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
00003  *
00004  * Permission is hereby granted, free of charge, to any person obtaining a
00005  * copy of this software and associated documentation files (the "Software"),
00006  * to deal in the Software without restriction, including without limitation
00007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
00008  * and/or sell copies of the Software, and to permit persons to whom the
00009  * Software is furnished to do so, subject to the following conditions:
00010  *
00011  * The above copyright notice and this permission notice shall be included
00012  * in all copies or substantial portions of the Software.
00013  *
00014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00016  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
00017  * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
00018  * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
00019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
00020  * OTHER DEALINGS IN THE SOFTWARE.
00021  *
00022  * Except as contained in this notice, the name of Maxim Integrated
00023  * Products, Inc. shall not be used except as stated in the Maxim Integrated
00024  * Products, Inc. Branding Policy.
00025  *
00026  * The mere transfer of this software does not imply any licenses
00027  * of trade secrets, proprietary technology, copyrights, patents,
00028  * trademarks, maskwork rights, or any other form of intellectual
00029  * property whatsoever. Maxim Integrated Products, Inc. retains all
00030  * ownership rights.
00031  *
00032  ******************************************************************************/
00033 
00034 #ifndef _MAX32620_H_
00035 #define _MAX32620_H_
00036 
00037 #include <stdint.h>
00038 
00039 #ifndef  FALSE
00040 #define  FALSE      (0)
00041 #endif
00042 
00043 #ifndef  TRUE
00044 #define  TRUE       (1)
00045 #endif
00046 
00047 #if !defined (__GNUC__)
00048 #define CMSIS_VECTAB_VIRTUAL
00049 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h"
00050 #endif /* !__GNUC__ */
00051 
00052 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
00053 #if defined ( __GNUC__ )
00054 #define __weak __attribute__((weak))
00055 
00056 #elif defined ( __CC_ARM)
00057 
00058 #define inline __inline
00059 #pragma anon_unions
00060 
00061 #endif
00062 
00063 typedef enum {
00064     NonMaskableInt_IRQn    = -14,
00065     HardFault_IRQn         = -13,
00066     MemoryManagement_IRQn  = -12,
00067     BusFault_IRQn          = -11,
00068     UsageFault_IRQn        = -10,
00069     SVCall_IRQn            = -5,
00070     DebugMonitor_IRQn      = -4,
00071     PendSV_IRQn            = -2,
00072     SysTick_IRQn           = -1,
00073 
00074     /* Device-specific interrupt sources (external to ARM core)                 */
00075     /*                      table entry number                                  */
00076     /*                      ||||                                                */
00077     /*                      ||||  table offset address                          */
00078     /*                      vvvv  vvvvvv                                        */
00079 
00080     CLKMAN_IRQn = 0,       /* 0x10 0x0040 CLKMAN                                */
00081     PWRMAN_IRQn,           /* 0x11 0x0044 PWRMAN                                */
00082     FLC_IRQn,              /* 0x12 0x0048 Flash Controller                      */
00083     RTC0_IRQn,             /* 0x13 0x004C RTC Counter match with Compare 0      */
00084     RTC1_IRQn,             /* 0x14 0x0050 RTC Counter match with Compare 1      */
00085     RTC2_IRQn,             /* 0x15 0x0054 RTC Prescaler interval compare match  */
00086     RTC3_IRQn,             /* 0x16 0x0058 RTC Overflow                          */
00087     PMU_IRQn,              /* 0x17 0x005C Peripheral Management Unit (PMU/DMA)  */
00088     USB_IRQn ,              /* 0x18 0x0060 USB                                   */
00089     AES_IRQn,              /* 0x19 0x0064 AES                                   */
00090     MAA_IRQn,              /* 0x1A 0x0068 MAA                                   */
00091     WDT0_IRQn,             /* 0x1B 0x006C Watchdog 0 timeout                    */
00092     WDT0_P_IRQn,           /* 0x1C 0x0070 Watchdog 0 pre-window (fed too early) */
00093     WDT1_IRQn,             /* 0x1D 0x0074 Watchdog 1 timeout                    */
00094     WDT1_P_IRQn,           /* 0x1E 0x0078 Watchdog 1 pre-window (fed too early) */
00095     GPIO_P0_IRQn,          /* 0x1F 0x007C GPIO Port 0                           */
00096     GPIO_P1_IRQn,          /* 0x20 0x0080 GPIO Port 1                           */
00097     GPIO_P2_IRQn,          /* 0x21 0x0084 GPIO Port 2                           */
00098     GPIO_P3_IRQn,          /* 0x22 0x0088 GPIO Port 3                           */
00099     GPIO_P4_IRQn,          /* 0x23 0x008C GPIO Port 4                           */
00100     GPIO_P5_IRQn,          /* 0x24 0x0090 GPIO Port 5                           */
00101     GPIO_P6_IRQn,          /* 0x25 0x0094 GPIO Port 6                           */
00102     TMR0_0_IRQn,           /* 0x26 0x0098 Timer 0 (32-bit, 16-bit #0)           */
00103     TMR0_1_IRQn,           /* 0x27 0x009C Timer 0         (16-bit #1)           */
00104     TMR1_0_IRQn,           /* 0x28 0x00A0 Timer 1 (32-bit, 16-bit #0)           */
00105     TMR1_1_IRQn,           /* 0x29 0x00A4 Timer 1         (16-bit #1)           */
00106     TMR2_0_IRQn,           /* 0x2A 0x00A8 Timer 2 (32-bit, 16-bit #0)           */
00107     TMR2_1_IRQn,           /* 0x2B 0x00AC Timer 2         (16-bit #1)           */
00108     TMR3_0_IRQn,           /* 0x2C 0x00B0 Timer 3 (32-bit, 16-bit #0)           */
00109     TMR3_1_IRQn,           /* 0x2D 0x00B4 Timer 3         (16-bit #1)           */
00110     TMR4_0_IRQn,           /* 0x2E 0x00B8 Timer 4 (32-bit, 16-bit #0)           */
00111     TMR4_1_IRQn,           /* 0x2F 0x00BC Timer 4         (16-bit #1)           */
00112     TMR5_0_IRQn,           /* 0x30 0x00C0 Timer 5 (32-bit, 16-bit #0)           */
00113     TMR5_1_IRQn,           /* 0x31 0x00C4 Timer 5         (16-bit #1)           */
00114     UART0_IRQn,            /* 0x32 0x00C8 UART 0                                */
00115     UART1_IRQn,            /* 0x33 0x00CC UART 1                                */
00116     UART2_IRQn,            /* 0x34 0x00D0 UART 2                                */
00117     UART3_IRQn ,            /* 0x35 0x00D4 UART 3                                */
00118     PT_IRQn,               /* 0x36 0x00D8 Pulse Trains                          */
00119     I2CM0_IRQn,            /* 0x37 0x00DC I2C Master 0                          */
00120     I2CM1_IRQn,            /* 0x38 0x00E0 I2C Master 1                          */
00121     I2CM2_IRQn,            /* 0x39 0x00E4 I2C Master 2                          */
00122     I2CS_IRQn,             /* 0x3A 0x00E8 I2C Slave                             */
00123     SPIM0_IRQn,            /* 0x3B 0x00EC SPI Master 0                          */
00124     SPIM1_IRQn,            /* 0x3C 0x00F0 SPI Master 1                          */
00125     SPIM2_IRQn,            /* 0x3D 0x00F4 SPI Master 2                          */
00126     SPIB_IRQn,             /* 0x3E 0x00F8 SPI Bridge                            */
00127     OWM_IRQn,              /* 0x3F 0x00FC 1-Wire Master                         */
00128     AFE_IRQn,              /* 0x40 0x0100 Analog Front End, ADC                 */
00129     SPIS_IRQn,             /* 0x41 0x0104 SPI Slave                             */
00130     GPIO_P7_IRQn,          /* 0x42 0x0108 GPIO Port 7                           */
00131     GPIO_P8_IRQn,          /* 0x43 0x010C GPIO Port 8                           */
00132     MXC_IRQ_EXT_COUNT,
00133 } IRQn_Type ;
00134 
00135 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
00136 
00137 
00138 /* ================================================================================ */
00139 /* ================      Processor and Core Peripheral Section     ================ */
00140 /* ================================================================================ */
00141 
00142 /* ----------------------  Configuration of the Cortex-M Processor and Core Peripherals  ---------------------- */
00143 #define __CM4_REV                 0x0100            /*!< Cortex-M4 Core Revision                                */
00144 #define __MPU_PRESENT                  0            /*!< MPU present or not                                     */
00145 #define __NVIC_PRIO_BITS               3            /*!< Number of Bits used for Priority Levels                */
00146 #define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used           */
00147 #define __FPU_PRESENT                  1            /*!< FPU present or not                                     */
00148 
00149 #include <core_cm4.h>                               /*!< Cortex-M4 processor and core peripherals               */
00150 #include "system_max32620.h"                        /*!< System Header                                          */
00151 
00152 
00153 /* ================================================================================ */
00154 /* ==================       Device Specific Memory Section       ================== */
00155 /* ================================================================================ */
00156 
00157 #define MXC_FLASH_MEM_BASE         0x00000000UL
00158 #define MXC_FLASH_PAGE_SIZE        0x00002000UL
00159 #define MXC_FLASH_FULL_MEM_SIZE    0x00200000UL
00160 #define MXC_SYS_MEM_BASE           0x20000000UL
00161 #define MXC_SRAM_FULL_MEM_SIZE     0x00040000UL
00162 #define MXC_EXT_FLASH_MEM_BASE     0x10000000UL
00163 
00164 /* ================================================================================ */
00165 /* ================       Device Specific Peripheral Section       ================ */
00166 /* ================================================================================ */
00167 
00168 
00169 /*
00170    Base addresses and configuration settings for all MAX32620 peripheral modules.
00171 */
00172 
00173 
00174 /*******************************************************************************/
00175 /*                                                     System Manager Settings */
00176 
00177 #define MXC_BASE_SYSMAN                  ((uint32_t)0x40000000UL)
00178 #define MXC_SYSMAN                       ((mxc_sysman_regs_t *)MXC_BASE_SYSMAN)
00179 
00180 
00181 
00182 /*******************************************************************************/
00183 /*                                                        System Clock Manager */
00184 
00185 #define MXC_BASE_CLKMAN                  ((uint32_t)0x40000400UL)
00186 #define MXC_CLKMAN                       ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
00187 
00188 
00189 
00190 /*******************************************************************************/
00191 /*                                                        System Power Manager */
00192 
00193 #define MXC_BASE_PWRMAN                  ((uint32_t)0x40000800UL)
00194 #define MXC_PWRMAN                       ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
00195 
00196 
00197 
00198 /*******************************************************************************/
00199 /*                                                             Real Time Clock */
00200 
00201 #define MXC_BASE_RTCTMR                  ((uint32_t)0x40000A00UL)
00202 #define MXC_RTCTMR                       ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
00203 #define MXC_BASE_RTCCFG                  ((uint32_t)0x40000A70UL)
00204 #define MXC_RTCCFG                       ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
00205 
00206 #define MXC_RTCTMR_GET_IRQ(i)            (IRQn_Type)(i == 0 ? RTC0_IRQn :   \
00207                                                      i == 1 ? RTC1_IRQn :   \
00208                                                      i == 2 ? RTC2_IRQn :   \
00209                                                      i == 3 ? RTC3_IRQn : 0)
00210 
00211 
00212 
00213 /*******************************************************************************/
00214 /*                                                             Power Sequencer */
00215 
00216 #define MXC_BASE_PWRSEQ                  ((uint32_t)0x40000A30UL)
00217 #define MXC_PWRSEQ                       ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
00218 
00219 
00220 
00221 /*******************************************************************************/
00222 /*                                                          System I/O Manager */
00223 
00224 #define MXC_BASE_IOMAN                   ((uint32_t)0x40000C00UL)
00225 #define MXC_IOMAN                        ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
00226 
00227 
00228 
00229 /*******************************************************************************/
00230 /*                                                       Shadow Trim Registers */
00231 
00232 #define MXC_BASE_TRIM                    ((uint32_t)0x40001000UL)
00233 #define MXC_TRIM                         ((mxc_trim_regs_t *)MXC_BASE_TRIM)
00234 
00235 
00236 
00237 /*******************************************************************************/
00238 /*                                                            Flash Controller */
00239 
00240 #define MXC_BASE_FLC                     ((uint32_t)0x40002000UL)
00241 #define MXC_FLC                          ((mxc_flc_regs_t *)MXC_BASE_FLC)
00242 
00243 #define MXC_FLC_PAGE_SIZE_SHIFT          (13)
00244 #define MXC_FLC_PAGE_SIZE                (1 << MXC_FLC_PAGE_SIZE_SHIFT)
00245 #define MXC_FLC_PAGE_ERASE_MSK           ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
00246 
00247 
00248 
00249 /*******************************************************************************/
00250 /*                                                           Instruction Cache */
00251 
00252 #define MXC_BASE_ICC                     ((uint32_t)0x40003000UL)
00253 #define MXC_ICC                          ((mxc_icc_regs_t *)MXC_BASE_ICC)
00254 
00255 
00256 
00257 /*******************************************************************************/
00258 /*                                                           SPI XIP Interface */
00259 
00260 #define MXC_BASE_SPIX                    ((uint32_t)0x40004000UL)
00261 #define MXC_SPIX                         ((mxc_spix_regs_t *)MXC_BASE_SPIX)
00262 
00263 
00264 
00265 /*******************************************************************************/
00266 /*                                                  Peripheral Management Unit */
00267 
00268 #define MXC_CFG_PMU_CHANNELS             (6)
00269 
00270 #define MXC_BASE_PMU0                    ((uint32_t)0x40005000UL)
00271 #define MXC_PMU0                         ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
00272 #define MXC_BASE_PMU1                    ((uint32_t)0x40005020UL)
00273 #define MXC_PMU1                         ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
00274 #define MXC_BASE_PMU2                    ((uint32_t)0x40005040UL)
00275 #define MXC_PMU2                         ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
00276 #define MXC_BASE_PMU3                    ((uint32_t)0x40005060UL)
00277 #define MXC_PMU3                         ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
00278 #define MXC_BASE_PMU4                    ((uint32_t)0x40005080UL)
00279 #define MXC_PMU4                         ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
00280 #define MXC_BASE_PMU5                    ((uint32_t)0x400050A0UL)
00281 #define MXC_PMU5                         ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
00282 
00283 #define MXC_PMU_GET_BASE(i)              ((i) == 0  ? MXC_BASE_PMU0 :          \
00284                                           (i) == 1  ? MXC_BASE_PMU1 :          \
00285                                           (i) == 2  ? MXC_BASE_PMU2 :          \
00286                                           (i) == 3  ? MXC_BASE_PMU3 :          \
00287                                           (i) == 4  ? MXC_BASE_PMU4 :          \
00288                                           (i) == 5  ? MXC_BASE_PMU5 : 0)
00289 
00290 #define MXC_PMU_GET_PMU(i)               ((i) == 0 ? MXC_PMU0 :                \
00291                                           (i) == 1 ? MXC_PMU1 :                \
00292                                           (i) == 2 ? MXC_PMU2 :                \
00293                                           (i) == 3 ? MXC_PMU3 :                \
00294                                           (i) == 4 ? MXC_PMU4 :                \
00295                                           (i) == 5 ? MXC_PMU5 : 0)
00296 
00297 #define MXC_PMU_GET_IDX(p)               ((p) == MXC_PMU0 ? 0 :                \
00298                                           (p) == MXC_PMU1 ? 1 :                \
00299                                           (p) == MXC_PMU2 ? 2 :                \
00300                                           (p) == MXC_PMU3 ? 3 :                \
00301                                           (p) == MXC_PMU4 ? 4 :                \
00302                                           (p) == MXC_PMU5 ? 5 : -1)
00303 
00304 /*******************************************************************************/
00305 /*                                                       USB Device Controller */
00306 
00307 #define MXC_BASE_USB                     ((uint32_t)0x40100000UL)
00308 #define MXC_USB                          ((mxc_usb_regs_t *)MXC_BASE_USB)
00309 
00310 #define MXC_USB_MAX_PACKET               (64)
00311 #define MXC_USB_NUM_EP                   (8)
00312 
00313 
00314 
00315 /*******************************************************************************/
00316 /*                                                        CRC-16/CRC-32 Engine */
00317 
00318 #define MXC_BASE_CRC                     ((uint32_t)0x40006000UL)
00319 #define MXC_CRC                          ((mxc_crc_regs_t *)MXC_BASE_CRC)
00320 #define MXC_BASE_CRC_DATA                ((uint32_t)0x40101000UL)
00321 #define MXC_CRC_DATA                     ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
00322 
00323 /*******************************************************************************/
00324 /*                                       Pseudo-random number generator (PRNG) */
00325 
00326 #define MXC_BASE_PRNG                     ((uint32_t)0x40007000UL)
00327 #define MXC_PRNG                          ((mxc_prng_regs_t *)MXC_BASE_PRNG)
00328 
00329 /*******************************************************************************/
00330 /*                                                    AES Cryptographic Engine */
00331 
00332 #define MXC_BASE_AES                     ((uint32_t)0x40007400UL)
00333 #define MXC_AES                          ((mxc_aes_regs_t *)MXC_BASE_AES)
00334 #define MXC_BASE_AES_MEM                 ((uint32_t)0x40102000UL)
00335 #define MXC_AES_MEM                      ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
00336 
00337 /*******************************************************************************/
00338 /*                                                    MAA Cryptographic Engine */
00339 
00340 #define MXC_BASE_MAA                     ((uint32_t)0x40007800UL)
00341 #define MXC_MAA                          ((mxc_maa_regs_t *)MXC_BASE_MAA)
00342 #define MXC_BASE_MAA_MEM                 ((uint32_t)0x40102800UL)
00343 #define MXC_MAA_MEM                      ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
00344 
00345 /*******************************************************************************/
00346 /*                                                 Trust Protection Unit (TPU) */
00347 
00348 #define MXC_BASE_TPU                     ((uint32_t)0x40007000UL)
00349 #define MXC_TPU                          ((mxc_tpu_regs_t *)MXC_BASE_TPU)
00350 #define MXC_BASE_TPU_TSR                 ((uint32_t)0x40007C00UL)
00351 #define MXC_TPU_TSR                      ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
00352 
00353 /*******************************************************************************/
00354 /*                                                             Watchdog Timers */
00355 
00356 #define MXC_CFG_WDT_INSTANCES            (2)
00357 
00358 #define MXC_BASE_WDT0                    ((uint32_t)0x40008000UL)
00359 #define MXC_WDT0                         ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
00360 #define MXC_BASE_WDT1                    ((uint32_t)0x40009000UL)
00361 #define MXC_WDT1                         ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
00362 
00363 #define MXC_WDT_GET_IRQ(i)               (IRQn_Type)((i) == 0 ? WDT0_IRQn :    \
00364                                           (i) == 1 ? WDT1_IRQn : 0)
00365 
00366 #define MXC_WDT_GET_IRQ_P(i)             (IRQn_Type)((i) == 0 ? WDT0_P_IRQn :  \
00367                                           (i) == 1 ? WDT1_P_IRQn : 0)
00368 
00369 #define MXC_WDT_GET_BASE(i)              ((i) == 0 ? MXC_BASE_WDT0 :           \
00370                                           (i) == 1 ? MXC_BASE_WDT1 : 0)
00371 
00372 #define MXC_WDT_GET_WDT(i)               ((i) == 0 ? MXC_WDT0 :                \
00373                                           (i) == 1 ? MXC_WDT1 : 0)
00374 
00375 #define MXC_WDT_GET_IDX(i)               ((i) == MXC_WDT0 ? 0:                 \
00376                                           (i) == MXC_WDT1 ? 1: -1)
00377 
00378 
00379 /*******************************************************************************/
00380 /*                                                    Always-On Watchdog Timer */
00381 
00382 #define MXC_BASE_WDT2                    ((uint32_t)0x40007C60UL)
00383 #define MXC_WDT2                         ((mxc_wdt2_regs_t *)MXC_BASE_WDT2)
00384 
00385 
00386 
00387 /*******************************************************************************/
00388 /*                                            General Purpose I/O Ports (GPIO) */
00389 
00390 #define MXC_GPIO_NUM_PORTS               (7)
00391 #define MXC_GPIO_MAX_PINS_PER_PORT       (8)
00392 
00393 #define MXC_BASE_GPIO                    ((uint32_t)0x4000A000UL)
00394 #define MXC_GPIO                         ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
00395 
00396 #define MXC_GPIO_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? GPIO_P0_IRQn :  \
00397                                           (i) == 1 ? GPIO_P1_IRQn :             \
00398                                           (i) == 2 ? GPIO_P2_IRQn :             \
00399                                           (i) == 3 ? GPIO_P3_IRQn :             \
00400                                           (i) == 4 ? GPIO_P4_IRQn :             \
00401                                           (i) == 5 ? GPIO_P5_IRQn :             \
00402                                           (i) == 6 ? GPIO_P6_IRQn :             \
00403                                           (i) == 7 ? GPIO_P7_IRQn :             \
00404                                           (i) == 8 ? GPIO_P8_IRQn : 0)
00405 
00406 
00407 
00408 /*******************************************************************************/
00409 /*                                                    16/32 bit Timer/Counters */
00410 
00411 #define MXC_CFG_TMR_INSTANCES            (6)
00412 
00413 #define MXC_BASE_TMR0                    ((uint32_t)0x4000B000UL)
00414 #define MXC_TMR0                         ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
00415 #define MXC_BASE_TMR1                    ((uint32_t)0x4000C000UL)
00416 #define MXC_TMR1                         ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
00417 #define MXC_BASE_TMR2                    ((uint32_t)0x4000D000UL)
00418 #define MXC_TMR2                         ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
00419 #define MXC_BASE_TMR3                    ((uint32_t)0x4000E000UL)
00420 #define MXC_TMR3                         ((mxc_tmr_regs_t *)MXC_BASE_TMR3)
00421 #define MXC_BASE_TMR4                    ((uint32_t)0x4000F000UL)
00422 #define MXC_TMR4                         ((mxc_tmr_regs_t *)MXC_BASE_TMR4)
00423 #define MXC_BASE_TMR5                    ((uint32_t)0x40010000UL)
00424 #define MXC_TMR5                         ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
00425 
00426 #define MXC_TMR_GET_IRQ_32(i)            (IRQn_Type)((i) == 0 ? TMR0_0_IRQn :     \
00427                                           (i) == 1 ? TMR1_0_IRQn :     \
00428                                           (i) == 2 ? TMR2_0_IRQn :     \
00429                                           (i) == 3 ? TMR3_0_IRQn :     \
00430                                           (i) == 4 ? TMR4_0_IRQn :     \
00431                                           (i) == 5 ? TMR5_0_IRQn : 0)
00432 
00433 #define MXC_TMR_GET_IRQ_16(i)            (IRQn_Type)((i) == 0  ? TMR0_0_IRQn :    \
00434                                           (i) == 1  ? TMR1_0_IRQn :    \
00435                                           (i) == 2  ? TMR2_0_IRQn :    \
00436                                           (i) == 3  ? TMR3_0_IRQn :    \
00437                                           (i) == 4  ? TMR4_0_IRQn :    \
00438                                           (i) == 5  ? TMR5_0_IRQn :    \
00439                                           (i) == 6  ? TMR0_1_IRQn :    \
00440                                           (i) == 7  ? TMR1_1_IRQn :    \
00441                                           (i) == 8  ? TMR2_1_IRQn :    \
00442                                           (i) == 9  ? TMR3_1_IRQn :    \
00443                                           (i) == 10 ? TMR4_1_IRQn :    \
00444                                           (i) == 11 ? TMR5_1_IRQn : 0)
00445 
00446 #define MXC_TMR_GET_BASE(i)              ((i) == 0 ? MXC_BASE_TMR0 :   \
00447                                           (i) == 1 ? MXC_BASE_TMR1 :   \
00448                                           (i) == 2 ? MXC_BASE_TMR2 :   \
00449                                           (i) == 3 ? MXC_BASE_TMR3 :   \
00450                                           (i) == 4 ? MXC_BASE_TMR4 :   \
00451                                           (i) == 5 ? MXC_BASE_TMR5 : 0)
00452 
00453 #define MXC_TMR_GET_TMR(i)               ((i) == 0 ? MXC_TMR0 :        \
00454                                           (i) == 1 ? MXC_TMR1 :        \
00455                                           (i) == 2 ? MXC_TMR2 :        \
00456                                           (i) == 3 ? MXC_TMR3 :        \
00457                                           (i) == 4 ? MXC_TMR4 :        \
00458                                           (i) == 5 ? MXC_TMR5 : 0)
00459 
00460 #define MXC_TMR_GET_IDX(p)               ((p) == MXC_TMR0 ? 0 :        \
00461                                           (p) == MXC_TMR1 ? 1 :        \
00462                                           (p) == MXC_TMR2 ? 2 :        \
00463                                           (p) == MXC_TMR3 ? 3 :        \
00464                                           (p) == MXC_TMR4 ? 4 :        \
00465                                           (p) == MXC_TMR5 ? 5 : -1)
00466 
00467 
00468 
00469 
00470 /*******************************************************************************/
00471 /*                                                      Pulse Train Generation */
00472 
00473 #define MXC_CFG_PT_INSTANCES             (16)
00474 
00475 #define MXC_BASE_PTG                     ((uint32_t)0x40011000UL)
00476 #define MXC_PTG                          ((mxc_ptg_regs_t *)MXC_BASE_PTG)
00477 #define MXC_BASE_PT0                     ((uint32_t)0x40011020UL)
00478 #define MXC_PT0                          ((mxc_pt_regs_t *)MXC_BASE_PT0)
00479 #define MXC_BASE_PT1                     ((uint32_t)0x40011040UL)
00480 #define MXC_PT1                          ((mxc_pt_regs_t *)MXC_BASE_PT1)
00481 #define MXC_BASE_PT2                     ((uint32_t)0x40011060UL)
00482 #define MXC_PT2                          ((mxc_pt_regs_t *)MXC_BASE_PT2)
00483 #define MXC_BASE_PT3                     ((uint32_t)0x40011080UL)
00484 #define MXC_PT3                          ((mxc_pt_regs_t *)MXC_BASE_PT3)
00485 #define MXC_BASE_PT4                     ((uint32_t)0x400110A0UL)
00486 #define MXC_PT4                          ((mxc_pt_regs_t *)MXC_BASE_PT4)
00487 #define MXC_BASE_PT5                     ((uint32_t)0x400110C0UL)
00488 #define MXC_PT5                          ((mxc_pt_regs_t *)MXC_BASE_PT5)
00489 #define MXC_BASE_PT6                     ((uint32_t)0x400110E0UL)
00490 #define MXC_PT6                          ((mxc_pt_regs_t *)MXC_BASE_PT6)
00491 #define MXC_BASE_PT7                     ((uint32_t)0x40011100UL)
00492 #define MXC_PT7                          ((mxc_pt_regs_t *)MXC_BASE_PT7)
00493 #define MXC_BASE_PT8                     ((uint32_t)0x40011120UL)
00494 #define MXC_PT8                          ((mxc_pt_regs_t *)MXC_BASE_PT8)
00495 #define MXC_BASE_PT9                     ((uint32_t)0x40011140UL)
00496 #define MXC_PT9                          ((mxc_pt_regs_t *)MXC_BASE_PT9)
00497 #define MXC_BASE_PT10                    ((uint32_t)0x40011160UL)
00498 #define MXC_PT10                         ((mxc_pt_regs_t *)MXC_BASE_PT10)
00499 #define MXC_BASE_PT11                    ((uint32_t)0x40011180UL)
00500 #define MXC_PT11                         ((mxc_pt_regs_t *)MXC_BASE_PT11)
00501 #define MXC_BASE_PT12                    ((uint32_t)0x400111A0UL)
00502 #define MXC_PT12                         ((mxc_pt_regs_t *)MXC_BASE_PT12)
00503 #define MXC_BASE_PT13                    ((uint32_t)0x400111C0UL)
00504 #define MXC_PT13                         ((mxc_pt_regs_t *)MXC_BASE_PT13)
00505 #define MXC_BASE_PT14                    ((uint32_t)0x400111E0UL)
00506 #define MXC_PT14                         ((mxc_pt_regs_t *)MXC_BASE_PT14)
00507 #define MXC_BASE_PT15                    ((uint32_t)0x40011200UL)
00508 #define MXC_PT15                         ((mxc_pt_regs_t *)MXC_BASE_PT15)
00509 
00510 #define MXC_PT_GET_BASE(i)               ((i) == 0  ? MXC_BASE_PT0  :           \
00511                                           (i) == 1  ? MXC_BASE_PT1  :           \
00512                                           (i) == 2  ? MXC_BASE_PT2  :           \
00513                                           (i) == 3  ? MXC_BASE_PT3  :           \
00514                                           (i) == 4  ? MXC_BASE_PT4  :           \
00515                                           (i) == 5  ? MXC_BASE_PT5  :           \
00516                                           (i) == 6  ? MXC_BASE_PT6  :           \
00517                                           (i) == 7  ? MXC_BASE_PT7  :           \
00518                                           (i) == 8  ? MXC_BASE_PT8  :           \
00519                                           (i) == 9  ? MXC_BASE_PT9  :           \
00520                                           (i) == 10 ? MXC_BASE_PT10 :           \
00521                                           (i) == 11 ? MXC_BASE_PT11 :           \
00522                                           (i) == 12 ? MXC_BASE_PT12 :           \
00523                                           (i) == 13 ? MXC_BASE_PT13 :           \
00524                                           (i) == 14 ? MXC_BASE_PT14 :           \
00525                                           (i) == 15 ? MXC_BASE_PT15 : 0)
00526 
00527 #define MXC_PT_GET_PT(i)                 ((i) == 0  ? MXC_PT0  :                \
00528                                           (i) == 1  ? MXC_PT1  :                \
00529                                           (i) == 2  ? MXC_PT2  :                \
00530                                           (i) == 3  ? MXC_PT3  :                \
00531                                           (i) == 4  ? MXC_PT4  :                \
00532                                           (i) == 5  ? MXC_PT5  :                \
00533                                           (i) == 6  ? MXC_PT6  :                \
00534                                           (i) == 7  ? MXC_PT7  :                \
00535                                           (i) == 8  ? MXC_PT8  :                \
00536                                           (i) == 9  ? MXC_PT9  :                \
00537                                           (i) == 10 ? MXC_PT10 :                \
00538                                           (i) == 11 ? MXC_PT11 :                \
00539                                           (i) == 12 ? MXC_PT12 :                \
00540                                           (i) == 13 ? MXC_PT13 :                \
00541                                           (i) == 14 ? MXC_PT14 :                \
00542                                           (i) == 15 ? MXC_PT15 : 0)
00543 
00544 #define MXC_PT_GET_IDX(p)                ((p) == MXC_PT0  ? 0  :                \
00545                                           (p) == MXC_PT1  ? 1  :                \
00546                                           (p) == MXC_PT2  ? 2  :                \
00547                                           (p) == MXC_PT3  ? 3  :                \
00548                                           (p) == MXC_PT4  ? 4  :                \
00549                                           (p) == MXC_PT5  ? 5  :                \
00550                                           (p) == MXC_PT6  ? 6  :                \
00551                                           (p) == MXC_PT7  ? 7  :                \
00552                                           (p) == MXC_PT8  ? 8  :                \
00553                                           (p) == MXC_PT9  ? 9  :                \
00554                                           (p) == MXC_PT10 ? 10 :                \
00555                                           (p) == MXC_PT11 ? 11 :                \
00556                                           (p) == MXC_PT12 ? 12 :                \
00557                                           (p) == MXC_PT13 ? 13 :                \
00558                                           (p) == MXC_PT14 ? 14 :                \
00559                                           (p) == MXC_PT15 ? 15 : -1)
00560 
00561 
00562 
00563 /*******************************************************************************/
00564 /*                                                UART / Serial Port Interface */
00565 
00566 #define MXC_CFG_UART_INSTANCES           (4)
00567 #define MXC_UART_FIFO_DEPTH              (32)
00568 
00569 #define MXC_BASE_UART0                   ((uint32_t)0x40012000UL)
00570 #define MXC_UART0                        ((mxc_uart_regs_t *)MXC_BASE_UART0)
00571 #define MXC_BASE_UART1                   ((uint32_t)0x40013000UL)
00572 #define MXC_UART1                        ((mxc_uart_regs_t *)MXC_BASE_UART1)
00573 #define MXC_BASE_UART2                   ((uint32_t)0x40014000UL)
00574 #define MXC_UART2                        ((mxc_uart_regs_t *)MXC_BASE_UART2)
00575 #define MXC_BASE_UART3                   ((uint32_t)0x40015000UL)
00576 #define MXC_UART3                        ((mxc_uart_regs_t *)MXC_BASE_UART3)
00577 #define MXC_BASE_UART0_FIFO              ((uint32_t)0x40103000UL)
00578 #define MXC_UART0_FIFO                   ((mxc_uart_fifo_regs_t *)MXC_BASE_UART0_FIFO)
00579 #define MXC_BASE_UART1_FIFO              ((uint32_t)0x40104000UL)
00580 #define MXC_UART1_FIFO                   ((mxc_uart_fifo_regs_t *)MXC_BASE_UART1_FIFO)
00581 #define MXC_BASE_UART2_FIFO              ((uint32_t)0x40105000UL)
00582 #define MXC_UART2_FIFO                   ((mxc_uart_fifo_regs_t *)MXC_BASE_UART2_FIFO)
00583 #define MXC_BASE_UART3_FIFO              ((uint32_t)0x40106000UL)
00584 #define MXC_UART3_FIFO                   ((mxc_uart_fifo_regs_t *)MXC_BASE_UART3_FIFO)
00585 
00586 #define MXC_UART_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? UART0_IRQn :  \
00587                                           (i) == 1 ? UART1_IRQn :             \
00588                                           (i) == 2 ? UART2_IRQn :             \
00589                                           (i) == 3 ? UART3_IRQn : 0)
00590 
00591 #define MXC_UART_GET_BASE(i)             ((i) == 0 ? MXC_BASE_UART0 :         \
00592                                           (i) == 1 ? MXC_BASE_UART1 :         \
00593                                           (i) == 2 ? MXC_BASE_UART2 :         \
00594                                           (i) == 3 ? MXC_BASE_UART3 : 0)
00595 
00596 #define MXC_UART_GET_UART(i)             ((i) == 0 ? MXC_UART0 :              \
00597                                           (i) == 1 ? MXC_UART1 :              \
00598                                           (i) == 2 ? MXC_UART2 :              \
00599                                           (i) == 3 ? MXC_UART3 : 0)
00600 
00601 #define MXC_UART_GET_IDX(p)              ((p) == MXC_UART0 ? 0 :              \
00602                                           (p) == MXC_UART1 ? 1 :              \
00603                                           (p) == MXC_UART2 ? 2 :              \
00604                                           (p) == MXC_UART3 ? 3 : -1)
00605 
00606 #define MXC_UART_GET_BASE_FIFO(i)        ((i) == 0 ? MXC_BASE_UART0_FIFO :    \
00607                                           (i) == 1 ? MXC_BASE_UART1_FIFO :    \
00608                                           (i) == 2 ? MXC_BASE_UART2_FIFO :    \
00609                                           (i) == 3 ? MXC_BASE_UART3_FIFO : 0)
00610 
00611 #define MXC_UART_GET_FIFO(i)             ((i) == 0 ? MXC_UART0_FIFO :         \
00612                                           (i) == 1 ? MXC_UART1_FIFO :         \
00613                                           (i) == 2 ? MXC_UART2_FIFO :         \
00614                                           (i) == 3 ? MXC_UART3_FIFO : 0)
00615 
00616 
00617 
00618 /*******************************************************************************/
00619 /*                                                        I2C Master Interface */
00620 
00621 #define MXC_CFG_I2CM_INSTANCES           (3)
00622 #define MXC_I2CM_FIFO_DEPTH              (8)
00623 
00624 #define MXC_BASE_I2CM0                   ((uint32_t)0x40016000UL)
00625 #define MXC_I2CM0                        ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
00626 #define MXC_BASE_I2CM1                   ((uint32_t)0x40017000UL)
00627 #define MXC_I2CM1                        ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
00628 #define MXC_BASE_I2CM2                   ((uint32_t)0x40018000UL)
00629 #define MXC_I2CM2                        ((mxc_i2cm_regs_t *)MXC_BASE_I2CM2)
00630 #define MXC_BASE_I2CM0_FIFO              ((uint32_t)0x40107000UL)
00631 #define MXC_I2CM0_FIFO                   ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM0_FIFO)
00632 #define MXC_BASE_I2CM1_FIFO              ((uint32_t)0x40108000UL)
00633 #define MXC_I2CM1_FIFO                   ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM1_FIFO)
00634 #define MXC_BASE_I2CM2_FIFO              ((uint32_t)0x40109000UL)
00635 #define MXC_I2CM2_FIFO                   ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM2_FIFO)
00636 
00637 #define MXC_I2CM_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? I2CM0_IRQn :   \
00638                                           (i) == 1 ? I2CM1_IRQn :              \
00639                                           (i) == 2 ? I2CM2_IRQn : 0)
00640 
00641 #define MXC_I2CM_GET_BASE(i)             ((i) == 0 ? MXC_BASE_I2CM0 :          \
00642                                           (i) == 1 ? MXC_BASE_I2CM1 :          \
00643                                           (i) == 2 ? MXC_BASE_I2CM2 : 0)
00644 
00645 #define MXC_I2CM_GET_I2CM(i)             ((i) == 0 ? MXC_I2CM0 :               \
00646                                           (i) == 1 ? MXC_I2CM1 :               \
00647                                           (i) == 2 ? MXC_I2CM2 : 0)
00648 
00649 #define MXC_I2CM_GET_IDX(p)              ((p) == MXC_I2CM0 ? 0 :               \
00650                                           (p) == MXC_I2CM1 ? 1 :               \
00651                                           (p) == MXC_I2CM2 ? 2 : -1)
00652 
00653 #define MXC_I2CM_GET_BASE_FIFO(i)        ((i) == 0 ? MXC_BASE_I2CM0_FIFO :     \
00654                                           (i) == 1 ? MXC_BASE_I2CM1_FIFO :     \
00655                                           (i) == 2 ? MXC_BASE_I2CM2_FIFO : 0)
00656 
00657 #define MXC_I2CM_GET_FIFO(i)             ((i) == 0 ? MXC_I2CM0_FIFO :          \
00658                                           (i) == 1 ? MXC_I2CM1_FIFO :          \
00659                                           (i) == 2 ? MXC_I2CM2_FIFO : 0)
00660 
00661 
00662 
00663 /*******************************************************************************/
00664 /*                                          I2C Slave Interface (Mailbox type) */
00665 
00666 #define MXC_CFG_I2CS_INSTANCES           (1)
00667 #define MXC_CFG_I2CS_BUFFER_SIZE         (32)
00668 
00669 #define MXC_BASE_I2CS                    ((uint32_t)0x40019000UL)
00670 #define MXC_I2CS                         ((mxc_i2cs_regs_t *)MXC_BASE_I2CS)
00671 
00672 #define MXC_I2CS_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? I2CS_IRQn : 0)
00673 
00674 #define MXC_I2CS_GET_BASE(i)             ((i) == 0 ? MXC_BASE_I2CS : 0)
00675 
00676 #define MXC_I2CS_GET_I2CS(i)             ((i) == 0 ? MXC_I2CS : 0)
00677 
00678 #define MXC_I2CS_GET_IDX(p)              ((p) == MXC_I2CS ? 0 : -1)
00679 
00680 /*******************************************************************************/
00681 /*                                                        SPI Master Interface */
00682 
00683 #define MXC_CFG_SPIM_INSTANCES           (3)
00684 #define MXC_CFG_SPIM_FIFO_DEPTH          (16)
00685 
00686 #define MXC_BASE_SPIM0                   ((uint32_t)0x4001A000UL)
00687 #define MXC_SPIM0                        ((mxc_spim_regs_t *)MXC_BASE_SPIM0)
00688 #define MXC_BASE_SPIM1                   ((uint32_t)0x4001B000UL)
00689 #define MXC_SPIM1                        ((mxc_spim_regs_t *)MXC_BASE_SPIM1)
00690 #define MXC_BASE_SPIM2                   ((uint32_t)0x4001C000UL)
00691 #define MXC_SPIM2                        ((mxc_spim_regs_t *)MXC_BASE_SPIM2)
00692 #define MXC_BASE_SPIM0_FIFO              ((uint32_t)0x4010A000UL)
00693 #define MXC_SPIM0_FIFO                   ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM0_FIFO)
00694 #define MXC_BASE_SPIM1_FIFO              ((uint32_t)0x4010B000UL)
00695 #define MXC_SPIM1_FIFO                   ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM1_FIFO)
00696 #define MXC_BASE_SPIM2_FIFO              ((uint32_t)0x4010C000UL)
00697 #define MXC_SPIM2_FIFO                   ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM2_FIFO)
00698 
00699 #define MXC_SPIM_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? SPIM0_IRQn :  \
00700                                           (i) == 1 ? SPIM1_IRQn :             \
00701                                           (i) == 2 ? SPIM2_IRQn : 0)
00702 
00703 #define MXC_SPIM_GET_BASE(i)             ((i) == 0 ? MXC_BASE_SPIM0 :         \
00704                                           (i) == 1 ? MXC_BASE_SPIM1 :         \
00705                                           (i) == 2 ? MXC_BASE_SPIM2 : 0)
00706 
00707 #define MXC_SPIM_GET_SPIM(i)             ((i) == 0 ? MXC_SPIM0 :              \
00708                                           (i) == 1 ? MXC_SPIM1 :              \
00709                                           (i) == 2 ? MXC_SPIM2 : 0)
00710 
00711 #define MXC_SPIM_GET_IDX(p)              ((p) == MXC_SPIM0 ? 0 :              \
00712                                           (p) == MXC_SPIM1 ? 1 :              \
00713                                           (p) == MXC_SPIM2 ? 2 : -1)
00714 
00715 #define MXC_SPIM_GET_BASE_FIFO(i)        ((i) == 0 ? MXC_BASE_SPIM0_FIFO :    \
00716                                           (i) == 1 ? MXC_BASE_SPIM1_FIFO :    \
00717                                           (i) == 2 ? MXC_BASE_SPIM2_FIFO : 0)
00718 
00719 #define MXC_SPIM_GET_SPIM_FIFO(i)        ((i) == 0 ? MXC_SPIM0_FIFO :         \
00720                                           (i) == 1 ? MXC_SPIM1_FIFO :         \
00721                                           (i) == 2 ? MXC_SPIM2_FIFO : 0)
00722 
00723 
00724 
00725 /*******************************************************************************/
00726 /*                                                     1-Wire Master Interface */
00727 
00728 #define MXC_CFG_OWM_INSTANCES            (1)
00729 
00730 #define MXC_BASE_OWM                     ((uint32_t)0x4001E000UL)
00731 #define MXC_OWM                          ((mxc_owm_regs_t *)MXC_BASE_OWM)
00732 
00733 #define MXC_OWM_GET_IRQ(i)               (IRQn_Type)((i) == 0 ? OWM_IRQn : 0)
00734 
00735 #define MXC_OWM_GET_BASE(i)              ((i) == 0 ? MXC_BASE_OWM : 0)
00736 
00737 #define MXC_OWM_GET_OWM(i)               ((i) == 0 ? MXC_OWM : 0)
00738 
00739 #define MXC_OWM_GET_IDX(p)               ((p) == MXC_OWM ? 0 : -1)
00740 
00741 
00742 /*******************************************************************************/
00743 /*                                                                   ADC / AFE */
00744 
00745 #define MXC_CFG_ADC_FIFO_DEPTH           (32)
00746 
00747 #define MXC_BASE_ADC                     ((uint32_t)0x4001F000UL)
00748 #define MXC_ADC                          ((mxc_adc_regs_t *)MXC_BASE_ADC)
00749 
00750 
00751 
00752 /*******************************************************************************/
00753 /*                                                      SPIB AHB-to-SPI Bridge */
00754 
00755 #define MXC_BASE_SPIB                    ((uint32_t)0x4000D000UL)
00756 #define MXC_SPIB                         ((mxc_spib_regs_t *)MXC_BASE_SPIB)
00757 
00758 
00759 
00760 /*******************************************************************************/
00761 /*                                                         SPI Slave Interface */
00762 #define MXC_CFG_SPIS_INSTANCES           (1)
00763 #define MXC_CFG_SPIS_FIFO_DEPTH          (32)
00764 
00765 #define MXC_BASE_SPIS                    ((uint32_t)0x40020000UL)
00766 #define MXC_SPIS                         ((mxc_spis_regs_t *)MXC_BASE_SPIS)
00767 #define MXC_BASE_SPIS_FIFO               ((uint32_t)0x4010E000UL)
00768 #define MXC_SPIS_FIFO                    ((mxc_spis_fifo_regs_t *)MXC_BASE_SPIS_FIFO)
00769 
00770 #define MXC_SPIS_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? SPIS_IRQn : 0)
00771 
00772 #define MXC_SPIS_GET_BASE(i)             ((i) == 0 ? MXC_BASE_SPIS : 0)
00773 
00774 #define MXC_SPIS_GET_SPIS(i)             ((i) == 0 ? MXC_SPIS : 0)
00775 
00776 #define MXC_SPIS_GET_IDX(p)              ((p) == MXC_SPIS ? 0 : -1)
00777 
00778 #define MXC_SPIS_GET_BASE_FIFO(i)        ((i) == 0 ? MXC_BASE_SPIS_FIFO : 0)
00779 
00780 #define MXC_SPIS_GET_SPIS_FIFO(i)        ((i) == 0 ? MXC_SPIS_FIFO :0)
00781 
00782 /*******************************************************************************/
00783 /*                                                                Bit Shifting */
00784 
00785 #define MXC_F_BIT_0        (1 << 0)
00786 #define MXC_F_BIT_1        (1 << 1)
00787 #define MXC_F_BIT_2        (1 << 2)
00788 #define MXC_F_BIT_3        (1 << 3)
00789 #define MXC_F_BIT_4        (1 << 4)
00790 #define MXC_F_BIT_5        (1 << 5)
00791 #define MXC_F_BIT_6        (1 << 6)
00792 #define MXC_F_BIT_7        (1 << 7)
00793 #define MXC_F_BIT_8        (1 << 8)
00794 #define MXC_F_BIT_9        (1 << 9)
00795 #define MXC_F_BIT_10       (1 << 10)
00796 #define MXC_F_BIT_11       (1 << 11)
00797 #define MXC_F_BIT_12       (1 << 12)
00798 #define MXC_F_BIT_13       (1 << 13)
00799 #define MXC_F_BIT_14       (1 << 14)
00800 #define MXC_F_BIT_15       (1 << 15)
00801 #define MXC_F_BIT_16       (1 << 16)
00802 #define MXC_F_BIT_17       (1 << 17)
00803 #define MXC_F_BIT_18       (1 << 18)
00804 #define MXC_F_BIT_19       (1 << 19)
00805 #define MXC_F_BIT_20       (1 << 20)
00806 #define MXC_F_BIT_21       (1 << 21)
00807 #define MXC_F_BIT_22       (1 << 22)
00808 #define MXC_F_BIT_23       (1 << 23)
00809 #define MXC_F_BIT_24       (1 << 24)
00810 #define MXC_F_BIT_25       (1 << 25)
00811 #define MXC_F_BIT_26       (1 << 26)
00812 #define MXC_F_BIT_27       (1 << 27)
00813 #define MXC_F_BIT_28       (1 << 28)
00814 #define MXC_F_BIT_29       (1 << 29)
00815 #define MXC_F_BIT_30       (1 << 30)
00816 #define MXC_F_BIT_31       (1 << 31)
00817 
00818 
00819 /*******************************************************************************/
00820 
00821 #define BITBAND(reg, bit)      ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
00822 #define MXC_CLRBIT(reg, bit)   (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
00823 #define MXC_SETBIT(reg, bit)   (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
00824 #define MXC_GETBIT(reg, bit)   (*(volatile uint32_t *)BITBAND(reg, bit))
00825 
00826 
00827 /*******************************************************************************/
00828 
00829 /* SCB CPACR Register Definitions */
00830 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
00831 #define SCB_CPACR_CP10_Pos      20                              /*!< SCB CPACR: Coprocessor 10 Position */
00832 #define SCB_CPACR_CP10_Msk      (0x3UL << SCB_CPACR_CP10_Pos)   /*!< SCB CPACR: Coprocessor 10 Mask */
00833 #define SCB_CPACR_CP11_Pos      22                              /*!< SCB CPACR: Coprocessor 11 Position */
00834 #define SCB_CPACR_CP11_Msk      (0x3UL << SCB_CPACR_CP11_Pos)   /*!< SCB CPACR: Coprocessor 11 Mask */
00835 
00836 #endif  /* _MAX32620_H_ */