trim_regs.h

00001 /*******************************************************************************
00002  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
00003  *
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00005  * copy of this software and associated documentation files (the "Software"),
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00010  *
00011  * The above copyright notice and this permission notice shall be included
00012  * in all copies or substantial portions of the Software.
00013  *
00014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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00021  *
00022  * Except as contained in this notice, the name of Maxim Integrated
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00024  * Products, Inc. Branding Policy.
00025  *
00026  * The mere transfer of this software does not imply any licenses
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00033 
00034 #ifndef _MXC_TRIM_REGS_H_
00035 #define _MXC_TRIM_REGS_H_
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 #include <stdint.h>
00042 
00043 /*
00044     If types are not defined elsewhere (CMSIS) define them here
00045 */
00046 #ifndef __IO
00047 #define __IO volatile
00048 #endif
00049 #ifndef __I
00050 #define __I  volatile const
00051 #endif
00052 #ifndef __O
00053 #define __O  volatile
00054 #endif
00055 #ifndef __R
00056 #define __R  volatile const
00057 #endif
00058 
00059 
00060 /*
00061    Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
00062    access to each register in module.
00063 */
00064 
00065 /*                                                          Offset          Register Description
00066                                                             =============   ============================================================================ */
00067 typedef struct {
00068     __R  uint32_t rsv000[10];                           /*  0x0000-0x0024                                                                                */
00069     __IO uint32_t reg10_mem_size;                       /*  0x0028          Shadow Trim for Flash and SRAM Memory Size                                   */
00070     __IO uint32_t reg11_adc_trim0;                      /*  0x002C          Shadow Trim for ADC R0                                                       */
00071     __IO uint32_t reg12_adc_trim1;                      /*  0x0030          Shadow Trim for ADC R1                                                       */
00072     __IO uint32_t for_pwr_reg5;                         /*  0x0034          Shadow Trim for PWRSEQ Register REG5                                         */
00073     __IO uint32_t for_pwr_reg6;                         /*  0x0038          Shadow Trim for PWRSEQ Register REG6                                         */
00074     __IO uint32_t for_pwr_reg7;                         /*  0x003C          Shadow Trim for PWRSEQ Register REG7                                         */
00075 } mxc_trim_regs_t;
00076 
00077 
00078 /*
00079    Register offsets for module TRIM.
00080 */
00081 
00082 #define MXC_R_TRIM_OFFS_REG10_MEM_SIZE                      ((uint32_t)0x00000028UL)
00083 #define MXC_R_TRIM_OFFS_REG11_ADC_TRIM0                     ((uint32_t)0x0000002CUL)
00084 #define MXC_R_TRIM_OFFS_REG12_ADC_TRIM1                     ((uint32_t)0x00000030UL)
00085 #define MXC_R_TRIM_OFFS_FOR_PWR_REG5                        ((uint32_t)0x00000034UL)
00086 #define MXC_R_TRIM_OFFS_FOR_PWR_REG6                        ((uint32_t)0x00000038UL)
00087 #define MXC_R_TRIM_OFFS_FOR_PWR_REG7                        ((uint32_t)0x0000003CUL)
00088 
00089 
00090 /*
00091    Field positions and masks for module TRIM.
00092 */
00093 
00094 #define MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS                  0
00095 #define MXC_F_TRIM_REG10_MEM_SIZE_SRAM                      ((uint32_t)(0x00000003UL << MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS))
00096 #define MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS                 2
00097 #define MXC_F_TRIM_REG10_MEM_SIZE_FLASH                     ((uint32_t)(0x00000007UL << MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS))
00098 
00099 #define MXC_V_TRIM_REG10_MEM_SRAM_FULL_SIZE                 ((uint32_t)(0x00000000UL))
00100 #define MXC_V_TRIM_REG10_MEM_SRAM_THREE_FOURTHS_SIZE        ((uint32_t)(0x00000001UL))
00101 #define MXC_V_TRIM_REG10_MEM_SRAM_HALF_SIZE                 ((uint32_t)(0x00000002UL))
00102 
00103 #define MXC_V_TRIM_REG10_MEM_FLASH_FULL_SIZE                ((uint32_t)(0x00000000UL))
00104 #define MXC_V_TRIM_REG10_MEM_FLASH_THREE_FOURTHS_SIZE       ((uint32_t)(0x00000001UL))
00105 #define MXC_V_TRIM_REG10_MEM_FLASH_HALF_SIZE                ((uint32_t)(0x00000002UL))
00106 #define MXC_V_TRIM_REG10_MEM_FLASH_THREE_EIGHTHS_SIZE       ((uint32_t)(0x00000003UL))
00107 #define MXC_V_TRIM_REG10_MEM_FLASH_FOURTH_SIZE              ((uint32_t)(0x00000004UL))
00108 
00109 #define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS         0
00110 #define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0             ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS))
00111 #define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS         16
00112 #define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0             ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS))
00113 
00114 #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS         0
00115 #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1             ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS))
00116 #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS         16
00117 #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1             ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS))
00118 #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS           28
00119 #define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC               ((uint32_t)(0x0000000FUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS))
00120 
00121 
00122 
00123 #ifdef __cplusplus
00124 }
00125 #endif
00126 
00127 #endif   /* _MXC_TRIM_REGS_H_ */