pwrseq_regs.h

00001 /*******************************************************************************
00002  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
00003  *
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00005  * copy of this software and associated documentation files (the "Software"),
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00010  *
00011  * The above copyright notice and this permission notice shall be included
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00013  *
00014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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00024  * Products, Inc. Branding Policy.
00025  *
00026  * The mere transfer of this software does not imply any licenses
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00033 
00034 #ifndef _MXC_PWRSEQ_REGS_H_
00035 #define _MXC_PWRSEQ_REGS_H_
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 #include <stdint.h>
00042 
00043 /*
00044     If types are not defined elsewhere (CMSIS) define them here
00045 */
00046 #ifndef __IO
00047 #define __IO volatile
00048 #endif
00049 #ifndef __I
00050 #define __I  volatile const
00051 #endif
00052 #ifndef __O
00053 #define __O  volatile
00054 #endif
00055 #ifndef __R
00056 #define __R  volatile const
00057 #endif
00058 
00059 
00060 /*
00061    Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
00062    access to each register in module.
00063 */
00064 
00065 /*                                                          Offset          Register Description
00066                                                             =============   ============================================================================ */
00067 typedef struct {
00068     __IO uint32_t reg0;                                 /*  0x0000          Power Sequencer Control Register 0                                           */
00069     __IO uint32_t reg1;                                 /*  0x0004          Power Sequencer Control Register 1                                           */
00070     __IO uint32_t reg2;                                 /*  0x0008          Power Sequencer Control Register 2                                           */
00071     __IO uint32_t reg3;                                 /*  0x000C          Power Sequencer Control Register 3                                           */
00072     __IO uint32_t reg4;                                 /*  0x0010          Power Sequencer Control Register 4 (Internal Test Only)                      */
00073     __IO uint32_t reg5;                                 /*  0x0014          Power Sequencer Control Register 5 (Trim 0)                                  */
00074     __IO uint32_t reg6;                                 /*  0x0018          Power Sequencer Control Register 6 (Trim 1)                                  */
00075     __IO uint32_t reg7;                                 /*  0x001C          Power Sequencer Control Register 7 (Trim 2)                                  */
00076     __IO uint32_t flags;                                /*  0x0020          Power Sequencer Flags                                                        */
00077     __IO uint32_t msk_flags;                            /*  0x0024          Power Sequencer Flags Mask Register                                          */
00078     __R  uint32_t rsv028;                               /*  0x0028                                                                                       */
00079     __IO uint32_t wr_protect;                           /*  0x002C          Critical Setting Write Protect Register                                      */
00080     __IO uint32_t retn_ctrl0;                           /*  0x0030          Retention Control Register 0                                                 */
00081     __IO uint32_t retn_ctrl1;                           /*  0x0034          Retention Control Register 1                                                 */
00082     __IO uint32_t pwr_misc;                             /*  0x0038          Power Misc Controls                                                          */
00083     __IO uint32_t rtc_ctrl2;                            /*  0x003C          RTC Misc Controls                                                            */
00084 } mxc_pwrseq_regs_t;
00085 
00086 
00087 /*
00088    Register offsets for module PWRSEQ.
00089 */
00090 
00091 #define MXC_R_PWRSEQ_OFFS_REG0                              ((uint32_t)0x00000000UL)
00092 #define MXC_R_PWRSEQ_OFFS_REG1                              ((uint32_t)0x00000004UL)
00093 #define MXC_R_PWRSEQ_OFFS_REG2                              ((uint32_t)0x00000008UL)
00094 #define MXC_R_PWRSEQ_OFFS_REG3                              ((uint32_t)0x0000000CUL)
00095 #define MXC_R_PWRSEQ_OFFS_REG4                              ((uint32_t)0x00000010UL)
00096 #define MXC_R_PWRSEQ_OFFS_REG5                              ((uint32_t)0x00000014UL)
00097 #define MXC_R_PWRSEQ_OFFS_REG6                              ((uint32_t)0x00000018UL)
00098 #define MXC_R_PWRSEQ_OFFS_REG7                              ((uint32_t)0x0000001CUL)
00099 #define MXC_R_PWRSEQ_OFFS_FLAGS                             ((uint32_t)0x00000020UL)
00100 #define MXC_R_PWRSEQ_OFFS_MSK_FLAGS                         ((uint32_t)0x00000024UL)
00101 #define MXC_R_PWRSEQ_OFFS_WR_PROTECT                        ((uint32_t)0x0000002CUL)
00102 #define MXC_R_PWRSEQ_OFFS_RETN_CTRL0                        ((uint32_t)0x00000030UL)
00103 #define MXC_R_PWRSEQ_OFFS_RETN_CTRL1                        ((uint32_t)0x00000034UL)
00104 #define MXC_R_PWRSEQ_OFFS_PWR_MISC                          ((uint32_t)0x00000038UL)
00105 #define MXC_R_PWRSEQ_OFFS_RTC_CTRL2                         ((uint32_t)0x0000003CUL)
00106 
00107 
00108 /*
00109    Field positions and masks for module PWRSEQ.
00110 */
00111 
00112 #define MXC_F_PWRSEQ_REG0_PWR_LP1_POS                       0
00113 #define MXC_F_PWRSEQ_REG0_PWR_LP1                           ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
00114 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS                1
00115 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
00116 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS                2
00117 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
00118 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS               3
00119 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS))
00120 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS               4
00121 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS))
00122 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS              5
00123 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS))
00124 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS              6
00125 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS))
00126 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS                  7
00127 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
00128 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS                  8
00129 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
00130 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS                  9
00131 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
00132 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS                  10
00133 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
00134 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS                 11
00135 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
00136 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS                 12
00137 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
00138 #define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS               13
00139 #define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS))
00140 #define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS               15
00141 #define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS))
00142 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS              17
00143 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
00144 #define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS              19
00145 #define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS))
00146 #define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS           21
00147 #define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS))
00148 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS            23
00149 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS))
00150 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS            24
00151 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS))
00152 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS            25
00153 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS))
00154 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS            26
00155 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS))
00156 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS           27
00157 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS))
00158 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS           28
00159 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS))
00160 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS                  29
00161 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS))
00162 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS                  30
00163 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS))
00164 #define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS                31
00165 #define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS))
00166 
00167 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS        0
00168 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS))
00169 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS          1
00170 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH              ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS))
00171 #define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS                 2
00172 #define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS))
00173 #define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS              3
00174 #define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS))
00175 #define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS               4
00176 #define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS))
00177 #define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS             5
00178 #define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS))
00179 #define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS            6
00180 #define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS))
00181 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS          8
00182 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN              ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS))
00183 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS         10
00184 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS))
00185 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS            12
00186 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS))
00187 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS           13
00188 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS))
00189 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS            14
00190 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS))
00191 #define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS          16
00192 #define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR              ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS))
00193 #define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS         17
00194 #define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS))
00195 #define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS        18
00196 #define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS))
00197 #define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS          19
00198 #define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN              ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS))
00199 
00200 #define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS                0
00201 #define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST                    ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS))
00202 #define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS                2
00203 #define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST                    ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS))
00204 #define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS                 4
00205 #define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST                     ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS))
00206 #define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS                 6
00207 #define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST                     ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS))
00208 #define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS               8
00209 #define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST                   ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS))
00210 #define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS                10
00211 #define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST                    ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS))
00212 #define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS               12
00213 #define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST                   ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS))
00214 
00215 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS                     0
00216 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL                         ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
00217 #define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS                 3
00218 #define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL                     ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS))
00219 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS               6
00220 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX                   ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
00221 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS                8
00222 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX                    ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
00223 #define MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS                   10
00224 #define MXC_F_PWRSEQ_REG3_PWR_FAILSEL                       ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS))
00225 #define MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS                    16
00226 #define MXC_F_PWRSEQ_REG3_PWR_RO_DIV                        ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS))
00227 #define MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS                    20
00228 #define MXC_F_PWRSEQ_REG3_PWR_RC_DIV                        ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS))
00229 
00230 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS              0
00231 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
00232 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS            1
00233 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
00234 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS              3
00235 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
00236 #define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS              4
00237 #define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS))
00238 #define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS            5
00239 #define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS))
00240 #define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS             6
00241 #define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS))
00242 #define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS               7
00243 #define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS))
00244 #define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS                   8
00245 #define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX                       ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS))
00246 #define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS        9
00247 #define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS))
00248 #define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS            10
00249 #define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS))
00250 
00251 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS               0
00252 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG                   ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
00253 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS                 9
00254 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS                     ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS))
00255 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS           15
00256 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0               ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS))
00257 #define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS                  21
00258 #define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM                      ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS))
00259 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS           25
00260 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6               ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS))
00261 
00262 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS             0
00263 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS                 ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
00264 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS           3
00265 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES               ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
00266 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS           7
00267 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES               ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
00268 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS             11
00269 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF                 ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS))
00270 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS           20
00271 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC               ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS))
00272 
00273 #define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS        0
00274 #define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS))
00275 #define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS                   16
00276 #define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC                       ((uint32_t)(0x0000FFFFUL << MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS))
00277 
00278 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS               0
00279 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
00280 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS               1
00281 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
00282 #define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS               2
00283 #define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS))
00284 #define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS                3
00285 #define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS))
00286 #define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS          4
00287 #define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE              ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS))
00288 #define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS                 5
00289 #define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS))
00290 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS            6
00291 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS))
00292 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS            7
00293 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS))
00294 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS             8
00295 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS))
00296 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS             9
00297 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS))
00298 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS           10
00299 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS))
00300 #define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS        11
00301 #define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
00302 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS                    12
00303 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0                        ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
00304 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS                    13
00305 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1                        ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
00306 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS             14
00307 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
00308 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS                 15
00309 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
00310 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS          16
00311 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP              ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
00312 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS        17
00313 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
00314 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS               18
00315 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS))
00316 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS            19
00317 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS))
00318 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS           20
00319 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS))
00320 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS          21
00321 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL              ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
00322 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS         22
00323 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
00324 #define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS     23
00325 #define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG         ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
00326 #define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS       24
00327 #define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG           ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
00328 
00329 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS           1
00330 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
00331 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS           2
00332 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS))
00333 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS            3
00334 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS))
00335 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS      4
00336 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE          ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS))
00337 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS             5
00338 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS))
00339 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS        6
00340 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS))
00341 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS        7
00342 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS))
00343 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS         8
00344 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS))
00345 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS         9
00346 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS))
00347 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS       10
00348 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD           ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS))
00349 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS    11
00350 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH        ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
00351 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS                12
00352 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
00353 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS                13
00354 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
00355 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS         14
00356 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
00357 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS             15
00358 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
00359 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS      16
00360 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP          ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
00361 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS    17
00362 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP        ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
00363 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS           18
00364 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS))
00365 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS        19
00366 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS))
00367 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS       20
00368 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD           ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS))
00369 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS      21
00370 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL          ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
00371 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS     22
00372 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL         ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
00373 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS  23
00374 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
00375 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS   24
00376 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG       ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
00377 
00378 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS              0
00379 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ                  ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS))
00380 #define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS                 8
00381 #define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ                     ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS))
00382 #define MXC_F_PWRSEQ_WR_PROTECT_RTC_POS                     28
00383 #define MXC_F_PWRSEQ_WR_PROTECT_RTC                         ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_RTC_POS))
00384 #define MXC_F_PWRSEQ_WR_PROTECT_INFO_POS                    29
00385 #define MXC_F_PWRSEQ_WR_PROTECT_INFO                        ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_INFO_POS))
00386 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS                  30
00387 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS))
00388 #define MXC_F_PWRSEQ_WR_PROTECT_WP_POS                      31
00389 #define MXC_F_PWRSEQ_WR_PROTECT_WP                          ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_WP_POS))
00390 
00391 #define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS            0
00392 #define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS))
00393 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS        1
00394 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS))
00395 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS          2
00396 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK              ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS))
00397 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS           3
00398 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS))
00399 #define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS        4
00400 #define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS))
00401 
00402 #define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS                  0
00403 #define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK                      ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS))
00404 #define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS                4
00405 #define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS                    ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS))
00406 
00407 #define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS        0
00408 #define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS))
00409 
00410 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS           0
00411 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS))
00412 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS           1
00413 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS))
00414 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS        2
00415 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS))
00416 #define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS          3
00417 #define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE              ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS))
00418 #define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS                 24
00419 #define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK                     ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS))
00420 
00421 
00422 
00423 #ifdef __cplusplus
00424 }
00425 #endif
00426 
00427 #endif   /* _MXC_PWRSEQ_REGS_H_ */