pwrman_regs.h

00001 /*******************************************************************************
00002  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
00003  *
00004  * Permission is hereby granted, free of charge, to any person obtaining a
00005  * copy of this software and associated documentation files (the "Software"),
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00009  * Software is furnished to do so, subject to the following conditions:
00010  *
00011  * The above copyright notice and this permission notice shall be included
00012  * in all copies or substantial portions of the Software.
00013  *
00014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00016  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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00019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
00020  * OTHER DEALINGS IN THE SOFTWARE.
00021  *
00022  * Except as contained in this notice, the name of Maxim Integrated
00023  * Products, Inc. shall not be used except as stated in the Maxim Integrated
00024  * Products, Inc. Branding Policy.
00025  *
00026  * The mere transfer of this software does not imply any licenses
00027  * of trade secrets, proprietary technology, copyrights, patents,
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00033 
00034 #ifndef _MXC_PWRMAN_REGS_H_
00035 #define _MXC_PWRMAN_REGS_H_
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 #include <stdint.h>
00042 
00043 /*
00044     If types are not defined elsewhere (CMSIS) define them here
00045 */
00046 #ifndef __IO
00047 #define __IO volatile
00048 #endif
00049 #ifndef __I
00050 #define __I  volatile const
00051 #endif
00052 #ifndef __O
00053 #define __O  volatile
00054 #endif
00055 #ifndef __R
00056 #define __R  volatile const
00057 #endif
00058 
00059 
00060 /**
00061  * @brief Defines PAD Modes for Wake Up Detection.
00062  */
00063 typedef enum {
00064     /** WUD Mode for Selected PAD = Clear/Activate */
00065     MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
00066     /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
00067     MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
00068     /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
00069     MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
00070     /** WUD Mode for Selected PAD = No pad state change */
00071     MXC_E_PWRMAN_PAD_MODE_NONE
00072 }
00073 mxc_pwrman_pad_mode_t;
00074 
00075 /*
00076    Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
00077    access to each register in module.
00078 */
00079 
00080 /*                                                          Offset          Register Description
00081                                                             =============   ============================================================================ */
00082 typedef struct {
00083     __IO uint32_t pwr_rst_ctrl;                         /*  0x0000          Power Reset Control and Status                                               */
00084     __IO uint32_t intfl;                                /*  0x0004          Interrupt Flags                                                              */
00085     __IO uint32_t inten;                                /*  0x0008          Interrupt Enable/Disable Controls                                            */
00086     __IO uint32_t svm_events;                           /*  0x000C          SVM Event Status Flags (read-only)                                           */
00087     __IO uint32_t wud_ctrl;                             /*  0x0010          Wake-Up Detect Control                                                       */
00088     __IO uint32_t wud_pulse0;                           /*  0x0014          WUD Pulse To Mode Bit 0                                                      */
00089     __IO uint32_t wud_pulse1;                           /*  0x0018          WUD Pulse To Mode Bit 1                                                      */
00090     __IO uint32_t wud_seen0;                            /*  0x001C          Wake-up Detect Status for P0/P1/P2/P3                                        */
00091     __IO uint32_t wud_seen1;                            /*  0x0020          Wake-up Detect Status for P4/P5/P6/P7                                        */
00092     __R  uint32_t rsv024[3];                            /*  0x0024-0x002C                                                                                */
00093     __IO uint32_t pt_regmap_ctrl;                       /*  0x0030          PT Register Mapping Control                                                  */
00094     __R  uint32_t rsv034;                               /*  0x0034                                                                                       */
00095     __IO uint32_t die_type;                             /*  0x0038          Die Type ID Register                                                         */
00096     __IO uint32_t base_part_num;                        /*  0x003C          Base Part Number                                                             */
00097     __IO uint32_t mask_id0;                             /*  0x0040          Mask ID Register 0                                                           */
00098     __IO uint32_t mask_id1;                             /*  0x0044          Mask ID Register 1                                                           */
00099     __IO uint32_t peripheral_reset;                     /*  0x0048          Peripheral Reset Control Register                                            */
00100 } mxc_pwrman_regs_t;
00101 
00102 
00103 /*
00104    Register offsets for module PWRMAN.
00105 */
00106 
00107 #define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL                      ((uint32_t)0x00000000UL)
00108 #define MXC_R_PWRMAN_OFFS_INTFL                             ((uint32_t)0x00000004UL)
00109 #define MXC_R_PWRMAN_OFFS_INTEN                             ((uint32_t)0x00000008UL)
00110 #define MXC_R_PWRMAN_OFFS_SVM_EVENTS                        ((uint32_t)0x0000000CUL)
00111 #define MXC_R_PWRMAN_OFFS_WUD_CTRL                          ((uint32_t)0x00000010UL)
00112 #define MXC_R_PWRMAN_OFFS_WUD_PULSE0                        ((uint32_t)0x00000014UL)
00113 #define MXC_R_PWRMAN_OFFS_WUD_PULSE1                        ((uint32_t)0x00000018UL)
00114 #define MXC_R_PWRMAN_OFFS_WUD_SEEN0                         ((uint32_t)0x0000001CUL)
00115 #define MXC_R_PWRMAN_OFFS_WUD_SEEN1                         ((uint32_t)0x00000020UL)
00116 #define MXC_R_PWRMAN_OFFS_PT_REGMAP_CTRL                    ((uint32_t)0x00000030UL)
00117 #define MXC_R_PWRMAN_OFFS_DIE_TYPE                          ((uint32_t)0x00000038UL)
00118 #define MXC_R_PWRMAN_OFFS_BASE_PART_NUM                     ((uint32_t)0x0000003CUL)
00119 #define MXC_R_PWRMAN_OFFS_MASK_ID0                          ((uint32_t)0x00000040UL)
00120 #define MXC_R_PWRMAN_OFFS_MASK_ID1                          ((uint32_t)0x00000044UL)
00121 #define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET                  ((uint32_t)0x00000048UL)
00122 
00123 
00124 /*
00125    Field positions and masks for module PWRMAN.
00126 */
00127 
00128 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS           2
00129 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED               ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
00130 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS             3
00131 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
00132 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS           4
00133 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED               ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
00134 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS       5
00135 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED           ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
00136 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS        8
00137 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET            ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
00138 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS      9
00139 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET          ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
00140 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS         16
00141 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT             ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
00142 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS            17
00143 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
00144 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS        18
00145 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM            ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
00146 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS      19
00147 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT          ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
00148 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS     20
00149 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN         ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
00150 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS       21
00151 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION           ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
00152 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS                   22
00153 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
00154 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS        31
00155 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE            ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
00156 
00157 #define MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS                 0
00158 #define MXC_F_PWRMAN_INTFL_V1_2_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS))
00159 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS                 1
00160 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
00161 #define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS                  2
00162 #define MXC_F_PWRMAN_INTFL_RTC_WARNING                      ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
00163 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS                 3
00164 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
00165 #define MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS                 4
00166 #define MXC_F_PWRMAN_INTFL_VDDB_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS))
00167 #define MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS                5
00168 #define MXC_F_PWRMAN_INTFL_VDDIO_WARNING                    ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS))
00169 #define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS               6
00170 #define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS))
00171 
00172 #define MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS                 0
00173 #define MXC_F_PWRMAN_INTEN_V1_2_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS))
00174 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS                 1
00175 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
00176 #define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS                  2
00177 #define MXC_F_PWRMAN_INTEN_RTC_WARNING                      ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
00178 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS                 3
00179 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
00180 #define MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS                 4
00181 #define MXC_F_PWRMAN_INTEN_VDDB_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS))
00182 #define MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS                5
00183 #define MXC_F_PWRMAN_INTEN_VDDIO_WARNING                    ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS))
00184 #define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS               6
00185 #define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS))
00186 
00187 #define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS            0
00188 #define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS))
00189 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS            1
00190 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
00191 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS             2
00192 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
00193 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS            3
00194 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
00195 #define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS            4
00196 #define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS))
00197 #define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS           5
00198 #define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING               ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS))
00199 #define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS          6
00200 #define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING              ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS))
00201 
00202 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS                0
00203 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT                    ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
00204 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS                  8
00205 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE                      ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
00206 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS                 12
00207 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
00208 #define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS               16
00209 #define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS))
00210 
00211 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS                    0
00212 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
00213 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS                    1
00214 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
00215 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS                    2
00216 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
00217 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS                    3
00218 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
00219 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS                    4
00220 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
00221 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS                    5
00222 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
00223 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS                    6
00224 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
00225 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS                    7
00226 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
00227 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS                    8
00228 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
00229 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS                    9
00230 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
00231 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS                   10
00232 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
00233 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS                   11
00234 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
00235 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS                   12
00236 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
00237 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS                   13
00238 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
00239 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS                   14
00240 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
00241 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS                   15
00242 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
00243 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS                   16
00244 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
00245 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS                   17
00246 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
00247 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS                   18
00248 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
00249 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS                   19
00250 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
00251 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS                   20
00252 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
00253 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS                   21
00254 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
00255 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS                   22
00256 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
00257 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS                   23
00258 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
00259 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS                   24
00260 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
00261 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS                   25
00262 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
00263 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS                   26
00264 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
00265 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS                   27
00266 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
00267 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS                   28
00268 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
00269 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS                   29
00270 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
00271 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS                   30
00272 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
00273 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS                   31
00274 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
00275 
00276 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS                   0
00277 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
00278 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS                   1
00279 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
00280 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS                   2
00281 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
00282 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS                   3
00283 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
00284 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS                   4
00285 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
00286 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS                   5
00287 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
00288 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS                   6
00289 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
00290 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS                   7
00291 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
00292 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS                   8
00293 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS))
00294 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS                   9
00295 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS))
00296 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS                   10
00297 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS))
00298 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS                   11
00299 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS))
00300 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS                   12
00301 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS))
00302 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS                   13
00303 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS))
00304 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS                   14
00305 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS))
00306 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS                   15
00307 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS))
00308 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS                   16
00309 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS))
00310 
00311 #define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS          0
00312 #define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE              ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS))
00313 
00314 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS     0
00315 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER         ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
00316 
00317 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS               0
00318 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID                   ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
00319 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS                   4
00320 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID                       ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
00321 
00322 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS                   0
00323 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID                       ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
00324 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS            31
00325 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
00326 
00327 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS               0
00328 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
00329 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS              1
00330 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS))
00331 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS               2
00332 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS))
00333 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS               3
00334 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
00335 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS               4
00336 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
00337 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS               5
00338 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
00339 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS         6
00340 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0             ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
00341 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS              7
00342 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
00343 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS            8
00344 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
00345 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS            9
00346 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
00347 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS            10
00348 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
00349 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS            11
00350 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
00351 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS            12
00352 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS))
00353 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS            13
00354 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS))
00355 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS       14
00356 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN           ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
00357 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS             15
00358 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
00359 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS             16
00360 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
00361 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS             17
00362 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS))
00363 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS             18
00364 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS))
00365 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS             19
00366 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
00367 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS             20
00368 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
00369 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS             21
00370 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS))
00371 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS              22
00372 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
00373 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS             23
00374 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS))
00375 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS             24
00376 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS))
00377 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS             25
00378 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS))
00379 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS              26
00380 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS))
00381 #define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS               27
00382 #define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS))
00383 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS               28
00384 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
00385 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS              29
00386 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS))
00387 
00388 
00389 
00390 #ifdef __cplusplus
00391 }
00392 #endif
00393 
00394 #endif   /* _MXC_PWRMAN_REGS_H_ */