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ioman_regs.h
00001 /******************************************************************************* 00002 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. 00003 * 00004 * Permission is hereby granted, free of charge, to any person obtaining a 00005 * copy of this software and associated documentation files (the "Software"), 00006 * to deal in the Software without restriction, including without limitation 00007 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 00008 * and/or sell copies of the Software, and to permit persons to whom the 00009 * Software is furnished to do so, subject to the following conditions: 00010 * 00011 * The above copyright notice and this permission notice shall be included 00012 * in all copies or substantial portions of the Software. 00013 * 00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 00015 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00016 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 00017 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 00018 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 00019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 00020 * OTHER DEALINGS IN THE SOFTWARE. 00021 * 00022 * Except as contained in this notice, the name of Maxim Integrated 00023 * Products, Inc. shall not be used except as stated in the Maxim Integrated 00024 * Products, Inc. Branding Policy. 00025 * 00026 * The mere transfer of this software does not imply any licenses 00027 * of trade secrets, proprietary technology, copyrights, patents, 00028 * trademarks, maskwork rights, or any other form of intellectual 00029 * property whatsoever. Maxim Integrated Products, Inc. retains all 00030 * ownership rights. 00031 * 00032 ******************************************************************************/ 00033 00034 #ifndef _MXC_IOMAN_REGS_H_ 00035 #define _MXC_IOMAN_REGS_H_ 00036 00037 #ifdef __cplusplus 00038 extern "C" { 00039 #endif 00040 00041 #include <stdint.h> 00042 00043 /* 00044 If types are not defined elsewhere (CMSIS) define them here 00045 */ 00046 #ifndef __IO 00047 #define __IO volatile 00048 #endif 00049 #ifndef __I 00050 #define __I volatile const 00051 #endif 00052 #ifndef __O 00053 #define __O volatile 00054 #endif 00055 #ifndef __R 00056 #define __R volatile const 00057 #endif 00058 00059 00060 /* 00061 Bitfield structs for registers in this module 00062 */ 00063 00064 typedef struct { 00065 uint32_t wud_req_p0 : 8; 00066 uint32_t wud_req_p1 : 8; 00067 uint32_t wud_req_p2 : 8; 00068 uint32_t wud_req_p3 : 8; 00069 } mxc_ioman_wud_req0_t; 00070 00071 typedef struct { 00072 uint32_t wud_req_p4 : 8; 00073 uint32_t wud_req_p5 : 8; 00074 uint32_t wud_req_p6 : 8; 00075 uint32_t wud_req_p7 : 8; 00076 } mxc_ioman_wud_req1_t; 00077 00078 typedef struct { 00079 uint32_t wud_ack_p0 : 8; 00080 uint32_t wud_ack_p1 : 8; 00081 uint32_t wud_ack_p2 : 8; 00082 uint32_t wud_ack_p3 : 8; 00083 } mxc_ioman_wud_ack0_t; 00084 00085 typedef struct { 00086 uint32_t wud_ack_p4 : 8; 00087 uint32_t wud_ack_p5 : 8; 00088 uint32_t wud_ack_p6 : 8; 00089 uint32_t wud_ack_p7 : 8; 00090 } mxc_ioman_wud_ack1_t; 00091 00092 typedef struct { 00093 uint32_t ali_req_p0 : 8; 00094 uint32_t ali_req_p1 : 8; 00095 uint32_t ali_req_p2 : 8; 00096 uint32_t ali_req_p3 : 8; 00097 } mxc_ioman_ali_req0_t; 00098 00099 typedef struct { 00100 uint32_t ali_req_p4 : 8; 00101 uint32_t ali_req_p5 : 8; 00102 uint32_t ali_req_p6 : 8; 00103 uint32_t ali_req_p7 : 8; 00104 } mxc_ioman_ali_req1_t; 00105 00106 typedef struct { 00107 uint32_t ali_ack_p0 : 8; 00108 uint32_t ali_ack_p1 : 8; 00109 uint32_t ali_ack_p2 : 8; 00110 uint32_t ali_ack_p3 : 8; 00111 } mxc_ioman_ali_ack0_t; 00112 00113 typedef struct { 00114 uint32_t ali_ack_p4 : 8; 00115 uint32_t ali_ack_p5 : 8; 00116 uint32_t ali_ack_p6 : 8; 00117 uint32_t ali_ack_p7 : 8; 00118 } mxc_ioman_ali_ack1_t; 00119 00120 typedef struct { 00121 uint32_t : 4; 00122 uint32_t core_io_req : 1; 00123 uint32_t : 3; 00124 uint32_t ss0_io_req : 1; 00125 uint32_t ss1_io_req : 1; 00126 uint32_t ss2_io_req : 1; 00127 uint32_t : 1; 00128 uint32_t quad_io_req : 1; 00129 uint32_t : 3; 00130 uint32_t fast_mode : 1; 00131 uint32_t : 15; 00132 } mxc_ioman_spix_req_t; 00133 00134 typedef struct { 00135 uint32_t : 4; 00136 uint32_t core_io_ack : 1; 00137 uint32_t : 3; 00138 uint32_t ss0_io_ack : 1; 00139 uint32_t ss1_io_ack : 1; 00140 uint32_t ss2_io_ack : 1; 00141 uint32_t : 1; 00142 uint32_t quad_io_ack : 1; 00143 uint32_t : 3; 00144 uint32_t fast_mode : 1; 00145 uint32_t : 15; 00146 } mxc_ioman_spix_ack_t; 00147 00148 typedef struct { 00149 uint32_t io_map : 1; 00150 uint32_t cts_map : 1; 00151 uint32_t rts_map : 1; 00152 uint32_t : 1; 00153 uint32_t io_req : 1; 00154 uint32_t cts_io_req : 1; 00155 uint32_t rts_io_req : 1; 00156 uint32_t : 25; 00157 } mxc_ioman_uart0_req_t; 00158 00159 typedef struct { 00160 uint32_t io_map : 1; 00161 uint32_t cts_map : 1; 00162 uint32_t rts_map : 1; 00163 uint32_t : 1; 00164 uint32_t io_ack : 1; 00165 uint32_t cts_io_ack : 1; 00166 uint32_t rts_io_ack : 1; 00167 uint32_t : 25; 00168 } mxc_ioman_uart0_ack_t; 00169 00170 typedef struct { 00171 uint32_t io_map : 1; 00172 uint32_t cts_map : 1; 00173 uint32_t rts_map : 1; 00174 uint32_t : 1; 00175 uint32_t io_req : 1; 00176 uint32_t cts_io_req : 1; 00177 uint32_t rts_io_req : 1; 00178 uint32_t : 25; 00179 } mxc_ioman_uart1_req_t; 00180 00181 typedef struct { 00182 uint32_t io_map : 1; 00183 uint32_t cts_map : 1; 00184 uint32_t rts_map : 1; 00185 uint32_t : 1; 00186 uint32_t io_ack : 1; 00187 uint32_t cts_io_ack : 1; 00188 uint32_t rts_io_ack : 1; 00189 uint32_t : 25; 00190 } mxc_ioman_uart1_ack_t; 00191 00192 typedef struct { 00193 uint32_t io_map : 1; 00194 uint32_t cts_map : 1; 00195 uint32_t rts_map : 1; 00196 uint32_t : 1; 00197 uint32_t io_req : 1; 00198 uint32_t cts_io_req : 1; 00199 uint32_t rts_io_req : 1; 00200 uint32_t : 25; 00201 } mxc_ioman_uart2_req_t; 00202 00203 typedef struct { 00204 uint32_t io_map : 1; 00205 uint32_t cts_map : 1; 00206 uint32_t rts_map : 1; 00207 uint32_t : 1; 00208 uint32_t io_ack : 1; 00209 uint32_t cts_io_ack : 1; 00210 uint32_t rts_io_ack : 1; 00211 uint32_t : 25; 00212 } mxc_ioman_uart2_ack_t; 00213 00214 typedef struct { 00215 uint32_t io_map : 1; 00216 uint32_t cts_map : 1; 00217 uint32_t rts_map : 1; 00218 uint32_t : 1; 00219 uint32_t io_req : 1; 00220 uint32_t cts_io_req : 1; 00221 uint32_t rts_io_req : 1; 00222 uint32_t : 25; 00223 } mxc_ioman_uart3_req_t; 00224 00225 typedef struct { 00226 uint32_t io_map : 1; 00227 uint32_t cts_map : 1; 00228 uint32_t rts_map : 1; 00229 uint32_t : 1; 00230 uint32_t io_ack : 1; 00231 uint32_t cts_io_ack : 1; 00232 uint32_t rts_io_ack : 1; 00233 uint32_t : 25; 00234 } mxc_ioman_uart3_ack_t; 00235 00236 typedef struct { 00237 uint32_t : 4; 00238 uint32_t core_io_req : 1; 00239 uint32_t push_pull : 1; 00240 uint32_t : 26; 00241 } mxc_ioman_i2cm0_req_t; 00242 00243 typedef struct { 00244 uint32_t : 4; 00245 uint32_t core_io_ack : 1; 00246 uint32_t : 27; 00247 } mxc_ioman_i2cm0_ack_t; 00248 00249 typedef struct { 00250 uint32_t : 4; 00251 uint32_t core_io_req : 1; 00252 uint32_t push_pull : 1; 00253 uint32_t : 26; 00254 } mxc_ioman_i2cm1_req_t; 00255 00256 typedef struct { 00257 uint32_t : 4; 00258 uint32_t core_io_ack : 1; 00259 uint32_t : 27; 00260 } mxc_ioman_i2cm1_ack_t; 00261 00262 typedef struct { 00263 uint32_t : 4; 00264 uint32_t core_io_req : 1; 00265 uint32_t push_pull : 1; 00266 uint32_t : 26; 00267 } mxc_ioman_i2cm2_req_t; 00268 00269 typedef struct { 00270 uint32_t : 4; 00271 uint32_t core_io_ack : 1; 00272 uint32_t : 27; 00273 } mxc_ioman_i2cm2_ack_t; 00274 00275 typedef struct { 00276 uint32_t mapping_req : 2; 00277 uint32_t : 2; 00278 uint32_t core_io_req : 1; 00279 uint32_t : 27; 00280 } mxc_ioman_i2cs_req_t; 00281 00282 typedef struct { 00283 uint32_t mapping_ack : 2; 00284 uint32_t : 2; 00285 uint32_t core_io_ack : 1; 00286 uint32_t : 27; 00287 } mxc_ioman_i2cs_acl_t; 00288 00289 typedef struct { 00290 uint32_t : 4; 00291 uint32_t core_io_req : 1; 00292 uint32_t : 3; 00293 uint32_t ss0_io_req : 1; 00294 uint32_t ss1_io_req : 1; 00295 uint32_t ss2_io_req : 1; 00296 uint32_t ss3_io_req : 1; 00297 uint32_t ss4_io_req : 1; 00298 uint32_t : 7; 00299 uint32_t quad_io_req : 1; 00300 uint32_t : 3; 00301 uint32_t fast_mode : 1; 00302 uint32_t : 7; 00303 } mxc_ioman_spim0_req_t; 00304 00305 typedef struct { 00306 uint32_t : 4; 00307 uint32_t core_io_ack : 1; 00308 uint32_t : 3; 00309 uint32_t ss0_io_ack : 1; 00310 uint32_t ss1_io_ack : 1; 00311 uint32_t ss2_io_ack : 1; 00312 uint32_t ss3_io_ack : 1; 00313 uint32_t ss4_io_ack : 1; 00314 uint32_t : 7; 00315 uint32_t quad_io_ack : 1; 00316 uint32_t : 3; 00317 uint32_t fast_mode : 1; 00318 uint32_t : 7; 00319 } mxc_ioman_spim0_ack_t; 00320 00321 typedef struct { 00322 uint32_t : 4; 00323 uint32_t core_io_req : 1; 00324 uint32_t : 3; 00325 uint32_t ss0_io_req : 1; 00326 uint32_t ss1_io_req : 1; 00327 uint32_t ss2_io_req : 1; 00328 uint32_t : 9; 00329 uint32_t quad_io_req : 1; 00330 uint32_t : 3; 00331 uint32_t fast_mode : 1; 00332 uint32_t : 7; 00333 } mxc_ioman_spim1_req_t; 00334 00335 typedef struct { 00336 uint32_t : 4; 00337 uint32_t core_io_ack : 1; 00338 uint32_t : 3; 00339 uint32_t ss0_io_ack : 1; 00340 uint32_t ss1_io_ack : 1; 00341 uint32_t ss2_io_ack : 1; 00342 uint32_t : 9; 00343 uint32_t quad_io_ack : 1; 00344 uint32_t : 3; 00345 uint32_t fast_mode : 1; 00346 uint32_t : 7; 00347 } mxc_ioman_spim1_ack_t; 00348 00349 typedef struct { 00350 uint32_t mapping_req : 2; 00351 uint32_t : 2; 00352 uint32_t core_io_req : 1; 00353 uint32_t : 3; 00354 uint32_t ss0_io_req : 1; 00355 uint32_t ss1_io_req : 1; 00356 uint32_t ss2_io_req : 1; 00357 uint32_t : 5; 00358 uint32_t sr0_io_req : 1; 00359 uint32_t sr1_io_req : 1; 00360 uint32_t : 2; 00361 uint32_t quad_io_req : 1; 00362 uint32_t : 3; 00363 uint32_t fast_mode : 1; 00364 uint32_t : 7; 00365 } mxc_ioman_spim2_req_t; 00366 00367 typedef struct { 00368 uint32_t mapping_ack : 2; 00369 uint32_t : 2; 00370 uint32_t core_io_ack : 1; 00371 uint32_t : 3; 00372 uint32_t ss0_io_ack : 1; 00373 uint32_t ss1_io_ack : 1; 00374 uint32_t ss2_io_ack : 1; 00375 uint32_t : 5; 00376 uint32_t sr0_io_req : 1; 00377 uint32_t sr1_io_req : 1; 00378 uint32_t : 2; 00379 uint32_t quad_io_ack : 1; 00380 uint32_t : 3; 00381 uint32_t fast_mode : 1; 00382 uint32_t : 7; 00383 } mxc_ioman_spim2_ack_t; 00384 00385 typedef struct { 00386 uint32_t : 4; 00387 uint32_t core_io_req : 1; 00388 uint32_t : 3; 00389 uint32_t quad_io_req : 1; 00390 uint32_t : 3; 00391 uint32_t fast_mode : 1; 00392 uint32_t : 19; 00393 } mxc_ioman_spib_req_t; 00394 00395 typedef struct { 00396 uint32_t : 4; 00397 uint32_t core_io_ack : 1; 00398 uint32_t : 3; 00399 uint32_t quad_io_ack : 1; 00400 uint32_t : 3; 00401 uint32_t fast_mode : 1; 00402 uint32_t : 19; 00403 } mxc_ioman_spib_ack_t; 00404 00405 typedef struct { 00406 uint32_t : 4; 00407 uint32_t mapping_req : 1; 00408 uint32_t epu_io_req : 1; 00409 uint32_t : 26; 00410 } mxc_ioman_owm_req_t; 00411 00412 typedef struct { 00413 uint32_t : 4; 00414 uint32_t mapping_ack : 1; 00415 uint32_t epu_io_ack : 1; 00416 uint32_t : 26; 00417 } mxc_ioman_owm_ack_t; 00418 00419 typedef struct { 00420 uint32_t mapping_req : 2; 00421 uint32_t : 2; 00422 uint32_t core_io_req : 1; 00423 uint32_t : 3; 00424 uint32_t quad_io_req : 1; 00425 uint32_t : 3; 00426 uint32_t fast_mode : 1; 00427 uint32_t : 19; 00428 } mxc_ioman_spis_req_t; 00429 00430 typedef struct { 00431 uint32_t mapping_ack : 2; 00432 uint32_t : 2; 00433 uint32_t core_io_ack : 1; 00434 uint32_t : 3; 00435 uint32_t quad_io_ack : 1; 00436 uint32_t : 3; 00437 uint32_t fast_mode : 1; 00438 uint32_t : 19; 00439 } mxc_ioman_spis_ack_t; 00440 00441 typedef struct { 00442 uint32_t slow_mode : 1; 00443 uint32_t alt_rcvr_mode : 1; 00444 uint32_t : 30; 00445 } mxc_ioman_pad_mode_t; 00446 00447 typedef struct { 00448 uint32_t wud_req_p8 : 2; 00449 uint32_t : 30; 00450 } mxc_ioman_wud_req2_t; 00451 00452 typedef struct { 00453 uint32_t wud_ack_p8 : 2; 00454 uint32_t : 30; 00455 } mxc_ioman_wud_ack2_t; 00456 00457 typedef struct { 00458 uint32_t ali_req_p8 : 2; 00459 uint32_t : 30; 00460 } mxc_ioman_ali_req2_t; 00461 00462 typedef struct { 00463 uint32_t ali_ack_p8 : 2; 00464 uint32_t : 30; 00465 } mxc_ioman_ali_ack2_t; 00466 00467 00468 /* 00469 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit 00470 access to each register in module. 00471 */ 00472 00473 /* Offset Register Description 00474 ============= ============================================================================ */ 00475 typedef struct { 00476 __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 (P0/P1/P2/P3) */ 00477 __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 (P4/P5/P6/P7) */ 00478 __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 (P0/P1/P2/P3) */ 00479 __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 (P4/P5/P6/P7) */ 00480 __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 (P0/P1/P2/P3) */ 00481 __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 (P4/P5/P6/P7) */ 00482 __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 (P0/P1/P2/P3) */ 00483 __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 (P4/P5/P6/P7) */ 00484 __IO uint32_t ali_connect0; /* 0x0020 Analog I/O Connection Control Register 0 */ 00485 __IO uint32_t ali_connect1; /* 0x0024 Analog I/O Connection Control Register 1 */ 00486 __IO uint32_t spix_req; /* 0x0028 SPIX I/O Mode Request */ 00487 __IO uint32_t spix_ack; /* 0x002C SPIX I/O Mode Acknowledge */ 00488 __IO uint32_t uart0_req; /* 0x0030 UART0 I/O Mode Request */ 00489 __IO uint32_t uart0_ack; /* 0x0034 UART0 I/O Mode Acknowledge */ 00490 __IO uint32_t uart1_req; /* 0x0038 UART1 I/O Mode Request */ 00491 __IO uint32_t uart1_ack; /* 0x003C UART1 I/O Mode Acknowledge */ 00492 __IO uint32_t uart2_req; /* 0x0040 UART2 I/O Mode Request */ 00493 __IO uint32_t uart2_ack; /* 0x0044 UART2 I/O Mode Acknowledge */ 00494 __IO uint32_t uart3_req; /* 0x0048 UART3 I/O Mode Request */ 00495 __IO uint32_t uart3_ack; /* 0x004C UART3 I/O Mode Acknowledge */ 00496 __IO uint32_t i2cm0_req; /* 0x0050 I2C Master 0 I/O Request */ 00497 __IO uint32_t i2cm0_ack; /* 0x0054 I2C Master 0 I/O Acknowledge */ 00498 __IO uint32_t i2cm1_req; /* 0x0058 I2C Master 1 I/O Request */ 00499 __IO uint32_t i2cm1_ack; /* 0x005C I2C Master 1 I/O Acknowledge */ 00500 __IO uint32_t i2cm2_req; /* 0x0060 I2C Master 2 I/O Request */ 00501 __IO uint32_t i2cm2_ack; /* 0x0064 I2C Master 2 I/O Acknowledge */ 00502 __IO uint32_t i2cs_req; /* 0x0068 I2C Slave I/O Request */ 00503 __IO uint32_t i2cs_ack; /* 0x006C I2C Slave I/O Acknowledge */ 00504 __IO uint32_t spim0_req; /* 0x0070 SPI Master 0 I/O Mode Request */ 00505 __IO uint32_t spim0_ack; /* 0x0074 SPI Master 0 I/O Mode Acknowledge */ 00506 __IO uint32_t spim1_req; /* 0x0078 SPI Master 1 I/O Mode Request */ 00507 __IO uint32_t spim1_ack; /* 0x007C SPI Master 1 I/O Mode Acknowledge */ 00508 __IO uint32_t spim2_req; /* 0x0080 SPI Master 2 I/O Mode Request */ 00509 __IO uint32_t spim2_ack; /* 0x0084 SPI Master 2 I/O Mode Acknowledge */ 00510 __IO uint32_t spib_req; /* 0x0088 SPI Bridge I/O Mode Request */ 00511 __IO uint32_t spib_ack; /* 0x008C SPI Bridge I/O Mode Acknowledge */ 00512 __IO uint32_t owm_req; /* 0x0090 1-Wire Master I/O Mode Request */ 00513 __IO uint32_t owm_ack; /* 0x0094 1-Wire Master I/O Mode Acknowledge */ 00514 __IO uint32_t spis_req; /* 0x0098 SPI Slave I/O Mode Request */ 00515 __IO uint32_t spis_ack; /* 0x009C SPI Slave I/O Mode Acknowledge */ 00516 __R uint32_t rsv0A0[24]; /* 0x00A0-0x00FC */ 00517 __IO uint32_t use_vddioh_0; /* 0x0100 Enable VDDIOH Register 0 */ 00518 __IO uint32_t use_vddioh_1; /* 0x0104 Enable VDDIOH Register 1 */ 00519 __IO uint32_t use_vddioh_2; /* 0x0108 Enable VDDIOH Register 2 */ 00520 __R uint32_t rsv10C; /* 0x010C */ 00521 __IO uint32_t pad_mode; /* 0x0110 Pad Mode Control Register */ 00522 __R uint32_t rsv114[27]; /* 0x0114-0x017C */ 00523 __IO uint32_t wud_req2; /* 0x0180 Wakeup Detect Mode Request Register 2 (P8) */ 00524 __R uint32_t rsv184; /* 0x0184 */ 00525 __IO uint32_t wud_ack2; /* 0x0188 Wakeup Detect Mode Acknowledge Register 2 (P8) */ 00526 __R uint32_t rsv18C; /* 0x018C */ 00527 __IO uint32_t ali_req2; /* 0x0190 Analog Input Request Register 2 (P8) */ 00528 __R uint32_t rsv194; /* 0x0194 */ 00529 __IO uint32_t ali_ack2; /* 0x0198 Analog Input Acknowledge Register 2 (P8) */ 00530 __R uint32_t rsv19C; /* 0x019C */ 00531 __IO uint32_t ali_connect2; /* 0x01A0 Analog I/O Connection Control Register 2 */ 00532 } mxc_ioman_regs_t; 00533 00534 00535 /* 00536 Register offsets for module IOMAN. 00537 */ 00538 00539 #define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL) 00540 #define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL) 00541 #define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL) 00542 #define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL) 00543 #define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL) 00544 #define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL) 00545 #define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL) 00546 #define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL) 00547 #define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x00000020UL) 00548 #define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000024UL) 00549 #define MXC_R_IOMAN_OFFS_SPIX_REQ ((uint32_t)0x00000028UL) 00550 #define MXC_R_IOMAN_OFFS_SPIX_ACK ((uint32_t)0x0000002CUL) 00551 #define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000030UL) 00552 #define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x00000034UL) 00553 #define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000038UL) 00554 #define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x0000003CUL) 00555 #define MXC_R_IOMAN_OFFS_UART2_REQ ((uint32_t)0x00000040UL) 00556 #define MXC_R_IOMAN_OFFS_UART2_ACK ((uint32_t)0x00000044UL) 00557 #define MXC_R_IOMAN_OFFS_UART3_REQ ((uint32_t)0x00000048UL) 00558 #define MXC_R_IOMAN_OFFS_UART3_ACK ((uint32_t)0x0000004CUL) 00559 #define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000050UL) 00560 #define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x00000054UL) 00561 #define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000058UL) 00562 #define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x0000005CUL) 00563 #define MXC_R_IOMAN_OFFS_I2CM2_REQ ((uint32_t)0x00000060UL) 00564 #define MXC_R_IOMAN_OFFS_I2CM2_ACK ((uint32_t)0x00000064UL) 00565 #define MXC_R_IOMAN_OFFS_I2CS_REQ ((uint32_t)0x00000068UL) 00566 #define MXC_R_IOMAN_OFFS_I2CS_ACK ((uint32_t)0x0000006CUL) 00567 #define MXC_R_IOMAN_OFFS_SPIM0_REQ ((uint32_t)0x00000070UL) 00568 #define MXC_R_IOMAN_OFFS_SPIM0_ACK ((uint32_t)0x00000074UL) 00569 #define MXC_R_IOMAN_OFFS_SPIM1_REQ ((uint32_t)0x00000078UL) 00570 #define MXC_R_IOMAN_OFFS_SPIM1_ACK ((uint32_t)0x0000007CUL) 00571 #define MXC_R_IOMAN_OFFS_SPIM2_REQ ((uint32_t)0x00000080UL) 00572 #define MXC_R_IOMAN_OFFS_SPIM2_ACK ((uint32_t)0x00000084UL) 00573 #define MXC_R_IOMAN_OFFS_SPIB_REQ ((uint32_t)0x00000088UL) 00574 #define MXC_R_IOMAN_OFFS_SPIB_ACK ((uint32_t)0x0000008CUL) 00575 #define MXC_R_IOMAN_OFFS_OWM_REQ ((uint32_t)0x00000090UL) 00576 #define MXC_R_IOMAN_OFFS_OWM_ACK ((uint32_t)0x00000094UL) 00577 #define MXC_R_IOMAN_OFFS_SPIS_REQ ((uint32_t)0x00000098UL) 00578 #define MXC_R_IOMAN_OFFS_SPIS_ACK ((uint32_t)0x0000009CUL) 00579 #define MXC_R_IOMAN_OFFS_USE_VDDIOH_0 ((uint32_t)0x00000100UL) 00580 #define MXC_R_IOMAN_OFFS_USE_VDDIOH_1 ((uint32_t)0x00000104UL) 00581 #define MXC_R_IOMAN_OFFS_USE_VDDIOH_2 ((uint32_t)0x00000108UL) 00582 #define MXC_R_IOMAN_OFFS_PAD_MODE ((uint32_t)0x00000110UL) 00583 #define MXC_R_IOMAN_OFFS_WUD_REQ2 ((uint32_t)0x00000180UL) 00584 #define MXC_R_IOMAN_OFFS_WUD_ACK2 ((uint32_t)0x00000188UL) 00585 #define MXC_R_IOMAN_OFFS_ALI_REQ2 ((uint32_t)0x00000190UL) 00586 #define MXC_R_IOMAN_OFFS_ALI_ACK2 ((uint32_t)0x00000198UL) 00587 #define MXC_R_IOMAN_OFFS_ALI_CONNECT2 ((uint32_t)0x000001A0UL) 00588 00589 00590 /* 00591 Field positions and masks for module IOMAN. 00592 */ 00593 00594 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS 0 00595 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS)) 00596 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS 8 00597 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS)) 00598 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS 16 00599 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS)) 00600 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS 24 00601 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS)) 00602 00603 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS 0 00604 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS)) 00605 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS 8 00606 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS)) 00607 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS 16 00608 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS)) 00609 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7_POS 24 00610 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7_POS)) 00611 00612 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS 0 00613 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS)) 00614 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS 8 00615 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS)) 00616 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS 16 00617 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS)) 00618 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS 24 00619 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS)) 00620 00621 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS 0 00622 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS)) 00623 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS 8 00624 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS)) 00625 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS 16 00626 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS)) 00627 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7_POS 24 00628 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7_POS)) 00629 00630 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS 0 00631 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS)) 00632 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS 8 00633 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS)) 00634 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS 16 00635 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS)) 00636 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS 24 00637 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS)) 00638 00639 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS 0 00640 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS)) 00641 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS 8 00642 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS)) 00643 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS 16 00644 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS)) 00645 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7_POS 24 00646 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7_POS)) 00647 00648 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS 0 00649 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS)) 00650 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS 8 00651 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS)) 00652 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS 16 00653 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS)) 00654 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS 24 00655 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS)) 00656 00657 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS 0 00658 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS)) 00659 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS 8 00660 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS)) 00661 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS 16 00662 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS)) 00663 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7_POS 24 00664 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7_POS)) 00665 00666 #define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS 4 00667 #define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS)) 00668 #define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS 8 00669 #define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS)) 00670 #define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS 9 00671 #define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS)) 00672 #define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS 10 00673 #define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS)) 00674 #define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS 12 00675 #define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS)) 00676 #define MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS 16 00677 #define MXC_F_IOMAN_SPIX_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS)) 00678 00679 #define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS 4 00680 #define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS)) 00681 #define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS 8 00682 #define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS)) 00683 #define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS 9 00684 #define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS)) 00685 #define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS 10 00686 #define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS)) 00687 #define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS 12 00688 #define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS)) 00689 #define MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS 16 00690 #define MXC_F_IOMAN_SPIX_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS)) 00691 00692 #define MXC_F_IOMAN_UART0_REQ_IO_MAP_POS 0 00693 #define MXC_F_IOMAN_UART0_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS)) 00694 #define MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS 1 00695 #define MXC_F_IOMAN_UART0_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS)) 00696 #define MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS 2 00697 #define MXC_F_IOMAN_UART0_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS)) 00698 #define MXC_F_IOMAN_UART0_REQ_IO_REQ_POS 4 00699 #define MXC_F_IOMAN_UART0_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_REQ_POS)) 00700 #define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS 5 00701 #define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS)) 00702 #define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS 6 00703 #define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS)) 00704 00705 #define MXC_F_IOMAN_UART0_ACK_IO_MAP_POS 0 00706 #define MXC_F_IOMAN_UART0_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_MAP_POS)) 00707 #define MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS 1 00708 #define MXC_F_IOMAN_UART0_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS)) 00709 #define MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS 2 00710 #define MXC_F_IOMAN_UART0_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS)) 00711 #define MXC_F_IOMAN_UART0_ACK_IO_ACK_POS 4 00712 #define MXC_F_IOMAN_UART0_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_ACK_POS)) 00713 #define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS 5 00714 #define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS)) 00715 #define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS 6 00716 #define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS)) 00717 00718 #define MXC_F_IOMAN_UART1_REQ_IO_MAP_POS 0 00719 #define MXC_F_IOMAN_UART1_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_MAP_POS)) 00720 #define MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS 1 00721 #define MXC_F_IOMAN_UART1_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS)) 00722 #define MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS 2 00723 #define MXC_F_IOMAN_UART1_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS)) 00724 #define MXC_F_IOMAN_UART1_REQ_IO_REQ_POS 4 00725 #define MXC_F_IOMAN_UART1_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_REQ_POS)) 00726 #define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS 5 00727 #define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS)) 00728 #define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS 6 00729 #define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS)) 00730 00731 #define MXC_F_IOMAN_UART1_ACK_IO_MAP_POS 0 00732 #define MXC_F_IOMAN_UART1_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_MAP_POS)) 00733 #define MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS 1 00734 #define MXC_F_IOMAN_UART1_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS)) 00735 #define MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS 2 00736 #define MXC_F_IOMAN_UART1_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS)) 00737 #define MXC_F_IOMAN_UART1_ACK_IO_ACK_POS 4 00738 #define MXC_F_IOMAN_UART1_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_ACK_POS)) 00739 #define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS 5 00740 #define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS)) 00741 #define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS 6 00742 #define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS)) 00743 00744 #define MXC_F_IOMAN_UART2_REQ_IO_MAP_POS 0 00745 #define MXC_F_IOMAN_UART2_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_MAP_POS)) 00746 #define MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS 1 00747 #define MXC_F_IOMAN_UART2_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS)) 00748 #define MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS 2 00749 #define MXC_F_IOMAN_UART2_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS)) 00750 #define MXC_F_IOMAN_UART2_REQ_IO_REQ_POS 4 00751 #define MXC_F_IOMAN_UART2_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_REQ_POS)) 00752 #define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS 5 00753 #define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS)) 00754 #define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS 6 00755 #define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS)) 00756 00757 #define MXC_F_IOMAN_UART2_ACK_IO_MAP_POS 0 00758 #define MXC_F_IOMAN_UART2_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_MAP_POS)) 00759 #define MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS 1 00760 #define MXC_F_IOMAN_UART2_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS)) 00761 #define MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS 2 00762 #define MXC_F_IOMAN_UART2_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS)) 00763 #define MXC_F_IOMAN_UART2_ACK_IO_ACK_POS 4 00764 #define MXC_F_IOMAN_UART2_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_ACK_POS)) 00765 #define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS 5 00766 #define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS)) 00767 #define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS 6 00768 #define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS)) 00769 00770 #define MXC_F_IOMAN_UART3_REQ_IO_MAP_POS 0 00771 #define MXC_F_IOMAN_UART3_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_MAP_POS)) 00772 #define MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS 1 00773 #define MXC_F_IOMAN_UART3_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS)) 00774 #define MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS 2 00775 #define MXC_F_IOMAN_UART3_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS)) 00776 #define MXC_F_IOMAN_UART3_REQ_IO_REQ_POS 4 00777 #define MXC_F_IOMAN_UART3_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_REQ_POS)) 00778 #define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS 5 00779 #define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS)) 00780 #define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS 6 00781 #define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS)) 00782 00783 #define MXC_F_IOMAN_UART3_ACK_IO_MAP_POS 0 00784 #define MXC_F_IOMAN_UART3_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_MAP_POS)) 00785 #define MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS 1 00786 #define MXC_F_IOMAN_UART3_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS)) 00787 #define MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS 2 00788 #define MXC_F_IOMAN_UART3_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS)) 00789 #define MXC_F_IOMAN_UART3_ACK_IO_ACK_POS 4 00790 #define MXC_F_IOMAN_UART3_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_ACK_POS)) 00791 #define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS 5 00792 #define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS)) 00793 #define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS 6 00794 #define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS)) 00795 00796 #define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS 4 00797 #define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS)) 00798 00799 #define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS 4 00800 #define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS)) 00801 00802 #define MXC_F_IOMAN_I2CM1_REQ_IO_SEL_POS 0 00803 #define MXC_F_IOMAN_I2CM1_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM1_REQ_IO_SEL_POS)) 00804 #define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS 4 00805 #define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS)) 00806 00807 #define MXC_F_IOMAN_I2CM1_ACK_IO_SEL_POS 0 00808 #define MXC_F_IOMAN_I2CM1_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM1_ACK_IO_SEL_POS)) 00809 #define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS 4 00810 #define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS)) 00811 00812 #define MXC_F_IOMAN_I2CM2_REQ_IO_SEL_POS 0 00813 #define MXC_F_IOMAN_I2CM2_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM2_REQ_IO_SEL_POS)) 00814 #define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS 4 00815 #define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS)) 00816 00817 #define MXC_F_IOMAN_I2CM2_ACK_IO_SEL_POS 0 00818 #define MXC_F_IOMAN_I2CM2_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM2_ACK_IO_SEL_POS)) 00819 #define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS 4 00820 #define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS)) 00821 00822 #define MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS 0 00823 #define MXC_F_IOMAN_I2CS_REQ_IO_SEL ((uint32_t)(0x00000007UL << MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS)) 00824 #define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS 4 00825 #define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS)) 00826 00827 #define MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS 0 00828 #define MXC_F_IOMAN_I2CS_ACK_IO_SEL ((uint32_t)(0x00000007UL << MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS)) 00829 #define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS 4 00830 #define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS)) 00831 00832 #define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS 4 00833 #define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS)) 00834 #define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS 8 00835 #define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS)) 00836 #define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS 9 00837 #define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS)) 00838 #define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS 10 00839 #define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS)) 00840 #define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS 11 00841 #define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS)) 00842 #define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS 12 00843 #define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS)) 00844 #define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS 20 00845 #define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS)) 00846 #define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS 24 00847 #define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS)) 00848 00849 #define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS 4 00850 #define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS)) 00851 #define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS 8 00852 #define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS)) 00853 #define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS 9 00854 #define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS)) 00855 #define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS 10 00856 #define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS)) 00857 #define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS 11 00858 #define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS)) 00859 #define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS 12 00860 #define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS)) 00861 #define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS 20 00862 #define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS)) 00863 #define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS 24 00864 #define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS)) 00865 00866 #define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS 4 00867 #define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS)) 00868 #define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS 8 00869 #define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS)) 00870 #define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS 9 00871 #define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS)) 00872 #define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS 10 00873 #define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS)) 00874 #define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS 20 00875 #define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS)) 00876 #define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS 24 00877 #define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS)) 00878 00879 #define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS 4 00880 #define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS)) 00881 #define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS 8 00882 #define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS)) 00883 #define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS 9 00884 #define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS)) 00885 #define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS 10 00886 #define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS)) 00887 #define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS 20 00888 #define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS)) 00889 #define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS 24 00890 #define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS)) 00891 00892 #define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS 0 00893 #define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS)) 00894 #define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS 4 00895 #define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS)) 00896 #define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS 8 00897 #define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS)) 00898 #define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS 9 00899 #define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS)) 00900 #define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS 10 00901 #define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS)) 00902 #define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS 16 00903 #define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS)) 00904 #define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS 17 00905 #define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS)) 00906 #define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS 20 00907 #define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS)) 00908 #define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS 24 00909 #define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS)) 00910 00911 #define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS 0 00912 #define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS)) 00913 #define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS 4 00914 #define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS)) 00915 #define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS 8 00916 #define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS)) 00917 #define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS 9 00918 #define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS)) 00919 #define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS 10 00920 #define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS)) 00921 #define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS 16 00922 #define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS)) 00923 #define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS 17 00924 #define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS)) 00925 #define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS 20 00926 #define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS)) 00927 #define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS 24 00928 #define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS)) 00929 00930 #define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS 4 00931 #define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS)) 00932 #define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS 8 00933 #define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS)) 00934 #define MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS 12 00935 #define MXC_F_IOMAN_SPIB_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS)) 00936 00937 #define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS 4 00938 #define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS)) 00939 #define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS 8 00940 #define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS)) 00941 #define MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS 12 00942 #define MXC_F_IOMAN_SPIB_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS)) 00943 00944 #define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS 4 00945 #define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS)) 00946 #define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS 5 00947 #define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS)) 00948 00949 #define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS 4 00950 #define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS)) 00951 #define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS 5 00952 #define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS)) 00953 00954 #define MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ_POS 0 00955 #define MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ_POS)) 00956 #define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS 4 00957 #define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS)) 00958 #define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS 8 00959 #define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS)) 00960 #define MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS 12 00961 #define MXC_F_IOMAN_SPIS_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS)) 00962 00963 #define MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK_POS 0 00964 #define MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK_POS)) 00965 #define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS 4 00966 #define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS)) 00967 #define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS 8 00968 #define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS)) 00969 #define MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS 12 00970 #define MXC_F_IOMAN_SPIS_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS)) 00971 00972 #define MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS 0 00973 #define MXC_F_IOMAN_PAD_MODE_SLOW_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS)) 00974 #define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS 1 00975 #define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS)) 00976 00977 #define MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8_POS 0 00978 #define MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8_POS)) 00979 00980 #define MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8_POS 0 00981 #define MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8_POS)) 00982 00983 #define MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8_POS 0 00984 #define MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8_POS)) 00985 00986 #define MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8_POS 0 00987 #define MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8_POS)) 00988 00989 00990 00991 #ifdef __cplusplus 00992 } 00993 #endif 00994 00995 #endif /* _MXC_IOMAN_REGS_H_ */
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