icc_regs.h

00001 /*******************************************************************************
00002  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
00003  *
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00005  * copy of this software and associated documentation files (the "Software"),
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00010  *
00011  * The above copyright notice and this permission notice shall be included
00012  * in all copies or substantial portions of the Software.
00013  *
00014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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00021  *
00022  * Except as contained in this notice, the name of Maxim Integrated
00023  * Products, Inc. shall not be used except as stated in the Maxim Integrated
00024  * Products, Inc. Branding Policy.
00025  *
00026  * The mere transfer of this software does not imply any licenses
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00033 
00034 #ifndef _MXC_ICC_REGS_H_
00035 #define _MXC_ICC_REGS_H_
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 #include <stdint.h>
00042 
00043 /*
00044     If types are not defined elsewhere (CMSIS) define them here
00045 */
00046 #ifndef __IO
00047 #define __IO volatile
00048 #endif
00049 #ifndef __I
00050 #define __I  volatile const
00051 #endif
00052 #ifndef __O
00053 #define __O  volatile
00054 #endif
00055 #ifndef __R
00056 #define __R  volatile const
00057 #endif
00058 
00059 
00060 /*
00061    Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
00062    access to each register in module.
00063 */
00064 
00065 /*                                                          Offset          Register Description
00066                                                             =============   ============================================================================ */
00067 typedef struct {
00068     __IO uint32_t id;                                   /*  0x0000          Cache ID Register (INTERNAL USE ONLY)                                        */
00069     __IO uint32_t mem_cfg;                              /*  0x0004          Memory Configuration Register                                                */
00070     __R  uint32_t rsv008[62];                           /*  0x0008-0x00FC                                                                                */
00071     __IO uint32_t ctrl_stat;                            /*  0x0100          Control and Status                                                           */
00072     __R  uint32_t rsv104[383];                          /*  0x0104-0x06FC                                                                                */
00073     __IO uint32_t invdt_all;                            /*  0x0700          Invalidate (Clear) Cache Control                                             */
00074 } mxc_icc_regs_t;
00075 
00076 
00077 /*
00078    Register offsets for module ICC.
00079 */
00080 
00081 #define MXC_R_ICC_OFFS_ID                                   ((uint32_t)0x00000000UL)
00082 #define MXC_R_ICC_OFFS_MEM_CFG                              ((uint32_t)0x00000004UL)
00083 #define MXC_R_ICC_OFFS_CTRL_STAT                            ((uint32_t)0x00000100UL)
00084 #define MXC_R_ICC_OFFS_INVDT_ALL                            ((uint32_t)0x00000700UL)
00085 
00086 
00087 /*
00088    Field positions and masks for module ICC.
00089 */
00090 
00091 #define MXC_F_ICC_ID_RTL_VERSION_POS                        0
00092 #define MXC_F_ICC_ID_RTL_VERSION                            ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS))
00093 #define MXC_F_ICC_ID_PART_NUM_POS                           6
00094 #define MXC_F_ICC_ID_PART_NUM                               ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS))
00095 #define MXC_F_ICC_ID_CACHE_ID_POS                           10
00096 #define MXC_F_ICC_ID_CACHE_ID                               ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS))
00097 
00098 #define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS                    0
00099 #define MXC_F_ICC_MEM_CFG_CACHE_SIZE                        ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS))
00100 #define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS              16
00101 #define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE                  ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS))
00102 
00103 #define MXC_F_ICC_CTRL_STAT_ENABLE_POS                      0
00104 #define MXC_F_ICC_CTRL_STAT_ENABLE                          ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS))
00105 #define MXC_F_ICC_CTRL_STAT_READY_POS                       16
00106 #define MXC_F_ICC_CTRL_STAT_READY                           ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS))
00107 
00108 
00109 
00110 #ifdef __cplusplus
00111 }
00112 #endif
00113 
00114 #endif   /* _MXC_ICC_REGS_H_ */