flc_regs.h

00001 /*******************************************************************************
00002  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
00003  *
00004  * Permission is hereby granted, free of charge, to any person obtaining a
00005  * copy of this software and associated documentation files (the "Software"),
00006  * to deal in the Software without restriction, including without limitation
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00008  * and/or sell copies of the Software, and to permit persons to whom the
00009  * Software is furnished to do so, subject to the following conditions:
00010  *
00011  * The above copyright notice and this permission notice shall be included
00012  * in all copies or substantial portions of the Software.
00013  *
00014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00016  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
00017  * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
00018  * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
00019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
00020  * OTHER DEALINGS IN THE SOFTWARE.
00021  *
00022  * Except as contained in this notice, the name of Maxim Integrated
00023  * Products, Inc. shall not be used except as stated in the Maxim Integrated
00024  * Products, Inc. Branding Policy.
00025  *
00026  * The mere transfer of this software does not imply any licenses
00027  * of trade secrets, proprietary technology, copyrights, patents,
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00033 
00034 #ifndef _MXC_FLC_REGS_H_
00035 #define _MXC_FLC_REGS_H_
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 #include <stdint.h>
00042 
00043 /*
00044     If types are not defined elsewhere (CMSIS) define them here
00045 */
00046 #ifndef __IO
00047 #define __IO volatile
00048 #endif
00049 #ifndef __I
00050 #define __I  volatile const
00051 #endif
00052 #ifndef __O
00053 #define __O  volatile
00054 #endif
00055 #ifndef __R
00056 #define __R  volatile const
00057 #endif
00058 
00059 
00060 #define MXC_V_FLC_ERASE_CODE_PAGE_ERASE   ((uint8_t)0x55)
00061 #define MXC_V_FLC_ERASE_CODE_MASS_ERASE   ((uint8_t)0xAA)
00062 #define MXC_V_FLC_FLSH_UNLOCK_KEY         ((uint8_t)0x2)
00063 
00064 /*
00065    Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
00066    access to each register in module.
00067 */
00068 
00069 /*                                                          Offset          Register Description
00070                                                             =============   ============================================================================ */
00071 typedef struct {
00072     __IO uint32_t faddr;                                /*  0x0000          Flash Operation Address                                                      */
00073     __IO uint32_t fckdiv;                               /*  0x0004          Flash Clock Pulse Divisor                                                    */
00074     __IO uint32_t ctrl;                                 /*  0x0008          Flash Control Register                                                       */
00075     __R  uint32_t rsv00C[6];                            /*  0x000C-0x0020                                                                                */
00076     __IO uint32_t intr;                                 /*  0x0024          Flash Controller Interrupt Flags and Enable/Disable 0                        */
00077     __R  uint32_t rsv028[2];                            /*  0x0028-0x002C                                                                                */
00078     __IO uint32_t fdata;                                /*  0x0030          Flash Operation Data Register                                                */
00079     __R  uint32_t rsv034[7];                            /*  0x0034-0x004C                                                                                */
00080     __IO uint32_t perform;                              /*  0x0050          Flash Performance Settings                                                   */
00081     __IO uint32_t tacc;                                 /*  0x0054          Flash Read Cycle Config                                                      */
00082     __IO uint32_t tprog;                                /*  0x0058          Flash Write Cycle Config                                                     */
00083     __R  uint32_t rsv05C[9];                            /*  0x005C-0x007C                                                                                */
00084     __IO uint32_t status;                               /*  0x0080          Security Status Flags                                                        */
00085     __R  uint32_t rsv084;                               /*  0x0084                                                                                       */
00086     __IO uint32_t security;                             /*  0x0088          Flash Controller Security Settings                                           */
00087     __R  uint32_t rsv08C[4];                            /*  0x008C-0x0098                                                                                */
00088     __IO uint32_t bypass;                               /*  0x009C          Status Flags for DSB Operations                                              */
00089     __R  uint32_t rsv0A0[24];                           /*  0x00A0-0x00FC                                                                                */
00090     __IO uint32_t user_option;                          /*  0x0100          Used to set DSB Access code and Auto-Lock in info block                      */
00091     __R  uint32_t rsv104[15];                           /*  0x0104-0x013C                                                                                */
00092     __IO uint32_t ctrl2;                                /*  0x0140          Flash Control Register 2                                                     */
00093     __IO uint32_t intfl1;                               /*  0x0144          Interrupt Flags Register 1                                                   */
00094     __IO uint32_t inten1;                               /*  0x0148          Interrupt Enable/Disable Register 1                                          */
00095     __R  uint32_t rsv14C[9];                            /*  0x014C-0x016C                                                                                */
00096     __IO uint32_t bl_ctrl;                              /*  0x0170          Bootloader Control Register                                                  */
00097     __IO uint32_t twk;                                  /*  0x0174          PDM33 Register                                                               */
00098     __R  uint32_t rsv178;                               /*  0x0178                                                                                       */
00099     __IO uint32_t slm;                                  /*  0x017C          Sleep Mode Register                                                          */
00100     __R  uint32_t rsv180[32];                           /*  0x0180-0x01FC                                                                                */
00101     __IO uint32_t disable_xr0;                          /*  0x0200          Disable Flash Page Exec/Read Register 0                                      */
00102     __IO uint32_t disable_xr1;                          /*  0x0204          Disable Flash Page Exec/Read Register 1                                      */
00103     __IO uint32_t disable_xr2;                          /*  0x0208          Disable Flash Page Exec/Read Register 2                                      */
00104     __IO uint32_t disable_xr3;                          /*  0x020C          Disable Flash Page Exec/Read Register 3                                      */
00105     __IO uint32_t disable_xr4;                          /*  0x0210          Disable Flash Page Exec/Read Register 4                                      */
00106     __IO uint32_t disable_xr5;                          /*  0x0214          Disable Flash Page Exec/Read Register 5                                      */
00107     __IO uint32_t disable_xr6;                          /*  0x0218          Disable Flash Page Exec/Read Register 6                                      */
00108     __IO uint32_t disable_xr7;                          /*  0x021C          Disable Flash Page Exec/Read Register 7                                      */
00109     __R  uint32_t rsv220[56];                           /*  0x0220-0x02FC                                                                                */
00110     __IO uint32_t disable_we0;                          /*  0x0300          Disable Flash Page Write/Erase Register 0                                    */
00111     __IO uint32_t disable_we1;                          /*  0x0304          Disable Flash Page Write/Erase Register 1                                    */
00112     __IO uint32_t disable_we2;                          /*  0x0308          Disable Flash Page Write/Erase Register 2                                    */
00113     __IO uint32_t disable_we3;                          /*  0x030C          Disable Flash Page Write/Erase Register 3                                    */
00114     __IO uint32_t disable_we4;                          /*  0x0310          Disable Flash Page Write/Erase Register 4                                    */
00115     __IO uint32_t disable_we5;                          /*  0x0314          Disable Flash Page Write/Erase Register 5                                    */
00116     __IO uint32_t disable_we6;                          /*  0x0318          Disable Flash Page Write/Erase Register 6                                    */
00117     __IO uint32_t disable_we7;                          /*  0x031C          Disable Flash Page Write/Erase Register 7                                    */
00118 } mxc_flc_regs_t;
00119 
00120 
00121 /*
00122    Register offsets for module FLC.
00123 */
00124 
00125 #define MXC_R_FLC_OFFS_FADDR                                ((uint32_t)0x00000000UL)
00126 #define MXC_R_FLC_OFFS_FCKDIV                               ((uint32_t)0x00000004UL)
00127 #define MXC_R_FLC_OFFS_CTRL                                 ((uint32_t)0x00000008UL)
00128 #define MXC_R_FLC_OFFS_INTR                                 ((uint32_t)0x00000024UL)
00129 #define MXC_R_FLC_OFFS_FDATA                                ((uint32_t)0x00000030UL)
00130 #define MXC_R_FLC_OFFS_PERFORM                              ((uint32_t)0x00000050UL)
00131 #define MXC_R_FLC_OFFS_TACC                                 ((uint32_t)0x00000054UL)
00132 #define MXC_R_FLC_OFFS_TPROG                                ((uint32_t)0x00000058UL)
00133 #define MXC_R_FLC_OFFS_STATUS                               ((uint32_t)0x00000080UL)
00134 #define MXC_R_FLC_OFFS_SECURITY                             ((uint32_t)0x00000088UL)
00135 #define MXC_R_FLC_OFFS_BYPASS                               ((uint32_t)0x0000009CUL)
00136 #define MXC_R_FLC_OFFS_USER_OPTION                          ((uint32_t)0x00000100UL)
00137 #define MXC_R_FLC_OFFS_CTRL2                                ((uint32_t)0x00000140UL)
00138 #define MXC_R_FLC_OFFS_INTFL1                               ((uint32_t)0x00000144UL)
00139 #define MXC_R_FLC_OFFS_INTEN1                               ((uint32_t)0x00000148UL)
00140 #define MXC_R_FLC_OFFS_BL_CTRL                              ((uint32_t)0x00000170UL)
00141 #define MXC_R_FLC_OFFS_TWK                                  ((uint32_t)0x00000174UL)
00142 #define MXC_R_FLC_OFFS_SLM                                  ((uint32_t)0x0000017CUL)
00143 #define MXC_R_FLC_OFFS_DISABLE_XR0                          ((uint32_t)0x00000200UL)
00144 #define MXC_R_FLC_OFFS_DISABLE_XR1                          ((uint32_t)0x00000204UL)
00145 #define MXC_R_FLC_OFFS_DISABLE_XR2                          ((uint32_t)0x00000208UL)
00146 #define MXC_R_FLC_OFFS_DISABLE_XR3                          ((uint32_t)0x0000020CUL)
00147 #define MXC_R_FLC_OFFS_DISABLE_XR4                          ((uint32_t)0x00000210UL)
00148 #define MXC_R_FLC_OFFS_DISABLE_XR5                          ((uint32_t)0x00000214UL)
00149 #define MXC_R_FLC_OFFS_DISABLE_XR6                          ((uint32_t)0x00000218UL)
00150 #define MXC_R_FLC_OFFS_DISABLE_XR7                          ((uint32_t)0x0000021CUL)
00151 #define MXC_R_FLC_OFFS_DISABLE_WE0                          ((uint32_t)0x00000300UL)
00152 #define MXC_R_FLC_OFFS_DISABLE_WE1                          ((uint32_t)0x00000304UL)
00153 #define MXC_R_FLC_OFFS_DISABLE_WE2                          ((uint32_t)0x00000308UL)
00154 #define MXC_R_FLC_OFFS_DISABLE_WE3                          ((uint32_t)0x0000030CUL)
00155 #define MXC_R_FLC_OFFS_DISABLE_WE4                          ((uint32_t)0x00000310UL)
00156 #define MXC_R_FLC_OFFS_DISABLE_WE5                          ((uint32_t)0x00000314UL)
00157 #define MXC_R_FLC_OFFS_DISABLE_WE6                          ((uint32_t)0x00000318UL)
00158 #define MXC_R_FLC_OFFS_DISABLE_WE7                          ((uint32_t)0x0000031CUL)
00159 
00160 
00161 /*
00162    Field positions and masks for module FLC.
00163 */
00164 
00165 #define MXC_F_FLC_FADDR_FADDR_POS                           0
00166 #define MXC_F_FLC_FADDR_FADDR                               ((uint32_t)(0x003FFFFFUL << MXC_F_FLC_FADDR_FADDR_POS))
00167 
00168 #define MXC_F_FLC_FCKDIV_FCKDIV_POS                         0
00169 #define MXC_F_FLC_FCKDIV_FCKDIV                             ((uint32_t)(0x0000007FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS))
00170 #define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS             16
00171 #define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT                 ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS))
00172 
00173 #define MXC_F_FLC_CTRL_WRITE_POS                            0
00174 #define MXC_F_FLC_CTRL_WRITE                                ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS))
00175 #define MXC_F_FLC_CTRL_MASS_ERASE_POS                       1
00176 #define MXC_F_FLC_CTRL_MASS_ERASE                           ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS))
00177 #define MXC_F_FLC_CTRL_PAGE_ERASE_POS                       2
00178 #define MXC_F_FLC_CTRL_PAGE_ERASE                           ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS))
00179 #define MXC_F_FLC_CTRL_ERASE_CODE_POS                       8
00180 #define MXC_F_FLC_CTRL_ERASE_CODE                           ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS))
00181 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS                16
00182 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK                    ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS))
00183 #define MXC_F_FLC_CTRL_WRITE_ENABLE_POS                     17
00184 #define MXC_F_FLC_CTRL_WRITE_ENABLE                         ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS))
00185 #define MXC_F_FLC_CTRL_PENDING_POS                          24
00186 #define MXC_F_FLC_CTRL_PENDING                              ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS))
00187 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS                 25
00188 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID                     ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS))
00189 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS                  27
00190 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE                      ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS))
00191 #define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS                      28
00192 #define MXC_F_FLC_CTRL_FLSH_UNLOCK                          ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS))
00193 
00194 #define MXC_F_FLC_INTR_FINISHED_IF_POS                      0
00195 #define MXC_F_FLC_INTR_FINISHED_IF                          ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IF_POS))
00196 #define MXC_F_FLC_INTR_FAILED_IF_POS                        1
00197 #define MXC_F_FLC_INTR_FAILED_IF                            ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IF_POS))
00198 #define MXC_F_FLC_INTR_FINISHED_IE_POS                      8
00199 #define MXC_F_FLC_INTR_FINISHED_IE                          ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IE_POS))
00200 #define MXC_F_FLC_INTR_FAILED_IE_POS                        9
00201 #define MXC_F_FLC_INTR_FAILED_IE                            ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IE_POS))
00202 #define MXC_F_FLC_INTR_FAIL_FLAGS_POS                       16
00203 #define MXC_F_FLC_INTR_FAIL_FLAGS                           ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_INTR_FAIL_FLAGS_POS))
00204 
00205 #define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS                   0
00206 #define MXC_F_FLC_PERFORM_DELAY_SE_EN                       ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS))
00207 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS             8
00208 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN                 ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS))
00209 #define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS               12
00210 #define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL                   ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS))
00211 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS              16
00212 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS                  ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS))
00213 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS              20
00214 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS                  ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS))
00215 #define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS             24
00216 #define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT                 ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS))
00217 #define MXC_F_FLC_PERFORM_AUTO_TACC_POS                     28
00218 #define MXC_F_FLC_PERFORM_AUTO_TACC                         ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_TACC_POS))
00219 #define MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS                   29
00220 #define MXC_F_FLC_PERFORM_AUTO_CLKDIV                       ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS))
00221 
00222 #define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS               0
00223 #define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW                   ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS))
00224 #define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS               1
00225 #define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC                   ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS))
00226 #define MXC_F_FLC_STATUS_AUTO_LOCK_POS                      3
00227 #define MXC_F_FLC_STATUS_AUTO_LOCK                          ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS))
00228 #define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS               29
00229 #define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE                   ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS))
00230 #define MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS               30
00231 #define MXC_F_FLC_STATUS_INFO_BLOCK_VALID                   ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS))
00232 
00233 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS                0
00234 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE                    ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS))
00235 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS              8
00236 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK                  ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS))
00237 #define MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS               16
00238 #define MXC_F_FLC_SECURITY_DISABLE_AHB_WR                   ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS))
00239 #define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS            24
00240 #define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK                ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS))
00241 #define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS                28
00242 #define MXC_F_FLC_SECURITY_SECURITY_LOCK                    ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS))
00243 
00244 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS          0
00245 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE              ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS))
00246 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS                1
00247 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE                    ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS))
00248 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS       2
00249 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE           ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS))
00250 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS             3
00251 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE                 ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS))
00252 
00253 #define MXC_F_FLC_CTRL2_FLASH_LVE_POS                       0
00254 #define MXC_F_FLC_CTRL2_FLASH_LVE                           ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FLASH_LVE_POS))
00255 #define MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS                    1
00256 #define MXC_F_FLC_CTRL2_FRC_FCLK1_ON                        ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS))
00257 #define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS             3
00258 #define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES                 ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS))
00259 #define MXC_F_FLC_CTRL2_EN_CHANGE_POS                       4
00260 #define MXC_F_FLC_CTRL2_EN_CHANGE                           ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_CHANGE_POS))
00261 #define MXC_F_FLC_CTRL2_SLOW_CLK_POS                        5
00262 #define MXC_F_FLC_CTRL2_SLOW_CLK                            ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_SLOW_CLK_POS))
00263 #define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS                6
00264 #define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP                    ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS))
00265 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS                 8
00266 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL                     ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS))
00267 
00268 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS              0
00269 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED                  ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS))
00270 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS             1
00271 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR                 ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS))
00272 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS              2
00273 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED                  ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS))
00274 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS               3
00275 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE                   ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS))
00276 #define MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS                 4
00277 #define MXC_F_FLC_INTFL1_FLC_STATE_DONE                     ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS))
00278 #define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS              5
00279 #define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE                  ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS))
00280 
00281 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS              0
00282 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED                  ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS))
00283 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS             1
00284 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR                 ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS))
00285 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS              2
00286 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED                  ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS))
00287 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS               3
00288 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE                   ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS))
00289 #define MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS                 4
00290 #define MXC_F_FLC_INTEN1_FLC_STATE_DONE                     ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS))
00291 #define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS              5
00292 #define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE                  ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS))
00293 
00294 
00295 
00296 #ifdef __cplusplus
00297 }
00298 #endif
00299 
00300 #endif   /* _MXC_FLC_REGS_H_ */