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clkman_regs.h
00001 /******************************************************************************* 00002 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. 00003 * 00004 * Permission is hereby granted, free of charge, to any person obtaining a 00005 * copy of this software and associated documentation files (the "Software"), 00006 * to deal in the Software without restriction, including without limitation 00007 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 00008 * and/or sell copies of the Software, and to permit persons to whom the 00009 * Software is furnished to do so, subject to the following conditions: 00010 * 00011 * The above copyright notice and this permission notice shall be included 00012 * in all copies or substantial portions of the Software. 00013 * 00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 00015 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00016 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 00017 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 00018 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 00019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 00020 * OTHER DEALINGS IN THE SOFTWARE. 00021 * 00022 * Except as contained in this notice, the name of Maxim Integrated 00023 * Products, Inc. shall not be used except as stated in the Maxim Integrated 00024 * Products, Inc. Branding Policy. 00025 * 00026 * The mere transfer of this software does not imply any licenses 00027 * of trade secrets, proprietary technology, copyrights, patents, 00028 * trademarks, maskwork rights, or any other form of intellectual 00029 * property whatsoever. Maxim Integrated Products, Inc. retains all 00030 * ownership rights. 00031 * 00032 ******************************************************************************/ 00033 00034 #ifndef _MXC_CLKMAN_REGS_H_ 00035 #define _MXC_CLKMAN_REGS_H_ 00036 00037 #ifdef __cplusplus 00038 extern "C" { 00039 #endif 00040 00041 #include <stdint.h> 00042 00043 /* 00044 If types are not defined elsewhere (CMSIS) define them here 00045 */ 00046 #ifndef __IO 00047 #define __IO volatile 00048 #endif 00049 #ifndef __I 00050 #define __I volatile const 00051 #endif 00052 #ifndef __O 00053 #define __O volatile 00054 #endif 00055 #ifndef __R 00056 #define __R volatile const 00057 #endif 00058 00059 00060 /* 00061 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit 00062 access to each register in module. 00063 */ 00064 00065 /* Offset Register Description 00066 ============= ============================================================================ */ 00067 typedef struct { 00068 __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */ 00069 __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */ 00070 __IO uint32_t intfl; /* 0x0008 Interrupt Flags */ 00071 __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */ 00072 __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */ 00073 __IO uint32_t i2c_timer_ctrl; /* 0x0014 I2C Timer Control */ 00074 __IO uint32_t cm4_start_clk_en0; /* 0x0018 CM4 Start Clock on Interrupt Enable 0 */ 00075 __IO uint32_t cm4_start_clk_en1; /* 0x001C CM4 Start Clock on Interrupt Enable 1 */ 00076 __IO uint32_t cm4_start_clk_en2; /* 0x0020 CM4 Start Clock on Interrupt Enable 2 */ 00077 __R uint32_t rsv024[7]; /* 0x0024-0x003C */ 00078 __IO uint32_t sys_clk_ctrl_0_cm4; /* 0x0040 Control Settings for CLK0 - Cortex M4 Clock */ 00079 __IO uint32_t sys_clk_ctrl_1_sync; /* 0x0044 Control Settings for CLK1 - Synchronizer Clock */ 00080 __IO uint32_t sys_clk_ctrl_2_spix; /* 0x0048 Control Settings for CLK2 - SPI XIP Clock */ 00081 __IO uint32_t sys_clk_ctrl_3_prng; /* 0x004C Control Settings for CLK3 - PRNG Clock */ 00082 __IO uint32_t sys_clk_ctrl_4_wdt0; /* 0x0050 Control Settings for CLK4 - Watchdog Timer 0 */ 00083 __IO uint32_t sys_clk_ctrl_5_wdt1; /* 0x0054 Control Settings for CLK5 - Watchdog Timer 1 */ 00084 __IO uint32_t sys_clk_ctrl_6_gpio; /* 0x0058 Control Settings for CLK6 - Clock for GPIO Ports */ 00085 __IO uint32_t sys_clk_ctrl_7_pt; /* 0x005C Control Settings for CLK7 - Source Clock for All Pulse Trains */ 00086 __IO uint32_t sys_clk_ctrl_8_uart; /* 0x0060 Control Settings for CLK8 - Source Clock for All UARTs */ 00087 __IO uint32_t sys_clk_ctrl_9_i2cm; /* 0x0064 Control Settings for CLK9 - Source Clock for All I2C Masters */ 00088 __IO uint32_t sys_clk_ctrl_10_i2cs; /* 0x0068 Control Settings for CLK10 - Source Clock for I2C Slave */ 00089 __IO uint32_t sys_clk_ctrl_11_spi0; /* 0x006C Control Settings for CLK11 - SPI Master 0 */ 00090 __IO uint32_t sys_clk_ctrl_12_spi1; /* 0x0070 Control Settings for CLK12 - SPI Master 1 */ 00091 __IO uint32_t sys_clk_ctrl_13_spi2; /* 0x0074 Control Settings for CLK13 - SPI Master 2 */ 00092 __IO uint32_t sys_clk_ctrl_14_spib; /* 0x0078 Control Settings for CLK14 - SPI Bridge Clock */ 00093 __IO uint32_t sys_clk_ctrl_15_owm; /* 0x007C Control Settings for CLK15 - 1-Wire Master Clock */ 00094 __IO uint32_t sys_clk_ctrl_16_spis; /* 0x0080 Control Settings for CLK16 - SPI Slave Clock */ 00095 __R uint32_t rsv084[31]; /* 0x0084-0x00FC */ 00096 __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */ 00097 __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */ 00098 __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */ 00099 __R uint32_t rsv10C[13]; /* 0x010C-0x013C */ 00100 __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */ 00101 __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */ 00102 __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */ 00103 } mxc_clkman_regs_t; 00104 00105 00106 /* 00107 Register offsets for module CLKMAN. 00108 */ 00109 00110 #define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL) 00111 #define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) 00112 #define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL) 00113 #define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL) 00114 #define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL) 00115 #define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000014UL) 00116 #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN0 ((uint32_t)0x00000018UL) 00117 #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN1 ((uint32_t)0x0000001CUL) 00118 #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN2 ((uint32_t)0x00000020UL) 00119 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_0_CM4 ((uint32_t)0x00000040UL) 00120 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_1_SYNC ((uint32_t)0x00000044UL) 00121 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_2_SPIX ((uint32_t)0x00000048UL) 00122 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_3_PRNG ((uint32_t)0x0000004CUL) 00123 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_4_WDT0 ((uint32_t)0x00000050UL) 00124 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_5_WDT1 ((uint32_t)0x00000054UL) 00125 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_6_GPIO ((uint32_t)0x00000058UL) 00126 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_7_PT ((uint32_t)0x0000005CUL) 00127 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_8_UART ((uint32_t)0x00000060UL) 00128 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_9_I2CM ((uint32_t)0x00000064UL) 00129 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_10_I2CS ((uint32_t)0x00000068UL) 00130 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_11_SPI0 ((uint32_t)0x0000006CUL) 00131 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_12_SPI1 ((uint32_t)0x00000070UL) 00132 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_13_SPI2 ((uint32_t)0x00000074UL) 00133 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_14_SPIB ((uint32_t)0x00000078UL) 00134 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_15_OWM ((uint32_t)0x0000007CUL) 00135 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_16_SPIS ((uint32_t)0x00000080UL) 00136 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL) 00137 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL) 00138 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL) 00139 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL) 00140 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL) 00141 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL) 00142 00143 00144 /* 00145 Field positions and masks for module CLKMAN. 00146 */ 00147 00148 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 0 00149 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS)) 00150 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 4 00151 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00152 00153 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 0 00154 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) 00155 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS 4 00156 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS)) 00157 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS 5 00158 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS)) 00159 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS 8 00160 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS)) 00161 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 12 00162 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS)) 00163 #define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS 13 00164 #define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS)) 00165 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS 16 00166 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS)) 00167 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS 17 00168 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) 00169 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS 20 00170 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS)) 00171 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS 21 00172 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) 00173 #define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS 24 00174 #define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS)) 00175 00176 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 0 00177 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS)) 00178 #define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS 1 00179 #define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS)) 00180 00181 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 0 00182 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS)) 00183 #define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS 1 00184 #define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS)) 00185 00186 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0 00187 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS)) 00188 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1 00189 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS)) 00190 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2 00191 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS)) 00192 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3 00193 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS)) 00194 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_LENGTH_POS 4 00195 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_LENGTH ((uint32_t)(0x00000FFFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_LENGTH_POS)) 00196 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16 00197 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x00003FFFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS)) 00198 00199 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0 00200 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS)) 00201 00202 #define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS 0 00203 #define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS)) 00204 00205 #define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS 0 00206 #define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS)) 00207 00208 #define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS 0 00209 #define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS)) 00210 00211 #define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS 0 00212 #define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) 00213 00214 #define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS 0 00215 #define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS)) 00216 00217 #define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS 0 00218 #define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS)) 00219 00220 #define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS 0 00221 #define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS)) 00222 00223 #define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS 0 00224 #define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS)) 00225 00226 #define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS 0 00227 #define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS)) 00228 00229 #define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS 0 00230 #define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS)) 00231 00232 #define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS 0 00233 #define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS)) 00234 00235 #define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS 0 00236 #define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS)) 00237 00238 #define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS 0 00239 #define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS)) 00240 00241 #define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS 0 00242 #define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS)) 00243 00244 #define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS 0 00245 #define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS)) 00246 00247 #define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS 0 00248 #define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS)) 00249 00250 #define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS 0 00251 #define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS)) 00252 00253 #define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS 0 00254 #define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS)) 00255 00256 #define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS 0 00257 #define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS)) 00258 00259 #define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS 0 00260 #define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS)) 00261 00262 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0 00263 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS)) 00264 00265 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS 0 00266 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS)) 00267 00268 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0 00269 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS)) 00270 00271 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS 0 00272 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS)) 00273 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS 2 00274 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS)) 00275 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4 00276 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS)) 00277 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6 00278 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS)) 00279 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8 00280 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS)) 00281 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10 00282 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS)) 00283 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12 00284 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS)) 00285 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS 14 00286 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS)) 00287 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS 16 00288 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS)) 00289 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS 18 00290 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS)) 00291 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS 20 00292 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS)) 00293 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS 22 00294 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS)) 00295 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 24 00296 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS)) 00297 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS 26 00298 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS)) 00299 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS 28 00300 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS)) 00301 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 30 00302 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS)) 00303 00304 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS 0 00305 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS)) 00306 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 2 00307 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS)) 00308 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS 4 00309 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS)) 00310 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS 6 00311 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS)) 00312 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS 8 00313 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS)) 00314 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS 10 00315 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS)) 00316 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS 12 00317 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS)) 00318 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS 14 00319 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS)) 00320 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 16 00321 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS)) 00322 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS 18 00323 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS)) 00324 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS 20 00325 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS)) 00326 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS 22 00327 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS)) 00328 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS 24 00329 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS)) 00330 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26 00331 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS)) 00332 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28 00333 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS)) 00334 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS 30 00335 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS)) 00336 00337 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS 0 00338 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS)) 00339 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS 2 00340 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS)) 00341 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS 4 00342 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS)) 00343 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS 6 00344 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS)) 00345 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS 8 00346 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS)) 00347 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS 10 00348 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS)) 00349 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS 12 00350 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS)) 00351 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS 14 00352 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS)) 00353 00354 00355 00356 /* 00357 Field values and shifted values for module CLKMAN. 00358 */ 00359 00360 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(0x00000000UL)) 00361 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(0x00000001UL)) 00362 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(0x00000002UL)) 00363 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(0x00000003UL)) 00364 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(0x00000004UL)) 00365 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(0x00000005UL)) 00366 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(0x00000006UL)) 00367 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(0x00000007UL)) 00368 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(0x00000008UL)) 00369 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(0x00000009UL)) 00370 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(0x0000000AUL)) 00371 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(0x0000000BUL)) 00372 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(0x0000000CUL)) 00373 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(0x0000000DUL)) 00374 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(0x0000000EUL)) 00375 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(0x0000000FUL)) 00376 00377 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00378 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00379 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00380 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00381 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00382 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00383 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00384 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00385 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00386 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00387 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00388 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00389 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00390 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00391 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00392 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) 00393 00394 #define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(0x00000000UL)) 00395 #define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(0x00000001UL)) 00396 00397 #define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) 00398 #define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) 00399 00400 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(0x00000000UL)) 00401 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL)) 00402 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL)) 00403 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL)) 00404 00405 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) 00406 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) 00407 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) 00408 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) 00409 00410 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(0x00000000UL)) 00411 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL)) 00412 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL)) 00413 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL)) 00414 00415 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) 00416 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) 00417 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) 00418 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) 00419 00420 #define MXC_V_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(0x00000000UL)) 00421 #define MXC_V_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(0x00000001UL)) 00422 #define MXC_V_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(0x00000002UL)) 00423 #define MXC_V_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(0x00000003UL)) 00424 #define MXC_V_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(0x00000004UL)) 00425 #define MXC_V_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(0x00000005UL)) 00426 #define MXC_V_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(0x00000006UL)) 00427 #define MXC_V_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(0x00000007UL)) 00428 #define MXC_V_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(0x00000008UL)) 00429 #define MXC_V_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(0x00000009UL)) 00430 00431 #define MXC_S_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DISABLED << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) 00432 #define MXC_S_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_1 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) 00433 #define MXC_S_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_2 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) 00434 #define MXC_S_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_4 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) 00435 #define MXC_S_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_8 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) 00436 #define MXC_S_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_16 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) 00437 #define MXC_S_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_32 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) 00438 #define MXC_S_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_64 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) 00439 #define MXC_S_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_128 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) 00440 #define MXC_S_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_256 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) 00441 00442 00443 00444 #ifdef __cplusplus 00445 } 00446 #endif 00447 00448 #endif /* _MXC_CLKMAN_REGS_H_ */
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