adc_regs.h

00001 /*******************************************************************************
00002  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
00003  *
00004  * Permission is hereby granted, free of charge, to any person obtaining a
00005  * copy of this software and associated documentation files (the "Software"),
00006  * to deal in the Software without restriction, including without limitation
00007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
00008  * and/or sell copies of the Software, and to permit persons to whom the
00009  * Software is furnished to do so, subject to the following conditions:
00010  *
00011  * The above copyright notice and this permission notice shall be included
00012  * in all copies or substantial portions of the Software.
00013  *
00014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00016  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
00017  * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
00018  * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
00019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
00020  * OTHER DEALINGS IN THE SOFTWARE.
00021  *
00022  * Except as contained in this notice, the name of Maxim Integrated
00023  * Products, Inc. shall not be used except as stated in the Maxim Integrated
00024  * Products, Inc. Branding Policy.
00025  *
00026  * The mere transfer of this software does not imply any licenses
00027  * of trade secrets, proprietary technology, copyrights, patents,
00028  * trademarks, maskwork rights, or any other form of intellectual
00029  * property whatsoever. Maxim Integrated Products, Inc. retains all
00030  * ownership rights.
00031  *
00032  ******************************************************************************/
00033 
00034 #ifndef _MXC_ADC_REGS_H_
00035 #define _MXC_ADC_REGS_H_
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 #include <stdint.h>
00042 
00043 /*
00044     If types are not defined elsewhere (CMSIS) define them here
00045 */
00046 #ifndef __IO
00047 #define __IO volatile
00048 #endif
00049 #ifndef __I
00050 #define __I  volatile const
00051 #endif
00052 #ifndef __O
00053 #define __O  volatile
00054 #endif
00055 #ifndef __R
00056 #define __R  volatile const
00057 #endif
00058 
00059 
00060 /*
00061    Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
00062    access to each register in module.
00063 */
00064 
00065 /*                                                          Offset          Register Description
00066                                                             =============   ============================================================================ */
00067 typedef struct {
00068     __IO uint32_t ctrl;                                 /*  0x0000          ADC Control                                                                  */
00069     __IO uint32_t status;                               /*  0x0004          ADC Status                                                                   */
00070     __IO uint32_t data;                                 /*  0x0008          ADC Output Data                                                              */
00071     __IO uint32_t intr;                                 /*  0x000C          ADC Interrupt Control Register                                               */
00072     __IO uint32_t limit[4];                             /*  0x0010-0x001C   ADC Limit 0..3                                                               */
00073     __IO uint32_t afe_ctrl;                             /*  0x0020          AFE Control Register                                                         */
00074     __IO uint32_t ro_cal0;                              /*  0x0024          RO Trim Calibration Register 0                                               */
00075     __IO uint32_t ro_cal1;                              /*  0x0028          RO Trim Calibration Register 1                                               */
00076     __IO uint32_t ro_cal2;                              /*  0x002C          RO Trim Calibration Register 2                                               */
00077 } mxc_adc_regs_t;
00078 
00079 
00080 /*
00081    Register offsets for module ADC.
00082 */
00083 
00084 #define MXC_R_ADC_OFFS_CTRL                                 ((uint32_t)0x00000000UL)
00085 #define MXC_R_ADC_OFFS_STATUS                               ((uint32_t)0x00000004UL)
00086 #define MXC_R_ADC_OFFS_DATA                                 ((uint32_t)0x00000008UL)
00087 #define MXC_R_ADC_OFFS_INTR                                 ((uint32_t)0x0000000CUL)
00088 #define MXC_R_ADC_OFFS_LIMIT0                               ((uint32_t)0x00000010UL)
00089 #define MXC_R_ADC_OFFS_LIMIT1                               ((uint32_t)0x00000014UL)
00090 #define MXC_R_ADC_OFFS_LIMIT2                               ((uint32_t)0x00000018UL)
00091 #define MXC_R_ADC_OFFS_LIMIT3                               ((uint32_t)0x0000001CUL)
00092 #define MXC_R_ADC_OFFS_AFE_CTRL                             ((uint32_t)0x00000020UL)
00093 #define MXC_R_ADC_OFFS_RO_CAL0                              ((uint32_t)0x00000024UL)
00094 #define MXC_R_ADC_OFFS_RO_CAL1                              ((uint32_t)0x00000028UL)
00095 #define MXC_R_ADC_OFFS_RO_CAL2                              ((uint32_t)0x0000002CUL)
00096 
00097 
00098 /*
00099    Field positions and masks for module ADC.
00100 */
00101 
00102 #define MXC_F_ADC_CTRL_CPU_ADC_START_POS                    0
00103 #define MXC_F_ADC_CTRL_CPU_ADC_START                        ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_CPU_ADC_START_POS))
00104 #define MXC_F_ADC_CTRL_ADC_PU_POS                           1
00105 #define MXC_F_ADC_CTRL_ADC_PU                               ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_PU_POS))
00106 #define MXC_F_ADC_CTRL_BUF_PU_POS                           2
00107 #define MXC_F_ADC_CTRL_BUF_PU                               ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PU_POS))
00108 #define MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS                    3
00109 #define MXC_F_ADC_CTRL_ADC_REFBUF_PU                        ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS))
00110 #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS                   4
00111 #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS))
00112 #define MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS                     5
00113 #define MXC_F_ADC_CTRL_BUF_CHOP_DIS                         ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS))
00114 #define MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS                     6
00115 #define MXC_F_ADC_CTRL_BUF_PUMP_DIS                         ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS))
00116 #define MXC_F_ADC_CTRL_BUF_BYPASS_POS                       7
00117 #define MXC_F_ADC_CTRL_BUF_BYPASS                           ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_BYPASS_POS))
00118 #define MXC_F_ADC_CTRL_ADC_REFSCL_POS                       8
00119 #define MXC_F_ADC_CTRL_ADC_REFSCL                           ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSCL_POS))
00120 #define MXC_F_ADC_CTRL_ADC_SCALE_POS                        9
00121 #define MXC_F_ADC_CTRL_ADC_SCALE                            ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_SCALE_POS))
00122 #define MXC_F_ADC_CTRL_ADC_REFSEL_POS                       10
00123 #define MXC_F_ADC_CTRL_ADC_REFSEL                           ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSEL_POS))
00124 #define MXC_F_ADC_CTRL_ADC_CLK_EN_POS                       11
00125 #define MXC_F_ADC_CTRL_ADC_CLK_EN                           ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CLK_EN_POS))
00126 #define MXC_F_ADC_CTRL_ADC_CHSEL_POS                        12
00127 #define MXC_F_ADC_CTRL_ADC_CHSEL                            ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL_ADC_CHSEL_POS))
00128 
00129 #if (MXC_ADC_REV == 0)
00130 #define MXC_F_ADC_CTRL_ADC_XREF_POS                         16
00131 #define MXC_F_ADC_CTRL_ADC_XREF                             ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_XREF_POS))
00132 #endif
00133 
00134 #define MXC_F_ADC_CTRL_ADC_DATAALIGN_POS                    17
00135 #define MXC_F_ADC_CTRL_ADC_DATAALIGN                        ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_DATAALIGN_POS))
00136 #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS                   24
00137 #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY                       ((uint32_t)(0x000000FFUL << MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS))
00138 
00139 #define MXC_F_ADC_STATUS_ADC_ACTIVE_POS                     0
00140 #define MXC_F_ADC_STATUS_ADC_ACTIVE                         ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_ACTIVE_POS))
00141 #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS           1
00142 #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE               ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS))
00143 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS              2
00144 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE                  ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS))
00145 #define MXC_F_ADC_STATUS_ADC_OVERFLOW_POS                   3
00146 #define MXC_F_ADC_STATUS_ADC_OVERFLOW                       ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_OVERFLOW_POS))
00147 
00148 #define MXC_F_ADC_DATA_ADC_DATA_POS                         0
00149 #define MXC_F_ADC_DATA_ADC_DATA                             ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS))
00150 
00151 #define MXC_F_ADC_INTR_ADC_DONE_IE_POS                      0
00152 #define MXC_F_ADC_INTR_ADC_DONE_IE                          ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IE_POS))
00153 #define MXC_F_ADC_INTR_ADC_REF_READY_IE_POS                 1
00154 #define MXC_F_ADC_INTR_ADC_REF_READY_IE                     ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IE_POS))
00155 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS                  2
00156 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS))
00157 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS                  3
00158 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS))
00159 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS                  4
00160 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS))
00161 #define MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS                   5
00162 #define MXC_F_ADC_INTR_RO_CAL_DONE_IE                       ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS))
00163 #define MXC_F_ADC_INTR_ADC_DONE_IF_POS                      16
00164 #define MXC_F_ADC_INTR_ADC_DONE_IF                          ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IF_POS))
00165 #define MXC_F_ADC_INTR_ADC_REF_READY_IF_POS                 17
00166 #define MXC_F_ADC_INTR_ADC_REF_READY_IF                     ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IF_POS))
00167 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS                  18
00168 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS))
00169 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS                  19
00170 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS))
00171 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS                  20
00172 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS))
00173 #define MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS                   21
00174 #define MXC_F_ADC_INTR_RO_CAL_DONE_IF                       ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS))
00175 #define MXC_F_ADC_INTR_ADC_INT_PENDING_POS                  22
00176 #define MXC_F_ADC_INTR_ADC_INT_PENDING                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_INT_PENDING_POS))
00177 
00178 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS                    0
00179 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT                        ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS))
00180 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS                    12
00181 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT                        ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS))
00182 #define MXC_F_ADC_LIMIT0_CH_SEL_POS                         24
00183 #define MXC_F_ADC_LIMIT0_CH_SEL                             ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT0_CH_SEL_POS))
00184 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS                 28
00185 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN                     ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS))
00186 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS                 29
00187 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN                     ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS))
00188 
00189 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS                    0
00190 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT                        ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS))
00191 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS                    12
00192 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT                        ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS))
00193 #define MXC_F_ADC_LIMIT1_CH_SEL_POS                         24
00194 #define MXC_F_ADC_LIMIT1_CH_SEL                             ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT1_CH_SEL_POS))
00195 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS                 28
00196 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN                     ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS))
00197 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS                 29
00198 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN                     ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS))
00199 
00200 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS                    0
00201 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT                        ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS))
00202 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS                    12
00203 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT                        ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS))
00204 #define MXC_F_ADC_LIMIT2_CH_SEL_POS                         24
00205 #define MXC_F_ADC_LIMIT2_CH_SEL                             ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT2_CH_SEL_POS))
00206 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS                 28
00207 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN                     ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS))
00208 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS                 29
00209 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN                     ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS))
00210 
00211 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS                    0
00212 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT                        ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS))
00213 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS                    12
00214 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT                        ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS))
00215 #define MXC_F_ADC_LIMIT3_CH_SEL_POS                         24
00216 #define MXC_F_ADC_LIMIT3_CH_SEL                             ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT3_CH_SEL_POS))
00217 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS                 28
00218 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN                     ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS))
00219 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS                 29
00220 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN                     ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS))
00221 
00222 #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS              8
00223 #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN                  ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS))
00224 #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS              9
00225 #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN                  ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS))
00226 
00227 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS                     0
00228 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN                         ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
00229 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS                    1
00230 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN                        ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
00231 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS                   2
00232 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD                       ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
00233 #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS                 4
00234 #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC                     ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS))
00235 #define MXC_F_ADC_RO_CAL0_DUMMY_POS                         5
00236 #define MXC_F_ADC_RO_CAL0_DUMMY                             ((uint32_t)(0x00000007UL << MXC_F_ADC_RO_CAL0_DUMMY_POS))
00237 #define MXC_F_ADC_RO_CAL0_TRM_MU_POS                        8
00238 #define MXC_F_ADC_RO_CAL0_TRM_MU                            ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
00239 #define MXC_F_ADC_RO_CAL0_RO_TRM_POS                        23
00240 #define MXC_F_ADC_RO_CAL0_RO_TRM                            ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
00241 
00242 #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS                      0
00243 #define MXC_F_ADC_RO_CAL1_TRM_INIT                          ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
00244 #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS                       10
00245 #define MXC_F_ADC_RO_CAL1_TRM_MIN                           ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
00246 #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS                       20
00247 #define MXC_F_ADC_RO_CAL1_TRM_MAX                           ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
00248 
00249 #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS             0
00250 #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT                 ((uint32_t)(0x000000FFUL << MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS))
00251 
00252 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0                       ((uint32_t)(0x00000000UL))
00253 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1                       ((uint32_t)(0x00000001UL))
00254 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN2                       ((uint32_t)(0x00000002UL))
00255 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN3                       ((uint32_t)(0x00000003UL))
00256 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0_DIV_5                 ((uint32_t)(0x00000004UL))
00257 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1_DIV_5                 ((uint32_t)(0x00000005UL))
00258 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDB_DIV_4                 ((uint32_t)(0x00000006UL))
00259 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDD18                      ((uint32_t)(0x00000007UL))
00260 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDD12                      ((uint32_t)(0x00000008UL))
00261 #define MXC_V_ADC_CTRL_ADC_CHSEL_VRTC_DIV_2                 ((uint32_t)(0x00000009UL))
00262 #define MXC_V_ADC_CTRL_ADC_CHSEL_TMON                       ((uint32_t)(0x0000000AUL))
00263 
00264 #if(MXC_ADC_REV > 0)
00265 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIO_DIV_4                ((uint32_t)(0x0000000BUL))
00266 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIOH_DIV_4               ((uint32_t)(0x0000000CUL))
00267 #endif
00268 
00269 #ifdef __cplusplus
00270 }
00271 #endif
00272 
00273 #endif   /* _MXC_ADC_REGS_H_ */