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m480_sys_reg.h
00001 /**************************************************************************//** 00002 * @file sys_reg.h 00003 * @version V1.00 00004 * @brief SYS register definition header file 00005 * 00006 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. 00007 * 00008 * Redistribution and use in source and binary forms, with or without modification, 00009 * are permitted provided that the following conditions are met: 00010 * 1. Redistributions of source code must retain the above copyright notice, 00011 * this list of conditions and the following disclaimer. 00012 * 2. Redistributions in binary form must reproduce the above copyright notice, 00013 * this list of conditions and the following disclaimer in the documentation 00014 * and/or other materials provided with the distribution. 00015 * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors 00016 * may be used to endorse or promote products derived from this software 00017 * without specific prior written permission. 00018 * 00019 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00020 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00021 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00022 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00023 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00024 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00025 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00026 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00027 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00028 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00029 *****************************************************************************/ 00030 #ifndef __SYS_REG_H__ 00031 #define __SYS_REG_H__ 00032 00033 #if defined ( __CC_ARM ) 00034 #pragma anon_unions 00035 #endif 00036 00037 /** 00038 @addtogroup REGISTER Control Register 00039 @{ 00040 */ 00041 00042 /** 00043 @addtogroup SYS System Manger Controller(SYS) 00044 Memory Mapped Structure for SYS Controller 00045 @{ */ 00046 00047 typedef struct { 00048 00049 00050 /** 00051 * @var SYS_T::PDID 00052 * Offset: 0x00 Part Device Identification Number Register 00053 * --------------------------------------------------------------------------------------------------- 00054 * |Bits |Field |Descriptions 00055 * | :----: | :----: | :---- | 00056 * |[31:0] |PDID |Part Device Identification Number (Read Only) 00057 * | | |This register reflects device part number code 00058 * | | |Software can read this register to identify which device is used. 00059 * @var SYS_T::RSTSTS 00060 * Offset: 0x04 System Reset Status Register 00061 * --------------------------------------------------------------------------------------------------- 00062 * |Bits |Field |Descriptions 00063 * | :----: | :----: | :---- | 00064 * |[0] |PORF |POR Reset Flag 00065 * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. 00066 * | | |0 = No reset from POR or CHIPRST. 00067 * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. 00068 * | | |Note: Write 1 to clear this bit to 0. 00069 * |[1] |PINRF |NRESET Pin Reset Flag 00070 * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source. 00071 * | | |0 = No reset from nRESET pin. 00072 * | | |1 = Pin nRESET had issued the reset signal to reset the system. 00073 * | | |Note: Write 1 to clear this bit to 0. 00074 * |[2] |WDTRF |WDT Reset Flag 00075 * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. 00076 * | | |0 = No reset from watchdog timer or window watchdog timer. 00077 * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. 00078 * | | |Note1: Write 1 to clear this bit to 0. 00079 * | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset 00080 * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. 00081 * |[3] |LVRF |LVR Reset Flag 00082 * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source. 00083 * | | |0 = No reset from LVR. 00084 * | | |1 = LVR controller had issued the reset signal to reset the system. 00085 * | | |Note: Write 1 to clear this bit to 0. 00086 * |[4] |BODRF |BOD Reset Flag 00087 * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out Detector to indicate the previous reset source. 00088 * | | |0 = No reset from BOD. 00089 * | | |1 = The BOD had issued the reset signal to reset the system. 00090 * | | |Note: Write 1 to clear this bit to 0. 00091 * |[5] |SYSRF |System Reset Flag 00092 * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source. 00093 * | | |0 = No reset from Cortex-M4. 00094 * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core. 00095 * | | |Note: Write 1 to clear this bit to 0. 00096 * |[7] |CPURF |CPU Reset Flag 00097 * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC). 00098 * | | |0 = No reset from CPU. 00099 * | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1. 00100 * | | |Note: Write to clear this bit to 0. 00101 * |[8] |CPULKRF |CPU Lock-up Reset Flag 00102 * | | |0 = No reset from CPU lock-up happened. 00103 * | | |1 = The Cortex-M4 lock-up happened and chip is reset. 00104 * | | |Note: Write 1 to clear this bit to 0. 00105 * | | |Note2: When CPU lock-up happened under ICE is connected, This flag will set to 1 but chip will not reset. 00106 * @var SYS_T::IPRST0 00107 * Offset: 0x08 Peripheral Reset Control Register 0 00108 * --------------------------------------------------------------------------------------------------- 00109 * |Bits |Field |Descriptions 00110 * | :----: | :----: | :---- | 00111 * |[0] |CHIPRST |Chip One-shot Reset (Write Protect) 00112 * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. 00113 * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. 00114 * | | |About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2 00115 * | | |0 = Chip normal operation. 00116 * | | |1 = Chip one-shot reset. 00117 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00118 * |[1] |CPURST |Processor Core One-shot Reset (Write Protect) 00119 * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. 00120 * | | |0 = Processor core normal operation. 00121 * | | |1 = Processor core one-shot reset. 00122 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00123 * |[2] |PDMARST |PDMA Controller Reset (Write Protect) 00124 * | | |Setting this bit to 1 will generate a reset signal to the PDMA 00125 * | | |User needs to set this bit to 0 to release from reset state. 00126 * | | |0 = PDMA controller normal operation. 00127 * | | |1 = PDMA controller reset. 00128 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00129 * |[3] |EBIRST |EBI Controller Reset (Write Protect) 00130 * | | |Set this bit to 1 will generate a reset signal to the EBI 00131 * | | |User needs to set this bit to 0 to release from the reset state. 00132 * | | |0 = EBI controller normal operation. 00133 * | | |1 = EBI controller reset. 00134 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00135 * |[5] |EMACRST |EMAC Controller Reset (Write Protect) 00136 * | | |Setting this bit to 1 will generate a reset signal to the EMAC controller 00137 * | | |User needs to set this bit to 0 to release from the reset state. 00138 * | | |0 = EMAC controller normal operation. 00139 * | | |1 = EMAC controller reset. 00140 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00141 * |[6] |SDH0RST |SDHOST0 Controller Reset (Write Protect) 00142 * | | |Setting this bit to 1 will generate a reset signal to the SDHOST0 controller 00143 * | | |User needs to set this bit to 0 to release from the reset state. 00144 * | | |0 = SDHOST0 controller normal operation. 00145 * | | |1 = SDHOST0 controller reset. 00146 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00147 * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect) 00148 * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller 00149 * | | |User needs to set this bit to 0 to release from the reset state. 00150 * | | |0 = CRC calculation controller normal operation. 00151 * | | |1 = CRC calculation controller reset. 00152 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00153 * |[10] |HSUSBDRST |HSUSBD Controller Reset (Write Protect) 00154 * | | |Setting this bit to 1 will generate a reset signal to the HSUSBD controller 00155 * | | |User needs to set this bit to 0 to release from the reset state. 00156 * | | |0 = HSUSBD controller normal operation. 00157 * | | |1 = HSUSBD controller reset. 00158 * |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect) 00159 * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller 00160 * | | |User needs to set this bit to 0 to release from the reset state. 00161 * | | |0 = CRYPTO controller normal operation. 00162 * | | |1 = CRYPTO controller reset. 00163 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00164 * |[14] |SPIMRST |SPIM Controller Reset 00165 * | | |Setting this bit to 1 will generate a reset signal to the SPIM controller 00166 * | | |User needs to set this bit to 0 to release from the reset state. 00167 * | | |0 = SPIM controller normal operation. 00168 * | | |1 = SPIM controller reset. 00169 * |[16] |USBHRST |USBH Controller Reset (Write Protect) 00170 * | | |Set this bit to 1 will generate a reset signal to the USBH controller 00171 * | | |User needs to set this bit to 0 to release from the reset state. 00172 * | | |0 = USBH controller normal operation. 00173 * | | |1 = USBH controller reset. 00174 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00175 * |[17] |SDH1RST |SDHOST1 Controller Reset (Write Protect) 00176 * | | |Setting this bit to 1 will generate a reset signal to the SDHOST1 controller 00177 * | | |User needs to set this bit to 0 to release from the reset state. 00178 * | | |0 = SDHOST1 controller normal operation. 00179 * | | |1 = SDHOST1 controller reset. 00180 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00181 * @var SYS_T::IPRST1 00182 * Offset: 0x0C Peripheral Reset Control Register 1 00183 * --------------------------------------------------------------------------------------------------- 00184 * |Bits |Field |Descriptions 00185 * | :----: | :----: | :---- | 00186 * |[1] |GPIORST |GPIO Controller Reset 00187 * | | |0 = GPIO controller normal operation. 00188 * | | |1 = GPIO controller reset. 00189 * |[2] |TMR0RST |Timer0 Controller Reset 00190 * | | |0 = Timer0 controller normal operation. 00191 * | | |1 = Timer0 controller reset. 00192 * |[3] |TMR1RST |Timer1 Controller Reset 00193 * | | |0 = Timer1 controller normal operation. 00194 * | | |1 = Timer1 controller reset. 00195 * |[4] |TMR2RST |Timer2 Controller Reset 00196 * | | |0 = Timer2 controller normal operation. 00197 * | | |1 = Timer2 controller reset. 00198 * |[5] |TMR3RST |Timer3 Controller Reset 00199 * | | |0 = Timer3 controller normal operation. 00200 * | | |1 = Timer3 controller reset. 00201 * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset 00202 * | | |0 = Analog Comparator 0/1 controller normal operation. 00203 * | | |1 = Analog Comparator 0/1 controller reset. 00204 * |[8] |I2C0RST |I2C0 Controller Reset 00205 * | | |0 = I2C0 controller normal operation. 00206 * | | |1 = I2C0 controller reset. 00207 * |[9] |I2C1RST |I2C1 Controller Reset 00208 * | | |0 = I2C1 controller normal operation. 00209 * | | |1 = I2C1 controller reset. 00210 * |[10] |I2C2RST |I2C2 Controller Reset 00211 * | | |0 = I2C2 controller normal operation. 00212 * | | |1 = I2C2 controller reset. 00213 * |[12] |QSPI0RST |QSPI0 Controller Reset 00214 * | | |0 = QSPI0 controller normal operation. 00215 * | | |1 = QSPI0 controller reset. 00216 * |[13] |SPI0RST |SPI0 Controller Reset 00217 * | | |0 = SPI0 controller normal operation. 00218 * | | |1 = SPI0 controller reset. 00219 * |[14] |SPI1RST |SPI1 Controller Reset 00220 * | | |0 = SPI1 controller normal operation. 00221 * | | |1 = SPI1 controller reset. 00222 * |[15] |SPI2RST |SPI2 Controller Reset 00223 * | | |0 = SPI2 controller normal operation. 00224 * | | |1 = SPI2 controller reset. 00225 * |[16] |UART0RST |UART0 Controller Reset 00226 * | | |0 = UART0 controller normal operation. 00227 * | | |1 = UART0 controller reset. 00228 * |[17] |UART1RST |UART1 Controller Reset 00229 * | | |0 = UART1 controller normal operation. 00230 * | | |1 = UART1 controller reset. 00231 * |[18] |UART2RST |UART2 Controller Reset 00232 * | | |0 = UART2 controller normal operation. 00233 * | | |1 = UART2 controller reset. 00234 * |[19] |UART3RST |UART3 Controller Reset 00235 * | | |0 = UART3 controller normal operation. 00236 * | | |1 = UART3 controller reset. 00237 * |[20] |UART4RST |UART4 Controller Reset 00238 * | | |0 = UART4 controller normal operation. 00239 * | | |1 = UART4 controller reset. 00240 * |[21] |UART5RST |UART5 Controller Reset 00241 * | | |0 = UART5 controller normal operation. 00242 * | | |1 = UART5 controller reset. 00243 * |[24] |CAN0RST |CAN0 Controller Reset 00244 * | | |0 = CAN0 controller normal operation. 00245 * | | |1 = CAN0 controller reset. 00246 * |[25] |CAN1RST |CAN1 Controller Reset 00247 * | | |0 = CAN1 controller normal operation. 00248 * | | |1 = CAN1 controller reset. 00249 * |[27] |USBDRST |USBD Controller Reset 00250 * | | |0 = USBD controller normal operation. 00251 * | | |1 = USBD controller reset. 00252 * |[28] |EADCRST |EADC Controller Reset 00253 * | | |0 = EADC controller normal operation. 00254 * | | |1 = EADC controller reset. 00255 * |[29] |I2S0RST |I2S0 Controller Reset 00256 * | | |0 = I2S0 controller normal operation. 00257 * | | |1 = I2S0 controller reset. 00258 * @var SYS_T::IPRST2 00259 * Offset: 0x10 Peripheral Reset Control Register 2 00260 * --------------------------------------------------------------------------------------------------- 00261 * |Bits |Field |Descriptions 00262 * | :----: | :----: | :---- | 00263 * |[0] |SC0RST |SC0 Controller Reset 00264 * | | |0 = SC0 controller normal operation. 00265 * | | |1 = SC0 controller reset. 00266 * |[1] |SC1RST |SC1 Controller Reset 00267 * | | |0 = SC1 controller normal operation. 00268 * | | |1 = SC1 controller reset. 00269 * |[2] |SC2RST |SC2 Controller Reset 00270 * | | |0 = SC2 controller normal operation. 00271 * | | |1 = SC2 controller reset. 00272 * |[6] |SPI3RST |SPI3 Controller Reset 00273 * | | |0 = SPI3 controller normal operation. 00274 * | | |1 = SPI3 controller reset. 00275 * |[8] |USCI0RST |USCI0 Controller Reset 00276 * | | |0 = USCI0 controller normal operation. 00277 * | | |1 = USCI0 controller reset. 00278 * |[9] |USCI1RST |USCI1 Controller Reset 00279 * | | |0 = USCI1 controller normal operation. 00280 * | | |1 = USCI1 controller reset. 00281 * |[12] |DACRST |DAC Controller Reset 00282 * | | |0 = DAC controller normal operation. 00283 * | | |1 = DAC controller reset. 00284 * |[16] |EPWM0RST |EPWM0 Controller Reset 00285 * | | |0 = EPWM0 controller normal operation. 00286 * | | |1 = EPWM0 controller reset. 00287 * |[17] |EPWM1RST |EPWM1 Controller Reset 00288 * | | |0 = EPWM1 controller normal operation. 00289 * | | |1 = EPWM1 controller reset. 00290 * |[18] |BPWM0RST |BPWM0 Controller Reset 00291 * | | |0 = BPWM0 controller normal operation. 00292 * | | |1 = BPWM0 controller reset. 00293 * |[19] |BPWM1RST |BPWM1 Controller Reset 00294 * | | |0 = BPWM1 controller normal operation. 00295 * | | |1 = BPWM1 controller reset. 00296 * |[22] |QEI0RST |QEI0 Controller Reset 00297 * | | |0 = QEI0 controller normal operation. 00298 * | | |1 = QEI0 controller reset. 00299 * |[23] |QEI1RST |QEI1 Controller Reset 00300 * | | |0 = QEI1 controller normal operation. 00301 * | | |1 = QEI1 controller reset. 00302 * |[26] |ECAP0RST |ECAP0 Controller Reset 00303 * | | |0 = ECAP0 controller normal operation. 00304 * | | |1 = ECAP0 controller reset. 00305 * |[27] |ECAP1RST |ECAP1 Controller Reset 00306 * | | |0 = ECAP1 controller normal operation. 00307 * | | |1 = ECAP1 controller reset. 00308 * |[30] |OPARST |OP Amplifier (OPA) Controller Reset 00309 * | | |0 = OPA controller normal operation. 00310 * | | |1 = OPA controller reset. 00311 * @var SYS_T::BODCTL 00312 * Offset: 0x18 Brown-Out Detector Control Register 00313 * --------------------------------------------------------------------------------------------------- 00314 * |Bits |Field |Descriptions 00315 * | :----: | :----: | :---- | 00316 * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect) 00317 * | | |The default value is set by flash controller user configuration register CBODEN(CONFIG0 [19]). 00318 * | | |0 = Brown-out Detector function Disabled. 00319 * | | |1 = Brown-out Detector function Enabled. 00320 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00321 * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect) 00322 * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit . 00323 * | | |0 = Brown-out INTERRUPT function Enabled. 00324 * | | |1 = Brown-out RESET function Enabled. 00325 * | | |Note1: 00326 * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). 00327 * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high 00328 * | | |BOD interrupt will keep till to the BODEN set to 0 00329 * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). 00330 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 00331 * |[4] |BODIF |Brown-out Detector Interrupt Flag 00332 * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. 00333 * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. 00334 * | | |Note: Write 1 to clear this bit to 0. 00335 * |[5] |BODLPM |Brown-out Detector Low Power Mode (Write Protect) 00336 * | | |0 = BOD operate in normal mode (default). 00337 * | | |1 = BOD Low Power mode Enabled. 00338 * | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. 00339 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 00340 * |[6] |BODOUT |Brown-out Detector Output Status 00341 * | | |0 = Brown-out Detector output status is 0. 00342 * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0. 00343 * | | |1 = Brown-out Detector output status is 1. 00344 * | | |It means the detected voltage is lower than BODVL setting 00345 * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000. 00346 * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect) 00347 * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting 00348 * | | |LVR function is enabled by default. 00349 * | | |0 = Low Voltage Reset function Disabled. 00350 * | | |1 = Low Voltage Reset function Enabled. 00351 * | | |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). 00352 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 00353 * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect) 00354 * | | |000 = BOD output is sampled by RC10K clock. 00355 * | | |001 = 4 system clock (HCLK). 00356 * | | |010 = 8 system clock (HCLK). 00357 * | | |011 = 16 system clock (HCLK). 00358 * | | |100 = 32 system clock (HCLK). 00359 * | | |101 = 64 system clock (HCLK). 00360 * | | |110 = 128 system clock (HCLK). 00361 * | | |111 = 256 system clock (HCLK). 00362 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 00363 * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect) 00364 * | | |000 = Without de-glitch function. 00365 * | | |001 = 4 system clock (HCLK). 00366 * | | |010 = 8 system clock (HCLK). 00367 * | | |011 = 16 system clock (HCLK). 00368 * | | |100 = 32 system clock (HCLK). 00369 * | | |101 = 64 system clock (HCLK). 00370 * | | |110 = 128 system clock (HCLK). 00371 * | | |111 = 256 system clock (HCLK). 00372 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 00373 * |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect) 00374 * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]). 00375 * | | |000 = Brown-Out Detector threshold voltage is 1.6V. 00376 * | | |001 = Brown-Out Detector threshold voltage is 1.8V. 00377 * | | |010 = Brown-Out Detector threshold voltage is 2.0V. 00378 * | | |011 = Brown-Out Detector threshold voltage is 2.2V. 00379 * | | |100 = Brown-Out Detector threshold voltage is 2.4V. 00380 * | | |101 = Brown-Out Detector threshold voltage is 2.6V. 00381 * | | |110 = Brown-Out Detector threshold voltage is 2.8V. 00382 * | | |111 = Brown-Out Detector threshold voltage is 3.0V. 00383 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00384 * @var SYS_T::IVSCTL 00385 * Offset: 0x1C Internal Voltage Source Control Register 00386 * --------------------------------------------------------------------------------------------------- 00387 * |Bits |Field |Descriptions 00388 * | :----: | :----: | :---- | 00389 * |[0] |VTEMPEN |Temperature Sensor Enable Bit 00390 * | | |This bit is used to enable/disable temperature sensor function. 00391 * | | |0 = Temperature sensor function Disabled (default). 00392 * | | |1 = Temperature sensor function Enabled. 00393 * | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained through GPC.9. 00394 * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit 00395 * | | |This bit is used to enable/disable VBAT unity gain buffer function. 00396 * | | |0 = VBAT unity gain buffer function Disabled (default). 00397 * | | |1 = VBAT unity gain buffer function Enabled. 00398 * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result 00399 * @var SYS_T::PORCTL 00400 * Offset: 0x24 Power-On-Reset Controller Register 00401 * --------------------------------------------------------------------------------------------------- 00402 * |Bits |Field |Descriptions 00403 * | :----: | :----: | :---- | 00404 * |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect) 00405 * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again 00406 * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. 00407 * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: 00408 * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. 00409 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00410 * @var SYS_T::VREFCTL 00411 * Offset: 0x28 VREF Control Register 00412 * --------------------------------------------------------------------------------------------------- 00413 * |Bits |Field |Descriptions 00414 * | :----: | :----: | :---- | 00415 * |[4:0] |VREFCTL |VREF Control Bits (Write Protect) 00416 * | | |00000 = VREF is from external pin. 00417 * | | |00011 = VREF is internal 1.6V. 00418 * | | |00111 = VREF is internal 2.0V. 00419 * | | |01011 = VREF is internal 2.5V. 00420 * | | |01111 = VREF is internal 3.0V. 00421 * | | |Others = Reserved. 00422 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00423 * |[7:6] |PRELOAD_SEL|Pre-load Timing Selection. 00424 * | | |00 = pre-load time is 60us for 0.1uF Capacitor. 00425 * | | |01 = pre-load time is 310us for 1uF Capacitor. 00426 * | | |10 = pre-load time is 1270us for 4.7uF Capacitor. 00427 * | | |11 = pre-load time is 2650us for 10uF Capacitor. 00428 * @var SYS_T::USBPHY 00429 * Offset: 0x2C USB PHY Control Register 00430 * --------------------------------------------------------------------------------------------------- 00431 * |Bits |Field |Descriptions 00432 * | :----: | :----: | :---- | 00433 * |[1:0] |USBROLE |USB Role Option (Write Protect) 00434 * | | |These two bits are used to select the role of USB. 00435 * | | |00 = Standard USB Device mode. 00436 * | | |01 = Standard USB Host mode. 00437 * | | |10 = ID dependent mode. 00438 * | | |11 = Reserved. 00439 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00440 * |[2] |SBO |Note: This bit must always be kept 1. If set to 0, the result is unpredictable 00441 * |[8] |USBEN |USB PHY Enable (Write Protect) 00442 * | | |This bit is used to enable/disable USB PHY. 00443 * | | |0 = USB PHY Disabled. 00444 * | | |1 = USB PHY Enabled. 00445 * |[17:16] |HSUSBROLE |HSUSB Role Option (Write Protect) 00446 * | | |These two bits are used to select the role of HSUSB 00447 * | | |00 = Standard HSUSB Device mode. 00448 * | | |01 = Standard HSUSB Host mode. 00449 * | | |10 = ID dependent mode. 00450 * | | |11 = Reserved. 00451 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00452 * |[24] |HSUSBEN |HSUSB PHY Enable (Write Protect) 00453 * | | |This bit is used to enable/disable HSUSB PHY. 00454 * | | |0 = HSUSB PHY Disabled. 00455 * | | |1 = HSUSB PHY Enabled. 00456 * |[25] |HSUSBACT |HSUSB PHY Active Control 00457 * | | |This bit is used to control HSUSB PHY at reset state or active state. 00458 * | | |0 = HSUSB PHY at reset state. 00459 * | | |1 = HSUSB PHY at active state. 00460 * | | |Note: After set HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY, user should keep HSUSB PHY at reset mode at lease 10uS before changing to active mode. 00461 * @var SYS_T::GPA_MFPL 00462 * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register 00463 * --------------------------------------------------------------------------------------------------- 00464 * |Bits |Field |Descriptions 00465 * | :----: | :----: | :---- | 00466 * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection 00467 * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection 00468 * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection 00469 * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection 00470 * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection 00471 * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection 00472 * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection 00473 * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection 00474 * @var SYS_T::GPA_MFPH 00475 * Offset: 0x34 GPIOA High Byte Multiple Function Control Register 00476 * --------------------------------------------------------------------------------------------------- 00477 * |Bits |Field |Descriptions 00478 * | :----: | :----: | :---- | 00479 * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection 00480 * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection 00481 * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection 00482 * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection 00483 * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection 00484 * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection 00485 * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection 00486 * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection 00487 * @var SYS_T::GPB_MFPL 00488 * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register 00489 * --------------------------------------------------------------------------------------------------- 00490 * |Bits |Field |Descriptions 00491 * | :----: | :----: | :---- | 00492 * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection 00493 * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection 00494 * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection 00495 * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection 00496 * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection 00497 * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection 00498 * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection 00499 * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection 00500 * @var SYS_T::GPB_MFPH 00501 * Offset: 0x3C GPIOB High Byte Multiple Function Control Register 00502 * --------------------------------------------------------------------------------------------------- 00503 * |Bits |Field |Descriptions 00504 * | :----: | :----: | :---- | 00505 * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection 00506 * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection 00507 * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection 00508 * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection 00509 * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection 00510 * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection 00511 * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection 00512 * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection 00513 * @var SYS_T::GPC_MFPL 00514 * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register 00515 * --------------------------------------------------------------------------------------------------- 00516 * |Bits |Field |Descriptions 00517 * | :----: | :----: | :---- | 00518 * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection 00519 * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection 00520 * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection 00521 * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection 00522 * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection 00523 * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection 00524 * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection 00525 * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection 00526 * @var SYS_T::GPC_MFPH 00527 * Offset: 0x44 GPIOC High Byte Multiple Function Control Register 00528 * --------------------------------------------------------------------------------------------------- 00529 * |Bits |Field |Descriptions 00530 * | :----: | :----: | :---- | 00531 * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection 00532 * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection 00533 * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection 00534 * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection 00535 * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection 00536 * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection 00537 * |[27:24] |PC14MFP |PC.14 Multi-function Pin Selection 00538 * |[31:28] |PC15MFP |PC.15 Multi-function Pin Selection 00539 * @var SYS_T::GPD_MFPL 00540 * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register 00541 * --------------------------------------------------------------------------------------------------- 00542 * |Bits |Field |Descriptions 00543 * | :----: | :----: | :---- | 00544 * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection 00545 * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection 00546 * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection 00547 * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection 00548 * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection 00549 * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection 00550 * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection 00551 * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection 00552 * @var SYS_T::GPD_MFPH 00553 * Offset: 0x4C GPIOD High Byte Multiple Function Control Register 00554 * --------------------------------------------------------------------------------------------------- 00555 * |Bits |Field |Descriptions 00556 * | :----: | :----: | :---- | 00557 * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection 00558 * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection 00559 * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection 00560 * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection 00561 * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection 00562 * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection 00563 * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection 00564 * |[31:28] |PD15MFP |PD.15 Multi-function Pin Selection 00565 * @var SYS_T::GPE_MFPL 00566 * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register 00567 * --------------------------------------------------------------------------------------------------- 00568 * |Bits |Field |Descriptions 00569 * | :----: | :----: | :---- | 00570 * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection 00571 * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection 00572 * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection 00573 * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection 00574 * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection 00575 * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection 00576 * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection 00577 * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection 00578 * @var SYS_T::GPE_MFPH 00579 * Offset: 0x54 GPIOE High Byte Multiple Function Control Register 00580 * --------------------------------------------------------------------------------------------------- 00581 * |Bits |Field |Descriptions 00582 * | :----: | :----: | :---- | 00583 * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection 00584 * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection 00585 * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection 00586 * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection 00587 * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection 00588 * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection 00589 * |[27:24] |PE14MFP |PE.14 Multi-function Pin Selection 00590 * |[31:28] |PE15MFP |PE.15 Multi-function Pin Selection 00591 * @var SYS_T::GPF_MFPL 00592 * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register 00593 * --------------------------------------------------------------------------------------------------- 00594 * |Bits |Field |Descriptions 00595 * | :----: | :----: | :---- | 00596 * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection 00597 * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection 00598 * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection 00599 * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection 00600 * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection 00601 * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection 00602 * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection 00603 * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection 00604 * @var SYS_T::GPF_MFPH 00605 * Offset: 0x5C GPIOF High Byte Multiple Function Control Register 00606 * --------------------------------------------------------------------------------------------------- 00607 * |Bits |Field |Descriptions 00608 * | :----: | :----: | :---- | 00609 * |[3:0] |PF8MFP |PF.8 Multi-function Pin Selection 00610 * |[7:4] |PF9MFP |PF.9 Multi-function Pin Selection 00611 * |[11:8] |PF10MFP |PF.10 Multi-function Pin Selection 00612 * |[15:12] |PF11MFP |PF.11 Multi-function Pin Selection 00613 * |[19:16] |PF12MFP |PF.12 Multi-function Pin Selection 00614 * |[23:20] |PF13MFP |PF.13 Multi-function Pin Selection 00615 * |[27:24] |PF14MFP |PF.14 Multi-function Pin Selection 00616 * |[31:28] |PF15MFP |PF.15 Multi-function Pin Selection 00617 * @var SYS_T::GPG_MFPL 00618 * Offset: 0x60 GPIOG Low Byte Multiple Function Control Register 00619 * --------------------------------------------------------------------------------------------------- 00620 * |Bits |Field |Descriptions 00621 * | :----: | :----: | :---- | 00622 * |[3:0] |PG0MFP |PG.0 Multi-function Pin Selection 00623 * |[7:4] |PG1MFP |PG.1 Multi-function Pin Selection 00624 * |[11:8] |PG2MFP |PG.2 Multi-function Pin Selection 00625 * |[15:12] |PG3MFP |PG.3 Multi-function Pin Selection 00626 * |[19:16] |PG4MFP |PG.4 Multi-function Pin Selection 00627 * |[23:20] |PG5MFP |PG.5 Multi-function Pin Selection 00628 * |[27:24] |PG6MFP |PG.6 Multi-function Pin Selection 00629 * |[31:28] |PG7MFP |PG.7 Multi-function Pin Selection 00630 * @var SYS_T::GPG_MFPH 00631 * Offset: 0x64 GPIOG High Byte Multiple Function Control Register 00632 * --------------------------------------------------------------------------------------------------- 00633 * |Bits |Field |Descriptions 00634 * | :----: | :----: | :---- | 00635 * |[3:0] |PG8MFP |PG.8 Multi-function Pin Selection 00636 * |[7:4] |PG9MFP |PG.9 Multi-function Pin Selection 00637 * |[11:8] |PG10MFP |PG.10 Multi-function Pin Selection 00638 * |[15:12] |PG11MFP |PG.11 Multi-function Pin Selection 00639 * |[19:16] |PG12MFP |PG.12 Multi-function Pin Selection 00640 * |[23:20] |PG13MFP |PG.13 Multi-function Pin Selection 00641 * |[27:24] |PG14MFP |PG.14 Multi-function Pin Selection 00642 * |[31:28] |PG15MFP |PG.15 Multi-function Pin Selection 00643 * @var SYS_T::GPH_MFPL 00644 * Offset: 0x68 GPIOH Low Byte Multiple Function Control Register 00645 * --------------------------------------------------------------------------------------------------- 00646 * |Bits |Field |Descriptions 00647 * | :----: | :----: | :---- | 00648 * |[3:0] |PH0MFP |PH.0 Multi-function Pin Selection 00649 * |[7:4] |PH1MFP |PH.1 Multi-function Pin Selection 00650 * |[11:8] |PH2MFP |PH.2 Multi-function Pin Selection 00651 * |[15:12] |PH3MFP |PH.3 Multi-function Pin Selection 00652 * |[19:16] |PH4MFP |PH.4 Multi-function Pin Selection 00653 * |[23:20] |PH5MFP |PH.5 Multi-function Pin Selection 00654 * |[27:24] |PH6MFP |PH.6 Multi-function Pin Selection 00655 * |[31:28] |PH7MFP |PH.7 Multi-function Pin Selection 00656 * @var SYS_T::GPH_MFPH 00657 * Offset: 0x6C GPIOH High Byte Multiple Function Control Register 00658 * --------------------------------------------------------------------------------------------------- 00659 * |Bits |Field |Descriptions 00660 * | :----: | :----: | :---- | 00661 * |[3:0] |PH8MFP |PH.8 Multi-function Pin Selection 00662 * |[7:4] |PH9MFP |PH.9 Multi-function Pin Selection 00663 * |[11:8] |PH10MFP |PH.10 Multi-function Pin Selection 00664 * |[15:12] |PH11MFP |PH.11 Multi-function Pin Selection 00665 * |[19:16] |PH12MFP |PH.12 Multi-function Pin Selection 00666 * |[23:20] |PH13MFP |PH.13 Multi-function Pin Selection 00667 * |[27:24] |PH14MFP |PH.14 Multi-function Pin Selection 00668 * |[31:28] |PH15MFP |PH.15 Multi-function Pin Selection 00669 * @var SYS_T::GPA_MFOS 00670 * Offset: 0x80 GPIOA Multiple Function Output Select Register 00671 * --------------------------------------------------------------------------------------------------- 00672 * |Bits |Field |Descriptions 00673 * | :----: | :----: | :---- | 00674 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00675 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00676 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00677 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00678 * | | |Note: 00679 * | | |Max. n=15 for port A/B/E/G. 00680 * | | |Max. n=14 for port C/D. 00681 * | | |Max. n=11 for port F/H. 00682 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00683 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00684 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00685 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00686 * | | |Note: 00687 * | | |Max. n=15 for port A/B/E/G. 00688 * | | |Max. n=14 for port C/D. 00689 * | | |Max. n=11 for port F/H. 00690 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00691 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00692 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00693 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00694 * | | |Note: 00695 * | | |Max. n=15 for port A/B/E/G. 00696 * | | |Max. n=14 for port C/D. 00697 * | | |Max. n=11 for port F/H. 00698 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00699 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00700 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00701 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00702 * | | |Note: 00703 * | | |Max. n=15 for port A/B/E/G. 00704 * | | |Max. n=14 for port C/D. 00705 * | | |Max. n=11 for port F/H. 00706 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00707 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00708 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00709 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00710 * | | |Note: 00711 * | | |Max. n=15 for port A/B/E/G. 00712 * | | |Max. n=14 for port C/D. 00713 * | | |Max. n=11 for port F/H. 00714 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00715 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00716 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00717 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00718 * | | |Note: 00719 * | | |Max. n=15 for port A/B/E/G. 00720 * | | |Max. n=14 for port C/D. 00721 * | | |Max. n=11 for port F/H. 00722 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00723 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00724 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00725 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00726 * | | |Note: 00727 * | | |Max. n=15 for port A/B/E/G. 00728 * | | |Max. n=14 for port C/D. 00729 * | | |Max. n=11 for port F/H. 00730 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00731 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00732 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00733 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00734 * | | |Note: 00735 * | | |Max. n=15 for port A/B/E/G. 00736 * | | |Max. n=14 for port C/D. 00737 * | | |Max. n=11 for port F/H. 00738 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00739 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00740 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00741 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00742 * | | |Note: 00743 * | | |Max. n=15 for port A/B/E/G. 00744 * | | |Max. n=14 for port C/D. 00745 * | | |Max. n=11 for port F/H. 00746 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00747 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00748 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00749 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00750 * | | |Note: 00751 * | | |Max. n=15 for port A/B/E/G. 00752 * | | |Max. n=14 for port C/D. 00753 * | | |Max. n=11 for port F/H. 00754 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00755 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00756 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00757 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00758 * | | |Note: 00759 * | | |Max. n=15 for port A/B/E/G. 00760 * | | |Max. n=14 for port C/D. 00761 * | | |Max. n=11 for port F/H. 00762 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00763 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00764 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00765 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00766 * | | |Note: 00767 * | | |Max. n=15 for port A/B/E/G. 00768 * | | |Max. n=14 for port C/D. 00769 * | | |Max. n=11 for port F/H. 00770 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00771 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00772 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00773 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00774 * | | |Note: 00775 * | | |Max. n=15 for port A/B/E/G. 00776 * | | |Max. n=14 for port C/D. 00777 * | | |Max. n=11 for port F/H. 00778 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00779 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00780 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00781 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00782 * | | |Note: 00783 * | | |Max. n=15 for port A/B/E/G. 00784 * | | |Max. n=14 for port C/D. 00785 * | | |Max. n=11 for port F/H. 00786 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00787 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00788 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00789 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00790 * | | |Note: 00791 * | | |Max. n=15 for port A/B/E/G. 00792 * | | |Max. n=14 for port C/D. 00793 * | | |Max. n=11 for port F/H. 00794 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00795 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00796 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00797 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00798 * | | |Note: 00799 * | | |Max. n=15 for port A/B/E/G. 00800 * | | |Max. n=14 for port C/D. 00801 * | | |Max. n=11 for port F/H. 00802 * @var SYS_T::GPB_MFOS 00803 * Offset: 0x84 GPIOB Multiple Function Output Select Register 00804 * --------------------------------------------------------------------------------------------------- 00805 * |Bits |Field |Descriptions 00806 * | :----: | :----: | :---- | 00807 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00808 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00809 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00810 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00811 * | | |Note: 00812 * | | |Max. n=15 for port A/B/E/G. 00813 * | | |Max. n=14 for port C/D. 00814 * | | |Max. n=11 for port F/H. 00815 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00816 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00817 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00818 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00819 * | | |Note: 00820 * | | |Max. n=15 for port A/B/E/G. 00821 * | | |Max. n=14 for port C/D. 00822 * | | |Max. n=11 for port F/H. 00823 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00824 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00825 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00826 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00827 * | | |Note: 00828 * | | |Max. n=15 for port A/B/E/G. 00829 * | | |Max. n=14 for port C/D. 00830 * | | |Max. n=11 for port F/H. 00831 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00832 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00833 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00834 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00835 * | | |Note: 00836 * | | |Max. n=15 for port A/B/E/G. 00837 * | | |Max. n=14 for port C/D. 00838 * | | |Max. n=11 for port F/H. 00839 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00840 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00841 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00842 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00843 * | | |Note: 00844 * | | |Max. n=15 for port A/B/E/G. 00845 * | | |Max. n=14 for port C/D. 00846 * | | |Max. n=11 for port F/H. 00847 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00848 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00849 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00850 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00851 * | | |Note: 00852 * | | |Max. n=15 for port A/B/E/G. 00853 * | | |Max. n=14 for port C/D. 00854 * | | |Max. n=11 for port F/H. 00855 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00856 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00857 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00858 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00859 * | | |Note: 00860 * | | |Max. n=15 for port A/B/E/G. 00861 * | | |Max. n=14 for port C/D. 00862 * | | |Max. n=11 for port F/H. 00863 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00864 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00865 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00866 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00867 * | | |Note: 00868 * | | |Max. n=15 for port A/B/E/G. 00869 * | | |Max. n=14 for port C/D. 00870 * | | |Max. n=11 for port F/H. 00871 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00872 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00873 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00874 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00875 * | | |Note: 00876 * | | |Max. n=15 for port A/B/E/G. 00877 * | | |Max. n=14 for port C/D. 00878 * | | |Max. n=11 for port F/H. 00879 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00880 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00881 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00882 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00883 * | | |Note: 00884 * | | |Max. n=15 for port A/B/E/G. 00885 * | | |Max. n=14 for port C/D. 00886 * | | |Max. n=11 for port F/H. 00887 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00888 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00889 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00890 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00891 * | | |Note: 00892 * | | |Max. n=15 for port A/B/E/G. 00893 * | | |Max. n=14 for port C/D. 00894 * | | |Max. n=11 for port F/H. 00895 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00896 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00897 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00898 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00899 * | | |Note: 00900 * | | |Max. n=15 for port A/B/E/G. 00901 * | | |Max. n=14 for port C/D. 00902 * | | |Max. n=11 for port F/H. 00903 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00904 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00905 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00906 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00907 * | | |Note: 00908 * | | |Max. n=15 for port A/B/E/G. 00909 * | | |Max. n=14 for port C/D. 00910 * | | |Max. n=11 for port F/H. 00911 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00912 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00913 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00914 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00915 * | | |Note: 00916 * | | |Max. n=15 for port A/B/E/G. 00917 * | | |Max. n=14 for port C/D. 00918 * | | |Max. n=11 for port F/H. 00919 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00920 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00921 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00922 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00923 * | | |Note: 00924 * | | |Max. n=15 for port A/B/E/G. 00925 * | | |Max. n=14 for port C/D. 00926 * | | |Max. n=11 for port F/H. 00927 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00928 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00929 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00930 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00931 * | | |Note: 00932 * | | |Max. n=15 for port A/B/E/G. 00933 * | | |Max. n=14 for port C/D. 00934 * | | |Max. n=11 for port F/H. 00935 * @var SYS_T::GPC_MFOS 00936 * Offset: 0x88 GPIOC Multiple Function Output Select Register 00937 * --------------------------------------------------------------------------------------------------- 00938 * |Bits |Field |Descriptions 00939 * | :----: | :----: | :---- | 00940 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00941 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00942 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00943 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00944 * | | |Note: 00945 * | | |Max. n=15 for port A/B/E/G. 00946 * | | |Max. n=14 for port C/D. 00947 * | | |Max. n=11 for port F/H. 00948 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00949 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00950 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00951 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00952 * | | |Note: 00953 * | | |Max. n=15 for port A/B/E/G. 00954 * | | |Max. n=14 for port C/D. 00955 * | | |Max. n=11 for port F/H. 00956 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00957 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00958 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00959 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00960 * | | |Note: 00961 * | | |Max. n=15 for port A/B/E/G. 00962 * | | |Max. n=14 for port C/D. 00963 * | | |Max. n=11 for port F/H. 00964 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00965 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00966 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00967 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00968 * | | |Note: 00969 * | | |Max. n=15 for port A/B/E/G. 00970 * | | |Max. n=14 for port C/D. 00971 * | | |Max. n=11 for port F/H. 00972 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00973 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00974 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00975 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00976 * | | |Note: 00977 * | | |Max. n=15 for port A/B/E/G. 00978 * | | |Max. n=14 for port C/D. 00979 * | | |Max. n=11 for port F/H. 00980 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00981 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00982 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00983 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00984 * | | |Note: 00985 * | | |Max. n=15 for port A/B/E/G. 00986 * | | |Max. n=14 for port C/D. 00987 * | | |Max. n=11 for port F/H. 00988 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00989 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00990 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00991 * | | |1 = Multiple function pin output mode type is Open-drain mode. 00992 * | | |Note: 00993 * | | |Max. n=15 for port A/B/E/G. 00994 * | | |Max. n=14 for port C/D. 00995 * | | |Max. n=11 for port F/H. 00996 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 00997 * | | |This bit used to select multiple function pin output mode type for Px.n pin 00998 * | | |0 = Multiple function pin output mode type is Push-pull mode. 00999 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01000 * | | |Note: 01001 * | | |Max. n=15 for port A/B/E/G. 01002 * | | |Max. n=14 for port C/D. 01003 * | | |Max. n=11 for port F/H. 01004 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01005 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01006 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01007 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01008 * | | |Note: 01009 * | | |Max. n=15 for port A/B/E/G. 01010 * | | |Max. n=14 for port C/D. 01011 * | | |Max. n=11 for port F/H. 01012 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01013 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01014 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01015 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01016 * | | |Note: 01017 * | | |Max. n=15 for port A/B/E/G. 01018 * | | |Max. n=14 for port C/D. 01019 * | | |Max. n=11 for port F/H. 01020 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01021 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01022 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01023 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01024 * | | |Note: 01025 * | | |Max. n=15 for port A/B/E/G. 01026 * | | |Max. n=14 for port C/D. 01027 * | | |Max. n=11 for port F/H. 01028 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01029 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01030 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01031 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01032 * | | |Note: 01033 * | | |Max. n=15 for port A/B/E/G. 01034 * | | |Max. n=14 for port C/D. 01035 * | | |Max. n=11 for port F/H. 01036 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01037 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01038 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01039 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01040 * | | |Note: 01041 * | | |Max. n=15 for port A/B/E/G. 01042 * | | |Max. n=14 for port C/D. 01043 * | | |Max. n=11 for port F/H. 01044 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01045 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01046 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01047 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01048 * | | |Note: 01049 * | | |Max. n=15 for port A/B/E/G. 01050 * | | |Max. n=14 for port C/D. 01051 * | | |Max. n=11 for port F/H. 01052 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01053 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01054 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01055 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01056 * | | |Note: 01057 * | | |Max. n=15 for port A/B/E/G. 01058 * | | |Max. n=14 for port C/D. 01059 * | | |Max. n=11 for port F/H. 01060 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01061 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01062 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01063 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01064 * | | |Note: 01065 * | | |Max. n=15 for port A/B/E/G. 01066 * | | |Max. n=14 for port C/D. 01067 * | | |Max. n=11 for port F/H. 01068 * @var SYS_T::GPD_MFOS 01069 * Offset: 0x8C GPIOD Multiple Function Output Select Register 01070 * --------------------------------------------------------------------------------------------------- 01071 * |Bits |Field |Descriptions 01072 * | :----: | :----: | :---- | 01073 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01074 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01075 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01076 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01077 * | | |Note: 01078 * | | |Max. n=15 for port A/B/E/G. 01079 * | | |Max. n=14 for port C/D. 01080 * | | |Max. n=11 for port F/H. 01081 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01082 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01083 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01084 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01085 * | | |Note: 01086 * | | |Max. n=15 for port A/B/E/G. 01087 * | | |Max. n=14 for port C/D. 01088 * | | |Max. n=11 for port F/H. 01089 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01090 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01091 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01092 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01093 * | | |Note: 01094 * | | |Max. n=15 for port A/B/E/G. 01095 * | | |Max. n=14 for port C/D. 01096 * | | |Max. n=11 for port F/H. 01097 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01098 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01099 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01100 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01101 * | | |Note: 01102 * | | |Max. n=15 for port A/B/E/G. 01103 * | | |Max. n=14 for port C/D. 01104 * | | |Max. n=11 for port F/H. 01105 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01106 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01107 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01108 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01109 * | | |Note: 01110 * | | |Max. n=15 for port A/B/E/G. 01111 * | | |Max. n=14 for port C/D. 01112 * | | |Max. n=11 for port F/H. 01113 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01114 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01115 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01116 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01117 * | | |Note: 01118 * | | |Max. n=15 for port A/B/E/G. 01119 * | | |Max. n=14 for port C/D. 01120 * | | |Max. n=11 for port F/H. 01121 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01122 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01123 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01124 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01125 * | | |Note: 01126 * | | |Max. n=15 for port A/B/E/G. 01127 * | | |Max. n=14 for port C/D. 01128 * | | |Max. n=11 for port F/H. 01129 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01130 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01131 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01132 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01133 * | | |Note: 01134 * | | |Max. n=15 for port A/B/E/G. 01135 * | | |Max. n=14 for port C/D. 01136 * | | |Max. n=11 for port F/H. 01137 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01138 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01139 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01140 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01141 * | | |Note: 01142 * | | |Max. n=15 for port A/B/E/G. 01143 * | | |Max. n=14 for port C/D. 01144 * | | |Max. n=11 for port F/H. 01145 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01146 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01147 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01148 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01149 * | | |Note: 01150 * | | |Max. n=15 for port A/B/E/G. 01151 * | | |Max. n=14 for port C/D. 01152 * | | |Max. n=11 for port F/H. 01153 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01154 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01155 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01156 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01157 * | | |Note: 01158 * | | |Max. n=15 for port A/B/E/G. 01159 * | | |Max. n=14 for port C/D. 01160 * | | |Max. n=11 for port F/H. 01161 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01162 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01163 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01164 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01165 * | | |Note: 01166 * | | |Max. n=15 for port A/B/E/G. 01167 * | | |Max. n=14 for port C/D. 01168 * | | |Max. n=11 for port F/H. 01169 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01170 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01171 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01172 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01173 * | | |Note: 01174 * | | |Max. n=15 for port A/B/E/G. 01175 * | | |Max. n=14 for port C/D. 01176 * | | |Max. n=11 for port F/H. 01177 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01178 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01179 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01180 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01181 * | | |Note: 01182 * | | |Max. n=15 for port A/B/E/G. 01183 * | | |Max. n=14 for port C/D. 01184 * | | |Max. n=11 for port F/H. 01185 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01186 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01187 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01188 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01189 * | | |Note: 01190 * | | |Max. n=15 for port A/B/E/G. 01191 * | | |Max. n=14 for port C/D. 01192 * | | |Max. n=11 for port F/H. 01193 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01194 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01195 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01196 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01197 * | | |Note: 01198 * | | |Max. n=15 for port A/B/E/G. 01199 * | | |Max. n=14 for port C/D. 01200 * | | |Max. n=11 for port F/H. 01201 * @var SYS_T::GPE_MFOS 01202 * Offset: 0x90 GPIOE Multiple Function Output Select Register 01203 * --------------------------------------------------------------------------------------------------- 01204 * |Bits |Field |Descriptions 01205 * | :----: | :----: | :---- | 01206 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01207 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01208 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01209 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01210 * | | |Note: 01211 * | | |Max. n=15 for port A/B/E/G. 01212 * | | |Max. n=14 for port C/D. 01213 * | | |Max. n=11 for port F/H. 01214 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01215 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01216 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01217 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01218 * | | |Note: 01219 * | | |Max. n=15 for port A/B/E/G. 01220 * | | |Max. n=14 for port C/D. 01221 * | | |Max. n=11 for port F/H. 01222 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01223 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01224 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01225 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01226 * | | |Note: 01227 * | | |Max. n=15 for port A/B/E/G. 01228 * | | |Max. n=14 for port C/D. 01229 * | | |Max. n=11 for port F/H. 01230 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01231 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01232 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01233 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01234 * | | |Note: 01235 * | | |Max. n=15 for port A/B/E/G. 01236 * | | |Max. n=14 for port C/D. 01237 * | | |Max. n=11 for port F/H. 01238 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01239 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01240 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01241 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01242 * | | |Note: 01243 * | | |Max. n=15 for port A/B/E/G. 01244 * | | |Max. n=14 for port C/D. 01245 * | | |Max. n=11 for port F/H. 01246 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01247 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01248 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01249 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01250 * | | |Note: 01251 * | | |Max. n=15 for port A/B/E/G. 01252 * | | |Max. n=14 for port C/D. 01253 * | | |Max. n=11 for port F/H. 01254 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01255 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01256 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01257 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01258 * | | |Note: 01259 * | | |Max. n=15 for port A/B/E/G. 01260 * | | |Max. n=14 for port C/D. 01261 * | | |Max. n=11 for port F/H. 01262 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01263 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01264 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01265 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01266 * | | |Note: 01267 * | | |Max. n=15 for port A/B/E/G. 01268 * | | |Max. n=14 for port C/D. 01269 * | | |Max. n=11 for port F/H. 01270 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01271 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01272 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01273 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01274 * | | |Note: 01275 * | | |Max. n=15 for port A/B/E/G. 01276 * | | |Max. n=14 for port C/D. 01277 * | | |Max. n=11 for port F/H. 01278 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01279 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01280 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01281 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01282 * | | |Note: 01283 * | | |Max. n=15 for port A/B/E/G. 01284 * | | |Max. n=14 for port C/D. 01285 * | | |Max. n=11 for port F/H. 01286 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01287 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01288 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01289 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01290 * | | |Note: 01291 * | | |Max. n=15 for port A/B/E/G. 01292 * | | |Max. n=14 for port C/D. 01293 * | | |Max. n=11 for port F/H. 01294 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01295 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01296 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01297 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01298 * | | |Note: 01299 * | | |Max. n=15 for port A/B/E/G. 01300 * | | |Max. n=14 for port C/D. 01301 * | | |Max. n=11 for port F/H. 01302 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01303 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01304 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01305 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01306 * | | |Note: 01307 * | | |Max. n=15 for port A/B/E/G. 01308 * | | |Max. n=14 for port C/D. 01309 * | | |Max. n=11 for port F/H. 01310 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01311 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01312 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01313 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01314 * | | |Note: 01315 * | | |Max. n=15 for port A/B/E/G. 01316 * | | |Max. n=14 for port C/D. 01317 * | | |Max. n=11 for port F/H. 01318 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01319 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01320 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01321 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01322 * | | |Note: 01323 * | | |Max. n=15 for port A/B/E/G. 01324 * | | |Max. n=14 for port C/D. 01325 * | | |Max. n=11 for port F/H. 01326 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01327 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01328 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01329 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01330 * | | |Note: 01331 * | | |Max. n=15 for port A/B/E/G. 01332 * | | |Max. n=14 for port C/D. 01333 * | | |Max. n=11 for port F/H. 01334 * @var SYS_T::GPF_MFOS 01335 * Offset: 0x94 GPIOF Multiple Function Output Select Register 01336 * --------------------------------------------------------------------------------------------------- 01337 * |Bits |Field |Descriptions 01338 * | :----: | :----: | :---- | 01339 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01340 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01341 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01342 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01343 * | | |Note: 01344 * | | |Max. n=15 for port A/B/E/G. 01345 * | | |Max. n=14 for port C/D. 01346 * | | |Max. n=11 for port F/H. 01347 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01348 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01349 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01350 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01351 * | | |Note: 01352 * | | |Max. n=15 for port A/B/E/G. 01353 * | | |Max. n=14 for port C/D. 01354 * | | |Max. n=11 for port F/H. 01355 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01356 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01357 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01358 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01359 * | | |Note: 01360 * | | |Max. n=15 for port A/B/E/G. 01361 * | | |Max. n=14 for port C/D. 01362 * | | |Max. n=11 for port F/H. 01363 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01364 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01365 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01366 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01367 * | | |Note: 01368 * | | |Max. n=15 for port A/B/E/G. 01369 * | | |Max. n=14 for port C/D. 01370 * | | |Max. n=11 for port F/H. 01371 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01372 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01373 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01374 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01375 * | | |Note: 01376 * | | |Max. n=15 for port A/B/E/G. 01377 * | | |Max. n=14 for port C/D. 01378 * | | |Max. n=11 for port F/H. 01379 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01380 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01381 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01382 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01383 * | | |Note: 01384 * | | |Max. n=15 for port A/B/E/G. 01385 * | | |Max. n=14 for port C/D. 01386 * | | |Max. n=11 for port F/H. 01387 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01388 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01389 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01390 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01391 * | | |Note: 01392 * | | |Max. n=15 for port A/B/E/G. 01393 * | | |Max. n=14 for port C/D. 01394 * | | |Max. n=11 for port F/H. 01395 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01396 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01397 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01398 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01399 * | | |Note: 01400 * | | |Max. n=15 for port A/B/E/G. 01401 * | | |Max. n=14 for port C/D. 01402 * | | |Max. n=11 for port F/H. 01403 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01404 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01405 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01406 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01407 * | | |Note: 01408 * | | |Max. n=15 for port A/B/E/G. 01409 * | | |Max. n=14 for port C/D. 01410 * | | |Max. n=11 for port F/H. 01411 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01412 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01413 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01414 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01415 * | | |Note: 01416 * | | |Max. n=15 for port A/B/E/G. 01417 * | | |Max. n=14 for port C/D. 01418 * | | |Max. n=11 for port F/H. 01419 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01420 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01421 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01422 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01423 * | | |Note: 01424 * | | |Max. n=15 for port A/B/E/G. 01425 * | | |Max. n=14 for port C/D. 01426 * | | |Max. n=11 for port F/H. 01427 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01428 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01429 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01430 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01431 * | | |Note: 01432 * | | |Max. n=15 for port A/B/E/G. 01433 * | | |Max. n=14 for port C/D. 01434 * | | |Max. n=11 for port F/H. 01435 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01436 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01437 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01438 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01439 * | | |Note: 01440 * | | |Max. n=15 for port A/B/E/G. 01441 * | | |Max. n=14 for port C/D. 01442 * | | |Max. n=11 for port F/H. 01443 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01444 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01445 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01446 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01447 * | | |Note: 01448 * | | |Max. n=15 for port A/B/E/G. 01449 * | | |Max. n=14 for port C/D. 01450 * | | |Max. n=11 for port F/H. 01451 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01452 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01453 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01454 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01455 * | | |Note: 01456 * | | |Max. n=15 for port A/B/E/G. 01457 * | | |Max. n=14 for port C/D. 01458 * | | |Max. n=11 for port F/H. 01459 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01460 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01461 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01462 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01463 * | | |Note: 01464 * | | |Max. n=15 for port A/B/E/G. 01465 * | | |Max. n=14 for port C/D. 01466 * | | |Max. n=11 for port F/H. 01467 * @var SYS_T::GPG_MFOS 01468 * Offset: 0x98 GPIOG Multiple Function Output Select Register 01469 * --------------------------------------------------------------------------------------------------- 01470 * |Bits |Field |Descriptions 01471 * | :----: | :----: | :---- | 01472 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01473 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01474 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01475 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01476 * | | |Note: 01477 * | | |Max. n=15 for port A/B/E/G. 01478 * | | |Max. n=14 for port C/D. 01479 * | | |Max. n=11 for port F/H. 01480 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01481 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01482 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01483 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01484 * | | |Note: 01485 * | | |Max. n=15 for port A/B/E/G. 01486 * | | |Max. n=14 for port C/D. 01487 * | | |Max. n=11 for port F/H. 01488 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01489 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01490 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01491 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01492 * | | |Note: 01493 * | | |Max. n=15 for port A/B/E/G. 01494 * | | |Max. n=14 for port C/D. 01495 * | | |Max. n=11 for port F/H. 01496 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01497 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01498 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01499 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01500 * | | |Note: 01501 * | | |Max. n=15 for port A/B/E/G. 01502 * | | |Max. n=14 for port C/D. 01503 * | | |Max. n=11 for port F/H. 01504 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01505 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01506 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01507 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01508 * | | |Note: 01509 * | | |Max. n=15 for port A/B/E/G. 01510 * | | |Max. n=14 for port C/D. 01511 * | | |Max. n=11 for port F/H. 01512 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01513 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01514 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01515 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01516 * | | |Note: 01517 * | | |Max. n=15 for port A/B/E/G. 01518 * | | |Max. n=14 for port C/D. 01519 * | | |Max. n=11 for port F/H. 01520 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01521 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01522 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01523 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01524 * | | |Note: 01525 * | | |Max. n=15 for port A/B/E/G. 01526 * | | |Max. n=14 for port C/D. 01527 * | | |Max. n=11 for port F/H. 01528 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01529 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01530 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01531 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01532 * | | |Note: 01533 * | | |Max. n=15 for port A/B/E/G. 01534 * | | |Max. n=14 for port C/D. 01535 * | | |Max. n=11 for port F/H. 01536 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01537 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01538 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01539 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01540 * | | |Note: 01541 * | | |Max. n=15 for port A/B/E/G. 01542 * | | |Max. n=14 for port C/D. 01543 * | | |Max. n=11 for port F/H. 01544 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01545 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01546 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01547 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01548 * | | |Note: 01549 * | | |Max. n=15 for port A/B/E/G. 01550 * | | |Max. n=14 for port C/D. 01551 * | | |Max. n=11 for port F/H. 01552 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01553 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01554 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01555 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01556 * | | |Note: 01557 * | | |Max. n=15 for port A/B/E/G. 01558 * | | |Max. n=14 for port C/D. 01559 * | | |Max. n=11 for port F/H. 01560 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01561 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01562 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01563 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01564 * | | |Note: 01565 * | | |Max. n=15 for port A/B/E/G. 01566 * | | |Max. n=14 for port C/D. 01567 * | | |Max. n=11 for port F/H. 01568 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01569 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01570 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01571 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01572 * | | |Note: 01573 * | | |Max. n=15 for port A/B/E/G. 01574 * | | |Max. n=14 for port C/D. 01575 * | | |Max. n=11 for port F/H. 01576 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01577 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01578 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01579 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01580 * | | |Note: 01581 * | | |Max. n=15 for port A/B/E/G. 01582 * | | |Max. n=14 for port C/D. 01583 * | | |Max. n=11 for port F/H. 01584 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01585 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01586 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01587 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01588 * | | |Note: 01589 * | | |Max. n=15 for port A/B/E/G. 01590 * | | |Max. n=14 for port C/D. 01591 * | | |Max. n=11 for port F/H. 01592 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01593 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01594 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01595 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01596 * | | |Note: 01597 * | | |Max. n=15 for port A/B/E/G. 01598 * | | |Max. n=14 for port C/D. 01599 * | | |Max. n=11 for port F/H. 01600 * @var SYS_T::GPH_MFOS 01601 * Offset: 0x9C GPIOH Multiple Function Output Select Register 01602 * --------------------------------------------------------------------------------------------------- 01603 * |Bits |Field |Descriptions 01604 * | :----: | :----: | :---- | 01605 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01606 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01607 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01608 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01609 * | | |Note: 01610 * | | |Max. n=15 for port A/B/E/G. 01611 * | | |Max. n=14 for port C/D. 01612 * | | |Max. n=11 for port F/H. 01613 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01614 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01615 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01616 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01617 * | | |Note: 01618 * | | |Max. n=15 for port A/B/E/G. 01619 * | | |Max. n=14 for port C/D. 01620 * | | |Max. n=11 for port F/H. 01621 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01622 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01623 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01624 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01625 * | | |Note: 01626 * | | |Max. n=15 for port A/B/E/G. 01627 * | | |Max. n=14 for port C/D. 01628 * | | |Max. n=11 for port F/H. 01629 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01630 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01631 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01632 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01633 * | | |Note: 01634 * | | |Max. n=15 for port A/B/E/G. 01635 * | | |Max. n=14 for port C/D. 01636 * | | |Max. n=11 for port F/H. 01637 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01638 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01639 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01640 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01641 * | | |Note: 01642 * | | |Max. n=15 for port A/B/E/G. 01643 * | | |Max. n=14 for port C/D. 01644 * | | |Max. n=11 for port F/H. 01645 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01646 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01647 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01648 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01649 * | | |Note: 01650 * | | |Max. n=15 for port A/B/E/G. 01651 * | | |Max. n=14 for port C/D. 01652 * | | |Max. n=11 for port F/H. 01653 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01654 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01655 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01656 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01657 * | | |Note: 01658 * | | |Max. n=15 for port A/B/E/G. 01659 * | | |Max. n=14 for port C/D. 01660 * | | |Max. n=11 for port F/H. 01661 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01662 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01663 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01664 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01665 * | | |Note: 01666 * | | |Max. n=15 for port A/B/E/G. 01667 * | | |Max. n=14 for port C/D. 01668 * | | |Max. n=11 for port F/H. 01669 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01670 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01671 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01672 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01673 * | | |Note: 01674 * | | |Max. n=15 for port A/B/E/G. 01675 * | | |Max. n=14 for port C/D. 01676 * | | |Max. n=11 for port F/H. 01677 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01678 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01679 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01680 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01681 * | | |Note: 01682 * | | |Max. n=15 for port A/B/E/G. 01683 * | | |Max. n=14 for port C/D. 01684 * | | |Max. n=11 for port F/H. 01685 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01686 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01687 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01688 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01689 * | | |Note: 01690 * | | |Max. n=15 for port A/B/E/G. 01691 * | | |Max. n=14 for port C/D. 01692 * | | |Max. n=11 for port F/H. 01693 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01694 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01695 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01696 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01697 * | | |Note: 01698 * | | |Max. n=15 for port A/B/E/G. 01699 * | | |Max. n=14 for port C/D. 01700 * | | |Max. n=11 for port F/H. 01701 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01702 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01703 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01704 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01705 * | | |Note: 01706 * | | |Max. n=15 for port A/B/E/G. 01707 * | | |Max. n=14 for port C/D. 01708 * | | |Max. n=11 for port F/H. 01709 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01710 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01711 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01712 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01713 * | | |Note: 01714 * | | |Max. n=15 for port A/B/E/G. 01715 * | | |Max. n=14 for port C/D. 01716 * | | |Max. n=11 for port F/H. 01717 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01718 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01719 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01720 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01721 * | | |Note: 01722 * | | |Max. n=15 for port A/B/E/G. 01723 * | | |Max. n=14 for port C/D. 01724 * | | |Max. n=11 for port F/H. 01725 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 01726 * | | |This bit used to select multiple function pin output mode type for Px.n pin 01727 * | | |0 = Multiple function pin output mode type is Push-pull mode. 01728 * | | |1 = Multiple function pin output mode type is Open-drain mode. 01729 * | | |Note: 01730 * | | |Max. n=15 for port A/B/E/G. 01731 * | | |Max. n=14 for port C/D. 01732 * | | |Max. n=11 for port F/H. 01733 * @var SYS_T::SRAM_INTCTL 01734 * Offset: 0xC0 System SRAM Interrupt Enable Control Register 01735 * --------------------------------------------------------------------------------------------------- 01736 * |Bits |Field |Descriptions 01737 * | :----: | :----: | :---- | 01738 * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit 01739 * | | |0 = SRAM parity check error interrupt Disabled. 01740 * | | |1 = SRAM parity check error interrupt Enabled. 01741 * @var SYS_T::SRAM_STATUS 01742 * Offset: 0xC4 System SRAM Parity Error Status Register 01743 * --------------------------------------------------------------------------------------------------- 01744 * |Bits |Field |Descriptions 01745 * | :----: | :----: | :---- | 01746 * |[0] |PERRIF |SRAM Parity Check Error Flag 01747 * | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0. 01748 * | | |0 = No System SRAM parity error. 01749 * | | |1 = System SRAM parity error occur. 01750 * @var SYS_T::SRAM_ERRADDR 01751 * Offset: 0xC8 System SRAM Parity Check Error Address Register 01752 * --------------------------------------------------------------------------------------------------- 01753 * |Bits |Field |Descriptions 01754 * | :----: | :----: | :---- | 01755 * |[31:0] |ERRADDR |System SRAM Parity Error Address 01756 * | | |This register shows system SRAM parity error byte address. 01757 * @var SYS_T::SRAM_BISTCTL 01758 * Offset: 0xD0 System SRAM BIST Test Control Register 01759 * --------------------------------------------------------------------------------------------------- 01760 * |Bits |Field |Descriptions 01761 * | :----: | :----: | :---- | 01762 * |[0] |SRBIST0 |SRAM Bank0 BIST Enable Bit (Write Protect) 01763 * | | |This bit enables BIST test for SRAM bank0. 01764 * | | |0 = system SRAM bank0 BIST Disabled. 01765 * | | |1 = system SRAM bank0 BIST Enabled. 01766 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01767 * |[1] |SRBIST1 |SRAM Bank1 BIST Enable Bit (Write Protect) 01768 * | | |This bit enables BIST test for SRAM bank1. 01769 * | | |0 = system SRAM bank1 BIST Disabled. 01770 * | | |1 = system SRAM bank1 BIST Enabled. 01771 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01772 * |[2] |CRBIST |CACHE BIST Enable Bit (Write Protect) 01773 * | | |This bit enables BIST test for CACHE RAM 01774 * | | |0 = system CACHE BIST Disabled. 01775 * | | |1 = system CACHE BIST Enabled. 01776 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01777 * |[3] |CANBIST |CAN BIST Enable Bit (Write Protect) 01778 * | | |This bit enables BIST test for CAN RAM 01779 * | | |0 = system CAN BIST Disabled. 01780 * | | |1 = system CAN BIST Enabled. 01781 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01782 * |[4] |USBBIST |USB BIST Enable Bit (Write Protect) 01783 * | | |This bit enables BIST test for USB RAM 01784 * | | |0 = system USB BIST Disabled. 01785 * | | |1 = system USB BIST Enabled. 01786 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01787 * |[5] |SPIMBIST |SPIM BIST Enable Bit (Write Protect) 01788 * | | |This bit enables BIST test for SPIM RAM 01789 * | | |0 = system SPIM BIST Disabled. 01790 * | | |1 = system SPIM BIST Enabled. 01791 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01792 * |[6] |EMCBIST |EMC BIST Enable Bit (Write Protect) 01793 * | | |This bit enables BIST test for EMC RAM 01794 * | | |0 = system EMC BIST Disabled. 01795 * | | |1 = system EMC BIST Enabled. 01796 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01797 * |[7] |PDMABIST |PDMA BIST Enable Bit (Write Protect) 01798 * | | |This bit enables BIST test for PDMA RAM 01799 * | | |0 = system PDMA BIST Disabled. 01800 * | | |1 = system PDMA BIST Enabled. 01801 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01802 * |[8] |HSUSBDBIST|HSUSBD BIST Enable Bit (Write Protect) 01803 * | | |This bit enables BIST test for HSUSBD RAM 01804 * | | |0 = system HSUSBD BIST Disabled. 01805 * | | |1 = system HSUSBD BIST Enabled. 01806 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01807 * |[9] |HSUSBHBIST|HSUSBH BIST Enable Bit (Write Protect) 01808 * | | |This bit enables BIST test for HSUSBH RAM 01809 * | | |0 = system HSUSBH BIST Disabled. 01810 * | | |1 = system HSUSBH BIST Enabled. 01811 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01812 * |[16] |SRB0S0 |SRAM Bank0 Section 0 BIST Select (Write Protect) 01813 * | | |This bit define if the first 16KB section of SRAM bank0 is selected or not when doing bist test. 01814 * | | |0 = SRAM bank0 section 0 is deselected when doing bist test. 01815 * | | |1 = SRAM bank0 section 0 is selected when doing bist test. 01816 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01817 * | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test. 01818 * |[17] |SRB0S1 |SRAM Bank0 Section 1 BIST Select (Write Protect) 01819 * | | |This bit define if the second 16KB section of SRAM bank0 is selected or not when doing bist test. 01820 * | | |0 = SRAM bank0 section 1 is deselected when doing bist test. 01821 * | | |1 = SRAM bank0 section 1 is selected when doing bist test. 01822 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01823 * | | |Note: At least one section of SRAM bank0 should be selected when doing SRAM bank0 bist test. 01824 * |[18] |SRB1S0 |SRAM Bank1 Section 0 BIST Select (Write Protect) 01825 * | | |This bit define if the first 16KB section of SRAM bank1 is selected or not when doing bist test. 01826 * | | |0 = SRAM bank1 first 16KB section is deselected when doing bist test. 01827 * | | |1 = SRAM bank1 first 16KB section is selected when doing bist test. 01828 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01829 * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. 01830 * |[19] |SRB1S1 |SRAM Bank1 Section 1 BIST Select (Write Protect) 01831 * | | |This bit define if the second 16KB section of SRAM bank1 is selected or not when doing bist test. 01832 * | | |0 = SRAM bank1 second 16KB section is deselected when doing bist test. 01833 * | | |1 = SRAM bank1 second 16KB section is selected when doing bist test. 01834 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01835 * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. 01836 * |[20] |SRB1S2 |SRAM Bank1 Section 0 BIST Select (Write Protect) 01837 * | | |This bit define if the third 16KB section of SRAM bank1 is selected or not when doing bist test. 01838 * | | |0 = SRAM bank1 third 16KB section is deselected when doing bist test. 01839 * | | |1 = SRAM bank1 third 16KB section is selected when doing bist test. 01840 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01841 * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. 01842 * |[21] |SRB1S3 |SRAM Bank1 Section 1 BIST Select (Write Protect) 01843 * | | |This bit define if the fourth 16KB section of SRAM bank1 is selected or not when doing bist test. 01844 * | | |0 = SRAM bank1 fourth 16KB section is deselected when doing bist test. 01845 * | | |1 = SRAM bank1 fourth 16KB section is selected when doing bist test. 01846 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01847 * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. 01848 * |[22] |SRB1S4 |SRAM Bank1 Section 0 BIST Select (Write Protect) 01849 * | | |This bit define if the fifth 16KB section of SRAM bank1 is selected or not when doing bist test. 01850 * | | |0 = SRAM bank1 fifth 16KB section is deselected when doing bist test. 01851 * | | |1 = SRAM bank1 fifth 16KB section is selected when doing bist test. 01852 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01853 * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. 01854 * |[23] |SRB1S5 |SRAM Bank1 Section 1 BIST Select (Write Protect) 01855 * | | |This bit define if the sixth 16KB section of SRAM bank1 is selected or not when doing bist test. 01856 * | | |0 = SRAM bank1 sixth 16KB section is deselected when doing bist test. 01857 * | | |1 = SRAM bank1 sixth 16KB section is selected when doing bist test. 01858 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 01859 * | | |Note: At least one section of SRAM bank1 should be selected when doing SRAM bank1 bist test. 01860 * @var SYS_T::SRAM_BISTSTS 01861 * Offset: 0xD4 System SRAM BIST Test Status Register 01862 * --------------------------------------------------------------------------------------------------- 01863 * |Bits |Field |Descriptions 01864 * | :----: | :----: | :---- | 01865 * |[0] |SRBISTEF0 |1st System SRAM BIST Fail Flag 01866 * | | |0 = 1st system SRAM BIST test pass. 01867 * | | |1 = 1st system SRAM BIST test fail. 01868 * |[1] |SRBISTEF1 |2nd System SRAM BIST Fail Flag 01869 * | | |0 = 2nd system SRAM BIST test pass. 01870 * | | |1 = 2nd system SRAM BIST test fail. 01871 * |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag 01872 * | | |0 = System CACHE RAM BIST test pass. 01873 * | | |1 = System CACHE RAM BIST test fail. 01874 * |[3] |CANBEF |CAN SRAM BIST Fail Flag 01875 * | | |0 = CAN SRAM BIST test pass. 01876 * | | |1 = CAN SRAM BIST test fail. 01877 * |[4] |USBBEF |USB SRAM BIST Fail Flag 01878 * | | |0 = USB SRAM BIST test pass. 01879 * | | |1 = USB SRAM BIST test fail. 01880 * |[16] |SRBEND0 |1st SRAM BIST Test Finish 01881 * | | |0 = 1st system SRAM BIST active. 01882 * | | |1 =1st system SRAM BIST finish. 01883 * |[17] |SRBEND1 |2nd SRAM BIST Test Finish 01884 * | | |0 = 2nd system SRAM BIST is active. 01885 * | | |1 = 2nd system SRAM BIST finish. 01886 * |[18] |CRBEND |CACHE SRAM BIST Test Finish 01887 * | | |0 = System CACHE RAM BIST is active. 01888 * | | |1 = System CACHE RAM BIST test finish. 01889 * |[19] |CANBEND |CAN SRAM BIST Test Finish 01890 * | | |0 = CAN SRAM BIST is active. 01891 * | | |1 = CAN SRAM BIST test finish. 01892 * |[20] |USBBEND |USB SRAM BIST Test Finish 01893 * | | |0 = USB SRAM BIST is active. 01894 * | | |1 = USB SRAM BIST test finish. 01895 * @var SYS_T::IRCTCTL 01896 * Offset: 0xF0 HIRC Trim Control Register 01897 * --------------------------------------------------------------------------------------------------- 01898 * |Bits |Field |Descriptions 01899 * | :----: | :----: | :---- | 01900 * |[1:0] |FREQSEL |Trim Frequency Selection 01901 * | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim. 01902 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 01903 * | | |00 = Disable HIRC auto trim function. 01904 * | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz. 01905 * | | |10 = Reserved.. 01906 * | | |11 = Reserved. 01907 * |[5:4] |LOOPSEL |Trim Calculation Loop Selection 01908 * | | |This field defines that trim value calculation is based on how many reference clocks. 01909 * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. 01910 * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. 01911 * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. 01912 * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. 01913 * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 01914 * |[7:6] |RETRYCNT |Trim Value Update Limitation Count 01915 * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. 01916 * | | |Once the HIRC locked, the internal trim value update counter will be reset. 01917 * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 01918 * | | |00 = Trim retry count limitation is 64 loops. 01919 * | | |01 = Trim retry count limitation is 128 loops. 01920 * | | |10 = Trim retry count limitation is 256 loops. 01921 * | | |11 = Trim retry count limitation is 512 loops. 01922 * |[8] |CESTOPEN |Clock Error Stop Enable Bit 01923 * | | |0 = The trim operation is keep going if clock is inaccuracy. 01924 * | | |1 = The trim operation is stopped if clock is inaccuracy. 01925 * |[10] |REFCKSEL |Reference Clock Selection 01926 * | | |0 = HIRC trim reference from external 32.768 kHz crystal oscillator. 01927 * | | |1 = HIRC trim reference from internal USB synchronous mode. 01928 * | | |Note: HIRC trim reference clock is 20Khz in test mode. 01929 * @var SYS_T::IRCTIEN 01930 * Offset: 0xF4 HIRC Trim Interrupt Enable Register 01931 * --------------------------------------------------------------------------------------------------- 01932 * |Bits |Field |Descriptions 01933 * | :----: | :----: | :---- | 01934 * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit 01935 * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]). 01936 * | | |If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 01937 * | | |0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. 01938 * | | |1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. 01939 * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit 01940 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. 01941 * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 01942 * | | |0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. 01943 * | | |1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. 01944 * @var SYS_T::IRCTISTS 01945 * Offset: 0xF8 HIRC Trim Interrupt Status Register 01946 * --------------------------------------------------------------------------------------------------- 01947 * |Bits |Field |Descriptions 01948 * | :----: | :----: | :---- | 01949 * |[0] |FREQLOCK |HIRC Frequency Lock Status 01950 * | | |This bit indicates the HIRC frequency is locked. 01951 * | | |This is a status bit and doesn't trigger any interrupt 01952 * | | |Write 1 to clear this to 0 01953 * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. 01954 * | | |0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet. 01955 * | | |1 = The internal high-speed oscillator frequency locked at 12 MHz. 01956 * |[1] |TFAILIF |Trim Failure Interrupt Status 01957 * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked 01958 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically. 01959 * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached 01960 * | | |Write 1 to clear this to 0. 01961 * | | |0 = Trim value update limitation count does not reach. 01962 * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. 01963 * |[2] |CLKERRIF |Clock Error Interrupt Status 01964 * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. 01965 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1. 01966 * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. 01967 * | | |Write 1 to clear this to 0. 01968 * | | |0 = Clock frequency is accuracy. 01969 * | | |1 = Clock frequency is inaccuracy. 01970 * @var SYS_T::REGLCTL 01971 * Offset: 0x100 Register Lock Control Register 01972 * --------------------------------------------------------------------------------------------------- 01973 * |Bits |Field |Descriptions 01974 * | :----: | :----: | :---- | 01975 * |[7:0] |REGLCTL |Register Lock Control Code 01976 * | | |Some registers have write-protection function 01977 * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field. 01978 * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. 01979 * | | |Register Lock Control Code 01980 * | | |0 = Write-protection Enabled for writing protected registers 01981 * | | |Any write to the protected register is ignored. 01982 * | | |1 = Write-protection Disabled for writing protected registers. 01983 * @var SYS_T::PLCTL 01984 * Offset: 0x1F8 Power Level Control Register 01985 * --------------------------------------------------------------------------------------------------- 01986 * |Bits |Field |Descriptions 01987 * | :----: | :----: | :---- | 01988 * |[1:0] |PLSEL |Power Level Select(Write Protect) 01989 * | | |00 = Power level is PL0. 01990 * | | |01 = Power level is PL1. 01991 * | | |Others = Reserved. 01992 * |[21:16] |LVSSTEP |LDO Voltage Scaling Step(Write Protect) 01993 * | | |The LVSSTEP value is LDO voltage rising step. 01994 * | | |Core voltage scaling voltage step = (LVSSTEP + 1) * 10mV. 01995 * |[31:24] |LVSPRD |LDO Voltage Scaling Period(Write Protect) 01996 * | | |The LVSPRD value is the period of each LDO voltage rising step. 01997 * | | |LDO voltage scaling period = (LVSPRD + 1) * 1us. 01998 * @var SYS_T::PLSTS 01999 * Offset: 0x1FC Power Level Status Register 02000 * --------------------------------------------------------------------------------------------------- 02001 * |Bits |Field |Descriptions 02002 * | :----: | :----: | :---- | 02003 * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only) 02004 * | | |This bit is set by hardware when core voltage is changing 02005 * | | |After core voltage change is completed, this bit will be cleared automatically by hardware. 02006 * | | |0 = Core voltage change is completed. 02007 * | | |1 = Core voltage change is ongoing. 02008 * |[9:8] |PLSTATUS |Power Level Status (Read Only) 02009 * | | |00 = Power level is PL0. 02010 * | | |01 = Power level is PL1. 02011 * | | |Others = Reserved. 02012 * @var SYS_T::AHBMCTL 02013 * Offset: 0x400 AHB Bus Matrix Priority Control Register 02014 * --------------------------------------------------------------------------------------------------- 02015 * |Bits |Field |Descriptions 02016 * | :----: | :----: | :---- | 02017 * |[0] |INTACTEN |Highest AHB Bus Priority of Cortex M4 Core Enable Bit (Write Protect) 02018 * | | |Enable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix 02019 * | | |0 = Run robin mode. 02020 * | | |1 = Cortex-M4 CPU with highest bus priority when interrupt occurred. 02021 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 02022 */ 02023 __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */ 02024 __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */ 02025 __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */ 02026 __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */ 02027 __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */ 02028 /** @cond HIDDEN_SYMBOLS */ 02029 __I uint32_t RESERVE0[1]; 02030 /** @endcond */ 02031 __IO uint32_t BODCTL; /*!< [0x0018] Brown-Out Detector Control Register */ 02032 __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */ 02033 /** @cond HIDDEN_SYMBOLS */ 02034 __I uint32_t RESERVE1[1]; 02035 /** @endcond */ 02036 __IO uint32_t PORCTL; /*!< [0x0024] Power-On-Reset Controller Register */ 02037 __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */ 02038 __IO uint32_t USBPHY; /*!< [0x002c] USB PHY Control Register */ 02039 __IO uint32_t GPA_MFPL; /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register */ 02040 __IO uint32_t GPA_MFPH; /*!< [0x0034] GPIOA High Byte Multiple Function Control Register */ 02041 __IO uint32_t GPB_MFPL; /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register */ 02042 __IO uint32_t GPB_MFPH; /*!< [0x003c] GPIOB High Byte Multiple Function Control Register */ 02043 __IO uint32_t GPC_MFPL; /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register */ 02044 __IO uint32_t GPC_MFPH; /*!< [0x0044] GPIOC High Byte Multiple Function Control Register */ 02045 __IO uint32_t GPD_MFPL; /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register */ 02046 __IO uint32_t GPD_MFPH; /*!< [0x004c] GPIOD High Byte Multiple Function Control Register */ 02047 __IO uint32_t GPE_MFPL; /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register */ 02048 __IO uint32_t GPE_MFPH; /*!< [0x0054] GPIOE High Byte Multiple Function Control Register */ 02049 __IO uint32_t GPF_MFPL; /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register */ 02050 __IO uint32_t GPF_MFPH; /*!< [0x005c] GPIOF High Byte Multiple Function Control Register */ 02051 __IO uint32_t GPG_MFPL; /*!< [0x0060] GPIOG Low Byte Multiple Function Control Register */ 02052 __IO uint32_t GPG_MFPH; /*!< [0x0064] GPIOG High Byte Multiple Function Control Register */ 02053 __IO uint32_t GPH_MFPL; /*!< [0x0068] GPIOH Low Byte Multiple Function Control Register */ 02054 __IO uint32_t GPH_MFPH; /*!< [0x006c] GPIOH High Byte Multiple Function Control Register */ 02055 /** @cond HIDDEN_SYMBOLS */ 02056 __I uint32_t RESERVE2[4]; 02057 /** @endcond */ 02058 __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */ 02059 __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */ 02060 __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */ 02061 __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */ 02062 __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */ 02063 __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */ 02064 __IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */ 02065 __IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */ 02066 /** @cond HIDDEN_SYMBOLS */ 02067 __I uint32_t RESERVE3[8]; 02068 /** @endcond */ 02069 __IO uint32_t SRAM_INTCTL; /*!< [0x00c0] System SRAM Interrupt Enable Control Register */ 02070 __IO uint32_t SRAM_STATUS; /*!< [0x00c4] System SRAM Parity Error Status Register */ 02071 __I uint32_t SRAM_ERRADDR; /*!< [0x00c8] System SRAM Parity Check Error Address Register */ 02072 /** @cond HIDDEN_SYMBOLS */ 02073 __I uint32_t RESERVE4[1]; 02074 /** @endcond */ 02075 __IO uint32_t SRAM_BISTCTL; /*!< [0x00d0] System SRAM BIST Test Control Register */ 02076 __I uint32_t SRAM_BISTSTS; /*!< [0x00d4] System SRAM BIST Test Status Register */ 02077 /** @cond HIDDEN_SYMBOLS */ 02078 __I uint32_t RESERVE5[6]; 02079 /** @endcond */ 02080 __IO uint32_t IRCTCTL; /*!< [0x00f0] HIRC Trim Control Register */ 02081 __IO uint32_t IRCTIEN; /*!< [0x00f4] HIRC Trim Interrupt Enable Register */ 02082 __IO uint32_t IRCTISTS; /*!< [0x00f8] HIRC Trim Interrupt Status Register */ 02083 /** @cond HIDDEN_SYMBOLS */ 02084 __I uint32_t RESERVE6[1]; 02085 /** @endcond */ 02086 __IO uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */ 02087 /** @cond HIDDEN_SYMBOLS */ 02088 __I uint32_t RESERVE7[61]; 02089 /** @endcond */ 02090 __IO uint32_t PLCTL; /*!< [0x01f8] Power Level Control Register */ 02091 __I uint32_t PLSTS; /*!< [0x01fc] Power Level Status Register */ 02092 /** @cond HIDDEN_SYMBOLS */ 02093 __I uint32_t RESERVE8[128]; 02094 /** @endcond */ 02095 __IO uint32_t AHBMCTL; /*!< [0x0400] AHB Bus Matrix Priority Control Register */ 02096 02097 } SYS_T; 02098 02099 /** 02100 @addtogroup SYS_CONST SYS Bit Field Definition 02101 Constant Definitions for SYS Controller 02102 @{ */ 02103 02104 #define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */ 02105 #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */ 02106 02107 #define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */ 02108 #define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */ 02109 02110 #define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */ 02111 #define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */ 02112 02113 #define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */ 02114 #define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */ 02115 02116 #define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */ 02117 #define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */ 02118 02119 #define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */ 02120 #define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */ 02121 02122 #define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */ 02123 #define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */ 02124 02125 #define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */ 02126 #define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */ 02127 02128 #define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */ 02129 #define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */ 02130 02131 #define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */ 02132 #define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */ 02133 02134 #define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */ 02135 #define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */ 02136 02137 #define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS_T::IPRST0: PDMARST Position */ 02138 #define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS_T::IPRST0: PDMARST Mask */ 02139 02140 #define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */ 02141 #define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */ 02142 02143 #define SYS_IPRST0_EMACRST_Pos (5) /*!< SYS_T::IPRST0: EMACRST Position */ 02144 #define SYS_IPRST0_EMACRST_Msk (0x1ul << SYS_IPRST0_EMACRST_Pos) /*!< SYS_T::IPRST0: EMACRST Mask */ 02145 02146 #define SYS_IPRST0_SDH0RST_Pos (6) /*!< SYS_T::IPRST0: SDH0RST Position */ 02147 #define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */ 02148 02149 #define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */ 02150 #define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */ 02151 02152 #define SYS_IPRST0_HSUSBDRST_Pos (10) /*!< SYS_T::IPRST0: HSUSBDRST Position */ 02153 #define SYS_IPRST0_HSUSBDRST_Msk (0x1ul << SYS_IPRST0_HSUSBDRST_Pos) /*!< SYS_T::IPRST0: HSUSBDRST Mask */ 02154 02155 #define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */ 02156 #define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */ 02157 02158 #define SYS_IPRST0_SPIMRST_Pos (14) /*!< SYS_T::IPRST0: SPIMRST Position */ 02159 #define SYS_IPRST0_SPIMRST_Msk (0x1ul << SYS_IPRST0_SPIMRST_Pos) /*!< SYS_T::IPRST0: SPIMRST Mask */ 02160 02161 #define SYS_IPRST0_USBHRST_Pos (16) /*!< SYS_T::IPRST0: USBHRST Position */ 02162 #define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */ 02163 02164 #define SYS_IPRST0_SDH1RST_Pos (17) /*!< SYS_T::IPRST0: SDH1RST Position */ 02165 #define SYS_IPRST0_SDH1RST_Msk (0x1ul << SYS_IPRST0_SDH1RST_Pos) /*!< SYS_T::IPRST0: SDH1RST Mask */ 02166 02167 #define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */ 02168 #define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */ 02169 02170 #define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */ 02171 #define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */ 02172 02173 #define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */ 02174 #define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */ 02175 02176 #define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */ 02177 #define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */ 02178 02179 #define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */ 02180 #define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */ 02181 02182 #define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */ 02183 #define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */ 02184 02185 #define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */ 02186 #define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */ 02187 02188 #define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */ 02189 #define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */ 02190 02191 #define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */ 02192 #define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */ 02193 02194 #define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */ 02195 #define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */ 02196 02197 #define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */ 02198 #define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */ 02199 02200 #define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */ 02201 #define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */ 02202 02203 #define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */ 02204 #define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */ 02205 02206 #define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */ 02207 #define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */ 02208 02209 #define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */ 02210 #define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */ 02211 02212 #define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */ 02213 #define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */ 02214 02215 #define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */ 02216 #define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */ 02217 02218 #define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */ 02219 #define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */ 02220 02221 #define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */ 02222 #define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */ 02223 02224 #define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */ 02225 #define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */ 02226 02227 #define SYS_IPRST1_CAN1RST_Pos (25) /*!< SYS_T::IPRST1: CAN1RST Position */ 02228 #define SYS_IPRST1_CAN1RST_Msk (0x1ul << SYS_IPRST1_CAN1RST_Pos) /*!< SYS_T::IPRST1: CAN1RST Mask */ 02229 02230 #define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */ 02231 #define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */ 02232 02233 #define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */ 02234 #define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */ 02235 02236 #define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */ 02237 #define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */ 02238 02239 #define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */ 02240 #define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */ 02241 02242 #define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */ 02243 #define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */ 02244 02245 #define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS_T::IPRST2: SC2RST Position */ 02246 #define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS_T::IPRST2: SC2RST Mask */ 02247 02248 #define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */ 02249 #define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */ 02250 02251 #define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */ 02252 #define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */ 02253 02254 #define SYS_IPRST2_USCI1RST_Pos (9) /*!< SYS_T::IPRST2: USCI1RST Position */ 02255 #define SYS_IPRST2_USCI1RST_Msk (0x1ul << SYS_IPRST2_USCI1RST_Pos) /*!< SYS_T::IPRST2: USCI1RST Mask */ 02256 02257 #define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */ 02258 #define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */ 02259 02260 #define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */ 02261 #define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */ 02262 02263 #define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */ 02264 #define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */ 02265 02266 #define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */ 02267 #define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */ 02268 02269 #define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */ 02270 #define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */ 02271 02272 #define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS_T::IPRST2: QEI0RST Position */ 02273 #define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS_T::IPRST2: QEI0RST Mask */ 02274 02275 #define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS_T::IPRST2: QEI1RST Position */ 02276 #define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS_T::IPRST2: QEI1RST Mask */ 02277 02278 #define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */ 02279 #define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */ 02280 02281 #define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */ 02282 #define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */ 02283 02284 #define SYS_IPRST2_OPARST_Pos (30) /*!< SYS_T::IPRST2: OPARST Position */ 02285 #define SYS_IPRST2_OPARST_Msk (0x1ul << SYS_IPRST2_OPARST_Pos) /*!< SYS_T::IPRST2: OPARST Mask */ 02286 02287 #define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */ 02288 #define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */ 02289 02290 #define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */ 02291 #define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */ 02292 02293 #define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */ 02294 #define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */ 02295 02296 #define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */ 02297 #define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */ 02298 02299 #define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */ 02300 #define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */ 02301 02302 #define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */ 02303 #define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */ 02304 02305 #define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */ 02306 #define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */ 02307 02308 #define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */ 02309 #define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */ 02310 02311 #define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */ 02312 #define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */ 02313 02314 #define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */ 02315 #define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */ 02316 02317 #define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */ 02318 #define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */ 02319 02320 #define SYS_PORCTL_POROFF_Pos (0) /*!< SYS_T::PORCTL: POROFF Position */ 02321 #define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS_T::PORCTL: POROFF Mask */ 02322 02323 #define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */ 02324 #define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */ 02325 02326 #define SYS_VREFCTL_PRELOAD_SEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOAD_SEL Position */ 02327 #define SYS_VREFCTL_PRELOAD_SEL_Msk (0x3ul << SYS_VREFCTL_PRELOAD_SEL_Pos) /*!< SYS_T::VREFCTL: PRELOAD_SEL Mask */ 02328 02329 #define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */ 02330 #define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */ 02331 02332 #define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */ 02333 #define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */ 02334 02335 #define SYS_USBPHY_USBEN_Pos (8) /*!< SYS_T::USBPHY: USBEN Position */ 02336 #define SYS_USBPHY_USBEN_Msk (0x1ul << SYS_USBPHY_USBEN_Pos) /*!< SYS_T::USBPHY: USBEN Mask */ 02337 02338 #define SYS_USBPHY_HSUSBROLE_Pos (16) /*!< SYS_T::USBPHY: HSUSBROLE Position */ 02339 #define SYS_USBPHY_HSUSBROLE_Msk (0x3ul << SYS_USBPHY_HSUSBROLE_Pos) /*!< SYS_T::USBPHY: HSUSBROLE Mask */ 02340 02341 #define SYS_USBPHY_HSUSBEN_Pos (24) /*!< SYS_T::USBPHY: HSUSBEN Position */ 02342 #define SYS_USBPHY_HSUSBEN_Msk (0x1ul << SYS_USBPHY_HSUSBEN_Pos) /*!< SYS_T::USBPHY: HSUSBEN Mask */ 02343 02344 #define SYS_USBPHY_HSUSBACT_Pos (25) /*!< SYS_T::USBPHY: HSUSBACT Position */ 02345 #define SYS_USBPHY_HSUSBACT_Msk (0x1ul << SYS_USBPHY_HSUSBACT_Pos) /*!< SYS_T::USBPHY: HSUSBACT Mask */ 02346 02347 #define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */ 02348 #define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */ 02349 02350 #define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */ 02351 #define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */ 02352 02353 #define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */ 02354 #define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */ 02355 02356 #define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */ 02357 #define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */ 02358 02359 #define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */ 02360 #define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */ 02361 02362 #define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */ 02363 #define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */ 02364 02365 #define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */ 02366 #define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */ 02367 02368 #define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */ 02369 #define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */ 02370 02371 #define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */ 02372 #define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */ 02373 02374 #define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */ 02375 #define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */ 02376 02377 #define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */ 02378 #define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */ 02379 02380 #define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */ 02381 #define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */ 02382 02383 #define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */ 02384 #define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */ 02385 02386 #define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */ 02387 #define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */ 02388 02389 #define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */ 02390 #define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */ 02391 02392 #define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */ 02393 #define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */ 02394 02395 #define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */ 02396 #define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */ 02397 02398 #define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */ 02399 #define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */ 02400 02401 #define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */ 02402 #define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */ 02403 02404 #define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */ 02405 #define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */ 02406 02407 #define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */ 02408 #define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */ 02409 02410 #define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */ 02411 #define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */ 02412 02413 #define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */ 02414 #define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */ 02415 02416 #define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */ 02417 #define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */ 02418 02419 #define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */ 02420 #define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */ 02421 02422 #define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */ 02423 #define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */ 02424 02425 #define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */ 02426 #define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */ 02427 02428 #define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */ 02429 #define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */ 02430 02431 #define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */ 02432 #define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */ 02433 02434 #define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */ 02435 #define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */ 02436 02437 #define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */ 02438 #define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */ 02439 02440 #define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */ 02441 #define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */ 02442 02443 #define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */ 02444 #define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */ 02445 02446 #define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */ 02447 #define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */ 02448 02449 #define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */ 02450 #define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */ 02451 02452 #define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */ 02453 #define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */ 02454 02455 #define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */ 02456 #define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */ 02457 02458 #define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */ 02459 #define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */ 02460 02461 #define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */ 02462 #define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */ 02463 02464 #define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */ 02465 #define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */ 02466 02467 #define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */ 02468 #define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */ 02469 02470 #define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */ 02471 #define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */ 02472 02473 #define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */ 02474 #define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */ 02475 02476 #define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */ 02477 #define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */ 02478 02479 #define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */ 02480 #define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */ 02481 02482 #define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */ 02483 #define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */ 02484 02485 #define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS_T::GPC_MFPH: PC14MFP Position */ 02486 #define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS_T::GPC_MFPH: PC14MFP Mask */ 02487 02488 #define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS_T::GPC_MFPH: PC15MFP Position */ 02489 #define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS_T::GPC_MFPH: PC15MFP Mask */ 02490 02491 #define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */ 02492 #define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */ 02493 02494 #define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */ 02495 #define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */ 02496 02497 #define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */ 02498 #define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */ 02499 02500 #define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */ 02501 #define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */ 02502 02503 #define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */ 02504 #define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */ 02505 02506 #define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */ 02507 #define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */ 02508 02509 #define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */ 02510 #define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */ 02511 02512 #define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */ 02513 #define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */ 02514 02515 #define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */ 02516 #define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */ 02517 02518 #define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */ 02519 #define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */ 02520 02521 #define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */ 02522 #define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */ 02523 02524 #define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */ 02525 #define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */ 02526 02527 #define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */ 02528 #define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */ 02529 02530 #define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */ 02531 #define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */ 02532 02533 #define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */ 02534 #define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */ 02535 02536 #define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS_T::GPD_MFPH: PD15MFP Position */ 02537 #define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS_T::GPD_MFPH: PD15MFP Mask */ 02538 02539 #define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */ 02540 #define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */ 02541 02542 #define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */ 02543 #define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */ 02544 02545 #define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */ 02546 #define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */ 02547 02548 #define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */ 02549 #define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */ 02550 02551 #define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */ 02552 #define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */ 02553 02554 #define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */ 02555 #define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */ 02556 02557 #define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */ 02558 #define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */ 02559 02560 #define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */ 02561 #define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */ 02562 02563 #define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */ 02564 #define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */ 02565 02566 #define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */ 02567 #define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */ 02568 02569 #define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */ 02570 #define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */ 02571 02572 #define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */ 02573 #define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */ 02574 02575 #define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */ 02576 #define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */ 02577 02578 #define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */ 02579 #define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */ 02580 02581 #define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */ 02582 #define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */ 02583 02584 #define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS_T::GPE_MFPH: PE15MFP Position */ 02585 #define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS_T::GPE_MFPH: PE15MFP Mask */ 02586 02587 #define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */ 02588 #define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */ 02589 02590 #define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */ 02591 #define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */ 02592 02593 #define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */ 02594 #define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */ 02595 02596 #define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */ 02597 #define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */ 02598 02599 #define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */ 02600 #define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */ 02601 02602 #define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */ 02603 #define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */ 02604 02605 #define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */ 02606 #define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */ 02607 02608 #define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */ 02609 #define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */ 02610 02611 #define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFPH: PF8MFP Position */ 02612 #define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS_T::GPF_MFPH: PF8MFP Mask */ 02613 02614 #define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS_T::GPF_MFPH: PF9MFP Position */ 02615 #define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS_T::GPF_MFPH: PF9MFP Mask */ 02616 02617 #define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS_T::GPF_MFPH: PF10MFP Position */ 02618 #define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS_T::GPF_MFPH: PF10MFP Mask */ 02619 02620 #define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS_T::GPF_MFPH: PF11MFP Position */ 02621 #define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS_T::GPF_MFPH: PF11MFP Mask */ 02622 02623 #define SYS_GPF_MFPH_PF12MFP_Pos (16) /*!< SYS_T::GPF_MFPH: PF12MFP Position */ 02624 #define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) /*!< SYS_T::GPF_MFPH: PF12MFP Mask */ 02625 02626 #define SYS_GPF_MFPH_PF13MFP_Pos (20) /*!< SYS_T::GPF_MFPH: PF13MFP Position */ 02627 #define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) /*!< SYS_T::GPF_MFPH: PF13MFP Mask */ 02628 02629 #define SYS_GPF_MFPH_PF14MFP_Pos (24) /*!< SYS_T::GPF_MFPH: PF14MFP Position */ 02630 #define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) /*!< SYS_T::GPF_MFPH: PF14MFP Mask */ 02631 02632 #define SYS_GPF_MFPH_PF15MFP_Pos (28) /*!< SYS_T::GPF_MFPH: PF15MFP Position */ 02633 #define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) /*!< SYS_T::GPF_MFPH: PF15MFP Mask */ 02634 02635 #define SYS_GPG_MFPL_PG0MFP_Pos (0) /*!< SYS_T::GPG_MFPL: PG0MFP Position */ 02636 #define SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos) /*!< SYS_T::GPG_MFPL: PG0MFP Mask */ 02637 02638 #define SYS_GPG_MFPL_PG1MFP_Pos (4) /*!< SYS_T::GPG_MFPL: PG1MFP Position */ 02639 #define SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos) /*!< SYS_T::GPG_MFPL: PG1MFP Mask */ 02640 02641 #define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS_T::GPG_MFPL: PG2MFP Position */ 02642 #define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS_T::GPG_MFPL: PG2MFP Mask */ 02643 02644 #define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS_T::GPG_MFPL: PG3MFP Position */ 02645 #define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS_T::GPG_MFPL: PG3MFP Mask */ 02646 02647 #define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS_T::GPG_MFPL: PG4MFP Position */ 02648 #define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS_T::GPG_MFPL: PG4MFP Mask */ 02649 02650 #define SYS_GPG_MFPL_PG5MFP_Pos (20) /*!< SYS_T::GPG_MFPL: PG5MFP Position */ 02651 #define SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos) /*!< SYS_T::GPG_MFPL: PG5MFP Mask */ 02652 02653 #define SYS_GPG_MFPL_PG6MFP_Pos (24) /*!< SYS_T::GPG_MFPL: PG6MFP Position */ 02654 #define SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos) /*!< SYS_T::GPG_MFPL: PG6MFP Mask */ 02655 02656 #define SYS_GPG_MFPL_PG7MFP_Pos (28) /*!< SYS_T::GPG_MFPL: PG7MFP Position */ 02657 #define SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos) /*!< SYS_T::GPG_MFPL: PG7MFP Mask */ 02658 02659 #define SYS_GPG_MFPH_PG8MFP_Pos (0) /*!< SYS_T::GPG_MFPH: PG8MFP Position */ 02660 #define SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos) /*!< SYS_T::GPG_MFPH: PG8MFP Mask */ 02661 02662 #define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS_T::GPG_MFPH: PG9MFP Position */ 02663 #define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS_T::GPG_MFPH: PG9MFP Mask */ 02664 02665 #define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS_T::GPG_MFPH: PG10MFP Position */ 02666 #define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS_T::GPG_MFPH: PG10MFP Mask */ 02667 02668 #define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS_T::GPG_MFPH: PG11MFP Position */ 02669 #define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS_T::GPG_MFPH: PG11MFP Mask */ 02670 02671 #define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS_T::GPG_MFPH: PG12MFP Position */ 02672 #define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS_T::GPG_MFPH: PG12MFP Mask */ 02673 02674 #define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS_T::GPG_MFPH: PG13MFP Position */ 02675 #define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS_T::GPG_MFPH: PG13MFP Mask */ 02676 02677 #define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS_T::GPG_MFPH: PG14MFP Position */ 02678 #define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS_T::GPG_MFPH: PG14MFP Mask */ 02679 02680 #define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS_T::GPG_MFPH: PG15MFP Position */ 02681 #define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS_T::GPG_MFPH: PG15MFP Mask */ 02682 02683 #define SYS_GPH_MFPL_PH0MFP_Pos (0) /*!< SYS_T::GPH_MFPL: PH0MFP Position */ 02684 #define SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos) /*!< SYS_T::GPH_MFPL: PH0MFP Mask */ 02685 02686 #define SYS_GPH_MFPL_PH1MFP_Pos (4) /*!< SYS_T::GPH_MFPL: PH1MFP Position */ 02687 #define SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos) /*!< SYS_T::GPH_MFPL: PH1MFP Mask */ 02688 02689 #define SYS_GPH_MFPL_PH2MFP_Pos (8) /*!< SYS_T::GPH_MFPL: PH2MFP Position */ 02690 #define SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos) /*!< SYS_T::GPH_MFPL: PH2MFP Mask */ 02691 02692 #define SYS_GPH_MFPL_PH3MFP_Pos (12) /*!< SYS_T::GPH_MFPL: PH3MFP Position */ 02693 #define SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos) /*!< SYS_T::GPH_MFPL: PH3MFP Mask */ 02694 02695 #define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS_T::GPH_MFPL: PH4MFP Position */ 02696 #define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS_T::GPH_MFPL: PH4MFP Mask */ 02697 02698 #define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS_T::GPH_MFPL: PH5MFP Position */ 02699 #define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS_T::GPH_MFPL: PH5MFP Mask */ 02700 02701 #define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS_T::GPH_MFPL: PH6MFP Position */ 02702 #define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS_T::GPH_MFPL: PH6MFP Mask */ 02703 02704 #define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS_T::GPH_MFPL: PH7MFP Position */ 02705 #define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS_T::GPH_MFPL: PH7MFP Mask */ 02706 02707 #define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFPH: PH8MFP Position */ 02708 #define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS_T::GPH_MFPH: PH8MFP Mask */ 02709 02710 #define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS_T::GPH_MFPH: PH9MFP Position */ 02711 #define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS_T::GPH_MFPH: PH9MFP Mask */ 02712 02713 #define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS_T::GPH_MFPH: PH10MFP Position */ 02714 #define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS_T::GPH_MFPH: PH10MFP Mask */ 02715 02716 #define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS_T::GPH_MFPH: PH11MFP Position */ 02717 #define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS_T::GPH_MFPH: PH11MFP Mask */ 02718 02719 #define SYS_GPH_MFPH_PH12MFP_Pos (16) /*!< SYS_T::GPH_MFPH: PH12MFP Position */ 02720 #define SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos) /*!< SYS_T::GPH_MFPH: PH12MFP Mask */ 02721 02722 #define SYS_GPH_MFPH_PH13MFP_Pos (20) /*!< SYS_T::GPH_MFPH: PH13MFP Position */ 02723 #define SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos) /*!< SYS_T::GPH_MFPH: PH13MFP Mask */ 02724 02725 #define SYS_GPH_MFPH_PH14MFP_Pos (24) /*!< SYS_T::GPH_MFPH: PH14MFP Position */ 02726 #define SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos) /*!< SYS_T::GPH_MFPH: PH14MFP Mask */ 02727 02728 #define SYS_GPH_MFPH_PH15MFP_Pos (28) /*!< SYS_T::GPH_MFPH: PH15MFP Position */ 02729 #define SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos) /*!< SYS_T::GPH_MFPH: PH15MFP Mask */ 02730 02731 #define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */ 02732 #define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */ 02733 02734 #define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */ 02735 #define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */ 02736 02737 #define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */ 02738 #define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */ 02739 02740 #define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */ 02741 #define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */ 02742 02743 #define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */ 02744 #define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */ 02745 02746 #define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */ 02747 #define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */ 02748 02749 #define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */ 02750 #define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */ 02751 02752 #define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */ 02753 #define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */ 02754 02755 #define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */ 02756 #define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */ 02757 02758 #define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */ 02759 #define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */ 02760 02761 #define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */ 02762 #define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */ 02763 02764 #define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */ 02765 #define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */ 02766 02767 #define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */ 02768 #define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */ 02769 02770 #define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */ 02771 #define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */ 02772 02773 #define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */ 02774 #define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */ 02775 02776 #define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */ 02777 #define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */ 02778 02779 #define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */ 02780 #define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */ 02781 02782 #define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */ 02783 #define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */ 02784 02785 #define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */ 02786 #define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */ 02787 02788 #define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */ 02789 #define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */ 02790 02791 #define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */ 02792 #define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */ 02793 02794 #define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */ 02795 #define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */ 02796 02797 #define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */ 02798 #define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */ 02799 02800 #define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */ 02801 #define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */ 02802 02803 #define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */ 02804 #define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */ 02805 02806 #define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */ 02807 #define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */ 02808 02809 #define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */ 02810 #define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */ 02811 02812 #define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */ 02813 #define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */ 02814 02815 #define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */ 02816 #define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */ 02817 02818 #define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */ 02819 #define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */ 02820 02821 #define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */ 02822 #define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */ 02823 02824 #define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */ 02825 #define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */ 02826 02827 #define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */ 02828 #define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */ 02829 02830 #define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */ 02831 #define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */ 02832 02833 #define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */ 02834 #define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */ 02835 02836 #define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */ 02837 #define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */ 02838 02839 #define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */ 02840 #define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */ 02841 02842 #define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */ 02843 #define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */ 02844 02845 #define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */ 02846 #define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */ 02847 02848 #define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */ 02849 #define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */ 02850 02851 #define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */ 02852 #define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */ 02853 02854 #define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */ 02855 #define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */ 02856 02857 #define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */ 02858 #define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */ 02859 02860 #define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */ 02861 #define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */ 02862 02863 #define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */ 02864 #define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */ 02865 02866 #define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */ 02867 #define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */ 02868 02869 #define SYS_GPC_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPC_MFOS: MFOS14 Position */ 02870 #define SYS_GPC_MFOS_MFOS14_Msk (0x1ul << SYS_GPC_MFOS_MFOS14_Pos) /*!< SYS_T::GPC_MFOS: MFOS14 Mask */ 02871 02872 #define SYS_GPC_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPC_MFOS: MFOS15 Position */ 02873 #define SYS_GPC_MFOS_MFOS15_Msk (0x1ul << SYS_GPC_MFOS_MFOS15_Pos) /*!< SYS_T::GPC_MFOS: MFOS15 Mask */ 02874 02875 #define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */ 02876 #define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */ 02877 02878 #define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */ 02879 #define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */ 02880 02881 #define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */ 02882 #define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */ 02883 02884 #define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */ 02885 #define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */ 02886 02887 #define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */ 02888 #define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */ 02889 02890 #define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */ 02891 #define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */ 02892 02893 #define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */ 02894 #define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */ 02895 02896 #define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */ 02897 #define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */ 02898 02899 #define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */ 02900 #define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */ 02901 02902 #define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */ 02903 #define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */ 02904 02905 #define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */ 02906 #define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */ 02907 02908 #define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */ 02909 #define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */ 02910 02911 #define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */ 02912 #define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */ 02913 02914 #define SYS_GPD_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPD_MFOS: MFOS13 Position */ 02915 #define SYS_GPD_MFOS_MFOS13_Msk (0x1ul << SYS_GPD_MFOS_MFOS13_Pos) /*!< SYS_T::GPD_MFOS: MFOS13 Mask */ 02916 02917 #define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */ 02918 #define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */ 02919 02920 #define SYS_GPD_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPD_MFOS: MFOS15 Position */ 02921 #define SYS_GPD_MFOS_MFOS15_Msk (0x1ul << SYS_GPD_MFOS_MFOS15_Pos) /*!< SYS_T::GPD_MFOS: MFOS15 Mask */ 02922 02923 #define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */ 02924 #define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */ 02925 02926 #define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */ 02927 #define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */ 02928 02929 #define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */ 02930 #define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */ 02931 02932 #define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */ 02933 #define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */ 02934 02935 #define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */ 02936 #define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */ 02937 02938 #define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */ 02939 #define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */ 02940 02941 #define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */ 02942 #define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */ 02943 02944 #define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */ 02945 #define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */ 02946 02947 #define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */ 02948 #define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */ 02949 02950 #define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */ 02951 #define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */ 02952 02953 #define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */ 02954 #define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */ 02955 02956 #define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */ 02957 #define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */ 02958 02959 #define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */ 02960 #define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */ 02961 02962 #define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */ 02963 #define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */ 02964 02965 #define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */ 02966 #define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */ 02967 02968 #define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */ 02969 #define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */ 02970 02971 #define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */ 02972 #define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */ 02973 02974 #define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */ 02975 #define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */ 02976 02977 #define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */ 02978 #define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */ 02979 02980 #define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */ 02981 #define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */ 02982 02983 #define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */ 02984 #define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */ 02985 02986 #define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */ 02987 #define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */ 02988 02989 #define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */ 02990 #define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */ 02991 02992 #define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */ 02993 #define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */ 02994 02995 #define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */ 02996 #define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */ 02997 02998 #define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */ 02999 #define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */ 03000 03001 #define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */ 03002 #define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */ 03003 03004 #define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */ 03005 #define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */ 03006 03007 #define SYS_GPF_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPF_MFOS: MFOS12 Position */ 03008 #define SYS_GPF_MFOS_MFOS12_Msk (0x1ul << SYS_GPF_MFOS_MFOS12_Pos) /*!< SYS_T::GPF_MFOS: MFOS12 Mask */ 03009 03010 #define SYS_GPF_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPF_MFOS: MFOS13 Position */ 03011 #define SYS_GPF_MFOS_MFOS13_Msk (0x1ul << SYS_GPF_MFOS_MFOS13_Pos) /*!< SYS_T::GPF_MFOS: MFOS13 Mask */ 03012 03013 #define SYS_GPF_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPF_MFOS: MFOS14 Position */ 03014 #define SYS_GPF_MFOS_MFOS14_Msk (0x1ul << SYS_GPF_MFOS_MFOS14_Pos) /*!< SYS_T::GPF_MFOS: MFOS14 Mask */ 03015 03016 #define SYS_GPF_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPF_MFOS: MFOS15 Position */ 03017 #define SYS_GPF_MFOS_MFOS15_Msk (0x1ul << SYS_GPF_MFOS_MFOS15_Pos) /*!< SYS_T::GPF_MFOS: MFOS15 Mask */ 03018 03019 #define SYS_GPG_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPG_MFOS: MFOS0 Position */ 03020 #define SYS_GPG_MFOS_MFOS0_Msk (0x1ul << SYS_GPG_MFOS_MFOS0_Pos) /*!< SYS_T::GPG_MFOS: MFOS0 Mask */ 03021 03022 #define SYS_GPG_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPG_MFOS: MFOS1 Position */ 03023 #define SYS_GPG_MFOS_MFOS1_Msk (0x1ul << SYS_GPG_MFOS_MFOS1_Pos) /*!< SYS_T::GPG_MFOS: MFOS1 Mask */ 03024 03025 #define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */ 03026 #define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */ 03027 03028 #define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */ 03029 #define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */ 03030 03031 #define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */ 03032 #define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */ 03033 03034 #define SYS_GPG_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPG_MFOS: MFOS5 Position */ 03035 #define SYS_GPG_MFOS_MFOS5_Msk (0x1ul << SYS_GPG_MFOS_MFOS5_Pos) /*!< SYS_T::GPG_MFOS: MFOS5 Mask */ 03036 03037 #define SYS_GPG_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPG_MFOS: MFOS6 Position */ 03038 #define SYS_GPG_MFOS_MFOS6_Msk (0x1ul << SYS_GPG_MFOS_MFOS6_Pos) /*!< SYS_T::GPG_MFOS: MFOS6 Mask */ 03039 03040 #define SYS_GPG_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPG_MFOS: MFOS7 Position */ 03041 #define SYS_GPG_MFOS_MFOS7_Msk (0x1ul << SYS_GPG_MFOS_MFOS7_Pos) /*!< SYS_T::GPG_MFOS: MFOS7 Mask */ 03042 03043 #define SYS_GPG_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPG_MFOS: MFOS8 Position */ 03044 #define SYS_GPG_MFOS_MFOS8_Msk (0x1ul << SYS_GPG_MFOS_MFOS8_Pos) /*!< SYS_T::GPG_MFOS: MFOS8 Mask */ 03045 03046 #define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */ 03047 #define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */ 03048 03049 #define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */ 03050 #define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */ 03051 03052 #define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */ 03053 #define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */ 03054 03055 #define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */ 03056 #define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */ 03057 03058 #define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */ 03059 #define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */ 03060 03061 #define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */ 03062 #define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */ 03063 03064 #define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */ 03065 #define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */ 03066 03067 #define SYS_GPH_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPH_MFOS: MFOS0 Position */ 03068 #define SYS_GPH_MFOS_MFOS0_Msk (0x1ul << SYS_GPH_MFOS_MFOS0_Pos) /*!< SYS_T::GPH_MFOS: MFOS0 Mask */ 03069 03070 #define SYS_GPH_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPH_MFOS: MFOS1 Position */ 03071 #define SYS_GPH_MFOS_MFOS1_Msk (0x1ul << SYS_GPH_MFOS_MFOS1_Pos) /*!< SYS_T::GPH_MFOS: MFOS1 Mask */ 03072 03073 #define SYS_GPH_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPH_MFOS: MFOS2 Position */ 03074 #define SYS_GPH_MFOS_MFOS2_Msk (0x1ul << SYS_GPH_MFOS_MFOS2_Pos) /*!< SYS_T::GPH_MFOS: MFOS2 Mask */ 03075 03076 #define SYS_GPH_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPH_MFOS: MFOS3 Position */ 03077 #define SYS_GPH_MFOS_MFOS3_Msk (0x1ul << SYS_GPH_MFOS_MFOS3_Pos) /*!< SYS_T::GPH_MFOS: MFOS3 Mask */ 03078 03079 #define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */ 03080 #define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */ 03081 03082 #define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */ 03083 #define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */ 03084 03085 #define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */ 03086 #define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */ 03087 03088 #define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */ 03089 #define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */ 03090 03091 #define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */ 03092 #define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */ 03093 03094 #define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */ 03095 #define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */ 03096 03097 #define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */ 03098 #define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */ 03099 03100 #define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */ 03101 #define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */ 03102 03103 #define SYS_GPH_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPH_MFOS: MFOS12 Position */ 03104 #define SYS_GPH_MFOS_MFOS12_Msk (0x1ul << SYS_GPH_MFOS_MFOS12_Pos) /*!< SYS_T::GPH_MFOS: MFOS12 Mask */ 03105 03106 #define SYS_GPH_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPH_MFOS: MFOS13 Position */ 03107 #define SYS_GPH_MFOS_MFOS13_Msk (0x1ul << SYS_GPH_MFOS_MFOS13_Pos) /*!< SYS_T::GPH_MFOS: MFOS13 Mask */ 03108 03109 #define SYS_GPH_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPH_MFOS: MFOS14 Position */ 03110 #define SYS_GPH_MFOS_MFOS14_Msk (0x1ul << SYS_GPH_MFOS_MFOS14_Pos) /*!< SYS_T::GPH_MFOS: MFOS14 Mask */ 03111 03112 #define SYS_GPH_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPH_MFOS: MFOS15 Position */ 03113 #define SYS_GPH_MFOS_MFOS15_Msk (0x1ul << SYS_GPH_MFOS_MFOS15_Pos) /*!< SYS_T::GPH_MFOS: MFOS15 Mask */ 03114 03115 #define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */ 03116 #define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */ 03117 03118 #define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */ 03119 #define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */ 03120 03121 #define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */ 03122 #define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */ 03123 03124 #define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */ 03125 #define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */ 03126 03127 #define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */ 03128 #define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */ 03129 03130 #define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */ 03131 #define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */ 03132 03133 #define SYS_SRAM_BISTCTL_CANBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANBIST Position */ 03134 #define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask */ 03135 03136 #define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */ 03137 #define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */ 03138 03139 #define SYS_SRAM_BISTCTL_SPIMBIST_Pos (5) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Position */ 03140 #define SYS_SRAM_BISTCTL_SPIMBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_SPIMBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Mask */ 03141 03142 #define SYS_SRAM_BISTCTL_EMCBIST_Pos (6) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Position */ 03143 #define SYS_SRAM_BISTCTL_EMCBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_EMCBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: EMCBIST Mask */ 03144 03145 #define SYS_SRAM_BISTCTL_PDMABIST_Pos (7) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Position */ 03146 #define SYS_SRAM_BISTCTL_PDMABIST_Msk (0x1ul << SYS_SRAM_BISTCTL_PDMABIST_Pos) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Mask */ 03147 03148 #define SYS_SRAM_BISTCTL_HSUSBDBIST_Pos (8) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Position*/ 03149 #define SYS_SRAM_BISTCTL_HSUSBDBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBDBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Mask */ 03150 03151 #define SYS_SRAM_BISTCTL_HSUSBHBIST_Pos (9) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Position*/ 03152 #define SYS_SRAM_BISTCTL_HSUSBHBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBHBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Mask */ 03153 03154 #define SYS_SRAM_BISTCTL_SRB0S0_Pos (16) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Position */ 03155 #define SYS_SRAM_BISTCTL_SRB0S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S0 Mask */ 03156 03157 #define SYS_SRAM_BISTCTL_SRB0S1_Pos (17) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Position */ 03158 #define SYS_SRAM_BISTCTL_SRB0S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB0S1 Mask */ 03159 03160 #define SYS_SRAM_BISTCTL_SRB1S0_Pos (18) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Position */ 03161 #define SYS_SRAM_BISTCTL_SRB1S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S0 Mask */ 03162 03163 #define SYS_SRAM_BISTCTL_SRB1S1_Pos (19) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Position */ 03164 #define SYS_SRAM_BISTCTL_SRB1S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S1 Mask */ 03165 03166 #define SYS_SRAM_BISTCTL_SRB1S2_Pos (20) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Position */ 03167 #define SYS_SRAM_BISTCTL_SRB1S2_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S2_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S2 Mask */ 03168 03169 #define SYS_SRAM_BISTCTL_SRB1S3_Pos (21) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Position */ 03170 #define SYS_SRAM_BISTCTL_SRB1S3_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S3_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S3 Mask */ 03171 03172 #define SYS_SRAM_BISTCTL_SRB1S4_Pos (22) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Position */ 03173 #define SYS_SRAM_BISTCTL_SRB1S4_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S4_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S4 Mask */ 03174 03175 #define SYS_SRAM_BISTCTL_SRB1S5_Pos (23) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Position */ 03176 #define SYS_SRAM_BISTCTL_SRB1S5_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S5_Pos) /*!< SYS_T::SRAM_BISTCTL: SRB1S5 Mask */ 03177 03178 #define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position*/ 03179 #define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */ 03180 03181 #define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position*/ 03182 #define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */ 03183 03184 #define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */ 03185 #define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */ 03186 03187 #define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */ 03188 #define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */ 03189 03190 #define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */ 03191 #define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */ 03192 03193 #define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */ 03194 #define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */ 03195 03196 #define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */ 03197 #define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */ 03198 03199 #define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */ 03200 #define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */ 03201 03202 #define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */ 03203 #define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */ 03204 03205 #define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */ 03206 #define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */ 03207 03208 #define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */ 03209 #define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */ 03210 03211 #define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */ 03212 #define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */ 03213 03214 #define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */ 03215 #define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */ 03216 03217 #define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */ 03218 #define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */ 03219 03220 #define SYS_IRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::IRCTCTL: REFCKSEL Position */ 03221 #define SYS_IRCTCTL_REFCKSEL_Msk (0x1ul << SYS_IRCTCTL_REFCKSEL_Pos) /*!< SYS_T::IRCTCTL: REFCKSEL Mask */ 03222 03223 #define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */ 03224 #define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */ 03225 03226 #define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */ 03227 #define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */ 03228 03229 #define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */ 03230 #define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */ 03231 03232 #define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */ 03233 #define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */ 03234 03235 #define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */ 03236 #define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */ 03237 03238 #define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */ 03239 #define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */ 03240 03241 #define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */ 03242 #define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */ 03243 03244 #define SYS_PLCTL_LVSSTEP_Pos (16) /*!< SYS_T::PLCTL: LVSSTEP Position */ 03245 #define SYS_PLCTL_LVSSTEP_Msk (0x3ful << SYS_PLCTL_LVSSTEP_Pos) /*!< SYS_T::PLCTL: LVSSTEP Mask */ 03246 03247 #define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */ 03248 #define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */ 03249 03250 #define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */ 03251 #define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */ 03252 03253 #define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */ 03254 #define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */ 03255 03256 #define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */ 03257 #define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */ 03258 03259 /**@}*/ /* SYS_CONST */ 03260 /**@}*/ /* end of SYS register group */ 03261 03262 /** 03263 @addtogroup NMI NMI Controller (NMI) 03264 Memory Mapped Structure for NMI Controller 03265 @{ */ 03266 03267 typedef struct { 03268 03269 03270 /** 03271 * @var NMI_T::NMIEN 03272 * Offset: 0x00 NMI Source Interrupt Enable Register 03273 * --------------------------------------------------------------------------------------------------- 03274 * |Bits |Field |Descriptions 03275 * | :----: | :----: | :---- | 03276 * |[0] |BODOUT |BOD NMI Source Enable (Write Protect) 03277 * | | |0 = BOD NMI source Disabled. 03278 * | | |1 = BOD NMI source Enabled. 03279 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 03280 * |[1] |IRC_INT |IRC TRIM NMI Source Enable (Write Protect) 03281 * | | |0 = IRC TRIM NMI source Disabled. 03282 * | | |1 = IRC TRIM NMI source Enabled. 03283 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 03284 * |[2] |PWRWU_INT |Power-down Mode Wake-up NMI Source Enable (Write Protect) 03285 * | | |0 = Power-down mode wake-up NMI source Disabled. 03286 * | | |1 = Power-down mode wake-up NMI source Enabled. 03287 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 03288 * |[3] |SRAM_PERR |SRAM Parity Check NMI Source Enable (Write Protect) 03289 * | | |0 = SRAM parity check error NMI source Disabled. 03290 * | | |1 = SRAM parity check error NMI source Enabled. 03291 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 03292 * |[4] |CLKFAIL |Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable (Write Protect) 03293 * | | |0 = Clock fail detected and IRC Auto Trim interrupt NMI source Disabled. 03294 * | | |1 = Clock fail detected and IRC Auto Trim interrupt NMI source Enabled. 03295 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 03296 * |[6] |RTC_INT |RTC NMI Source Enable (Write Protect) 03297 * | | |0 = RTC NMI source Disabled. 03298 * | | |1 = RTC NMI source Enabled. 03299 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 03300 * |[7] |TAMPER_INT|TAMPER_INT NMI Source Enable (Write Protect) 03301 * | | |0 = Backup register tamper detected NMI source Disabled. 03302 * | | |1 = Backup register tamper detected NMI source Enabled. 03303 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 03304 * |[8] |EINT0 |External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write Protect) 03305 * | | |0 = External interrupt from PA.6 or PB.5 pin NMI source Disabled. 03306 * | | |1 = External interrupt from PA.6 or PB.5 pin NMI source Enabled. 03307 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 03308 * |[9] |EINT1 |External Interrupt From PA.7, PB.4 or PD.15 Pin NMI Source Enable (Write Protect) 03309 * | | |0 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Disabled. 03310 * | | |1 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Enabled. 03311 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 03312 * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect) 03313 * | | |0 = External interrupt from PB.3 or PC.6 pin NMI source Disabled. 03314 * | | |1 = External interrupt from PB.3 or PC.6 pin NMI source Enabled. 03315 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 03316 * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect) 03317 * | | |0 = External interrupt from PB.2 or PC.7 pin NMI source Disabled. 03318 * | | |1 = External interrupt from PB.2 or PC.7 pin NMI source Enabled. 03319 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 03320 * |[12] |EINT4 |External Interrupt From PA.8, PB.6 or PF.15 Pin NMI Source Enable (Write Protect) 03321 * | | |0 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Disabled. 03322 * | | |1 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Enabled. 03323 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 03324 * |[13] |EINT5 |External Interrupt From PB.7 or PF.14 Pin NMI Source Enable (Write Protect) 03325 * | | |0 = External interrupt from PB.7 or PF.14 pin NMI source Disabled. 03326 * | | |1 = External interrupt from PB.7 or PF.14 pin NMI source Enabled. 03327 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 03328 * |[14] |UART0_INT |UART0 NMI Source Enable (Write Protect) 03329 * | | |0 = UART0 NMI source Disabled. 03330 * | | |1 = UART0 NMI source Enabled. 03331 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 03332 * |[15] |UART1_INT |UART1 NMI Source Enable (Write Protect) 03333 * | | |0 = UART1 NMI source Disabled. 03334 * | | |1 = UART1 NMI source Enabled. 03335 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 03336 * @var NMI_T::NMISTS 03337 * Offset: 0x04 NMI Source Interrupt Status Register 03338 * --------------------------------------------------------------------------------------------------- 03339 * |Bits |Field |Descriptions 03340 * | :----: | :----: | :---- | 03341 * |[0] |BODOUT |BOD Interrupt Flag (Read Only) 03342 * | | |0 = BOD interrupt is deasserted. 03343 * | | |1 = BOD interrupt is asserted. 03344 * |[1] |IRC_INT |IRC TRIM Interrupt Flag (Read Only) 03345 * | | |0 = HIRC TRIM interrupt is deasserted. 03346 * | | |1 = HIRC TRIM interrupt is asserted. 03347 * |[2] |PWRWU_INT |Power-down Mode Wake-up Interrupt Flag (Read Only) 03348 * | | |0 = Power-down mode wake-up interrupt is deasserted. 03349 * | | |1 = Power-down mode wake-up interrupt is asserted. 03350 * |[3] |SRAM_PERR |SRAM ParityCheck Error Interrupt Flag (Read Only) 03351 * | | |0 = SRAM parity check error interrupt is deasserted. 03352 * | | |1 = SRAM parity check error interrupt is asserted. 03353 * |[4] |CLKFAIL |Clock Fail Detected or IRC Auto Trim Interrupt Flag (Read Only) 03354 * | | |0 = Clock fail detected or IRC Auto Trim interrupt is deasserted. 03355 * | | |1 = Clock fail detected or IRC Auto Trim interrupt is asserted. 03356 * |[6] |RTC_INT |RTC Interrupt Flag (Read Only) 03357 * | | |0 = RTC interrupt is deasserted. 03358 * | | |1 = RTC interrupt is asserted. 03359 * |[7] |TAMPER_INT|TAMPER_INT Interrupt Flag (Read Only) 03360 * | | |0 = Backup register tamper detected interrupt is deasserted. 03361 * | | |1 = Backup register tamper detected interrupt is asserted. 03362 * |[8] |EINT0 |External Interrupt From PA.6 or PB.5 Pin Interrupt Flag (Read Only) 03363 * | | |0 = External Interrupt from PA.6 or PB.5 interrupt is deasserted. 03364 * | | |1 = External Interrupt from PA.6 or PB.5 interrupt is asserted. 03365 * |[9] |EINT1 |External Interrupt From PA.7, PB.4 or PD.15 Pin Interrupt Flag (Read Only) 03366 * | | |0 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is deasserted. 03367 * | | |1 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is asserted. 03368 * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only) 03369 * | | |0 = External Interrupt from PB.3 or PC.6 interrupt is deasserted. 03370 * | | |1 = External Interrupt from PB.3 or PC.6 interrupt is asserted. 03371 * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only) 03372 * | | |0 = External Interrupt from PB.2 or PC.7 interrupt is deasserted. 03373 * | | |1 = External Interrupt from PB.2 or PC.7 interrupt is asserted. 03374 * |[12] |EINT4 |External Interrupt From PA.8, PB.6 or PF.15 Pin Interrupt Flag (Read Only) 03375 * | | |0 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is deasserted. 03376 * | | |1 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is asserted. 03377 * |[13] |EINT5 |External Interrupt From PB.7 or PF.14 Pin Interrupt Flag (Read Only) 03378 * | | |0 = External Interrupt from PB.7 or PF.14 interrupt is deasserted. 03379 * | | |1 = External Interrupt from PB.7 or PF.14 interrupt is asserted. 03380 * |[14] |UART0_INT |UART0 Interrupt Flag (Read Only) 03381 * | | |0 = UART1 interrupt is deasserted. 03382 * | | |1 = UART1 interrupt is asserted. 03383 * |[15] |UART1_INT |UART1 Interrupt Flag (Read Only) 03384 * | | |0 = UART1 interrupt is deasserted. 03385 * | | |1 = UART1 interrupt is asserted. 03386 */ 03387 __IO uint32_t NMIEN; /*!< [0x0000] NMI Source Interrupt Enable Register */ 03388 __I uint32_t NMISTS; /*!< [0x0004] NMI Source Interrupt Status Register */ 03389 03390 } NMI_T; 03391 03392 /** 03393 @addtogroup NMI_CONST NMI Bit Field Definition 03394 Constant Definitions for NMI Controller 03395 @{ */ 03396 03397 #define NMI_NMIEN_BODOUT_Pos (0) /*!< NMI_T::NMIEN: BODOUT Position */ 03398 #define NMI_NMIEN_BODOUT_Msk (0x1ul << NMI_NMIEN_BODOUT_Pos) /*!< NMI_T::NMIEN: BODOUT Mask */ 03399 03400 #define NMI_NMIEN_IRC_INT_Pos (1) /*!< NMI_T::NMIEN: IRC_INT Position */ 03401 #define NMI_NMIEN_IRC_INT_Msk (0x1ul << NMI_NMIEN_IRC_INT_Pos) /*!< NMI_T::NMIEN: IRC_INT Mask */ 03402 03403 #define NMI_NMIEN_PWRWU_INT_Pos (2) /*!< NMI_T::NMIEN: PWRWU_INT Position */ 03404 #define NMI_NMIEN_PWRWU_INT_Msk (0x1ul << NMI_NMIEN_PWRWU_INT_Pos) /*!< NMI_T::NMIEN: PWRWU_INT Mask */ 03405 03406 #define NMI_NMIEN_SRAM_PERR_Pos (3) /*!< NMI_T::NMIEN: SRAM_PERR Position */ 03407 #define NMI_NMIEN_SRAM_PERR_Msk (0x1ul << NMI_NMIEN_SRAM_PERR_Pos) /*!< NMI_T::NMIEN: SRAM_PERR Mask */ 03408 03409 #define NMI_NMIEN_CLKFAIL_Pos (4) /*!< NMI_T::NMIEN: CLKFAIL Position */ 03410 #define NMI_NMIEN_CLKFAIL_Msk (0x1ul << NMI_NMIEN_CLKFAIL_Pos) /*!< NMI_T::NMIEN: CLKFAIL Mask */ 03411 03412 #define NMI_NMIEN_RTC_INT_Pos (6) /*!< NMI_T::NMIEN: RTC_INT Position */ 03413 #define NMI_NMIEN_RTC_INT_Msk (0x1ul << NMI_NMIEN_RTC_INT_Pos) /*!< NMI_T::NMIEN: RTC_INT Mask */ 03414 03415 #define NMI_NMIEN_TAMPER_INT_Pos (7) /*!< NMI_T::NMIEN: TAMPER_INT Position */ 03416 #define NMI_NMIEN_TAMPER_INT_Msk (0x1ul << NMI_NMIEN_TAMPER_INT_Pos) /*!< NMI_T::NMIEN: TAMPER_INT Mask */ 03417 03418 #define NMI_NMIEN_EINT0_Pos (8) /*!< NMI_T::NMIEN: EINT0 Position */ 03419 #define NMI_NMIEN_EINT0_Msk (0x1ul << NMI_NMIEN_EINT0_Pos) /*!< NMI_T::NMIEN: EINT0 Mask */ 03420 03421 #define NMI_NMIEN_EINT1_Pos (9) /*!< NMI_T::NMIEN: EINT1 Position */ 03422 #define NMI_NMIEN_EINT1_Msk (0x1ul << NMI_NMIEN_EINT1_Pos) /*!< NMI_T::NMIEN: EINT1 Mask */ 03423 03424 #define NMI_NMIEN_EINT2_Pos (10) /*!< NMI_T::NMIEN: EINT2 Position */ 03425 #define NMI_NMIEN_EINT2_Msk (0x1ul << NMI_NMIEN_EINT2_Pos) /*!< NMI_T::NMIEN: EINT2 Mask */ 03426 03427 #define NMI_NMIEN_EINT3_Pos (11) /*!< NMI_T::NMIEN: EINT3 Position */ 03428 #define NMI_NMIEN_EINT3_Msk (0x1ul << NMI_NMIEN_EINT3_Pos) /*!< NMI_T::NMIEN: EINT3 Mask */ 03429 03430 #define NMI_NMIEN_EINT4_Pos (12) /*!< NMI_T::NMIEN: EINT4 Position */ 03431 #define NMI_NMIEN_EINT4_Msk (0x1ul << NMI_NMIEN_EINT4_Pos) /*!< NMI_T::NMIEN: EINT4 Mask */ 03432 03433 #define NMI_NMIEN_EINT5_Pos (13) /*!< NMI_T::NMIEN: EINT5 Position */ 03434 #define NMI_NMIEN_EINT5_Msk (0x1ul << NMI_NMIEN_EINT5_Pos) /*!< NMI_T::NMIEN: EINT5 Mask */ 03435 03436 #define NMI_NMIEN_UART0_INT_Pos (14) /*!< NMI_T::NMIEN: UART0_INT Position */ 03437 #define NMI_NMIEN_UART0_INT_Msk (0x1ul << NMI_NMIEN_UART0_INT_Pos) /*!< NMI_T::NMIEN: UART0_INT Mask */ 03438 03439 #define NMI_NMIEN_UART1_INT_Pos (15) /*!< NMI_T::NMIEN: UART1_INT Position */ 03440 #define NMI_NMIEN_UART1_INT_Msk (0x1ul << NMI_NMIEN_UART1_INT_Pos) /*!< NMI_T::NMIEN: UART1_INT Mask */ 03441 03442 #define NMI_NMISTS_BODOUT_Pos (0) /*!< NMI_T::NMISTS: BODOUT Position */ 03443 #define NMI_NMISTS_BODOUT_Msk (0x1ul << NMI_NMISTS_BODOUT_Pos) /*!< NMI_T::NMISTS: BODOUT Mask */ 03444 03445 #define NMI_NMISTS_IRC_INT_Pos (1) /*!< NMI_T::NMISTS: IRC_INT Position */ 03446 #define NMI_NMISTS_IRC_INT_Msk (0x1ul << NMI_NMISTS_IRC_INT_Pos) /*!< NMI_T::NMISTS: IRC_INT Mask */ 03447 03448 #define NMI_NMISTS_PWRWU_INT_Pos (2) /*!< NMI_T::NMISTS: PWRWU_INT Position */ 03449 #define NMI_NMISTS_PWRWU_INT_Msk (0x1ul << NMI_NMISTS_PWRWU_INT_Pos) /*!< NMI_T::NMISTS: PWRWU_INT Mask */ 03450 03451 #define NMI_NMISTS_SRAM_PERR_Pos (3) /*!< NMI_T::NMISTS: SRAM_PERR Position */ 03452 #define NMI_NMISTS_SRAM_PERR_Msk (0x1ul << NMI_NMISTS_SRAM_PERR_Pos) /*!< NMI_T::NMISTS: SRAM_PERR Mask */ 03453 03454 #define NMI_NMISTS_CLKFAIL_Pos (4) /*!< NMI_T::NMISTS: CLKFAIL Position */ 03455 #define NMI_NMISTS_CLKFAIL_Msk (0x1ul << NMI_NMISTS_CLKFAIL_Pos) /*!< NMI_T::NMISTS: CLKFAIL Mask */ 03456 03457 #define NMI_NMISTS_RTC_INT_Pos (6) /*!< NMI_T::NMISTS: RTC_INT Position */ 03458 #define NMI_NMISTS_RTC_INT_Msk (0x1ul << NMI_NMISTS_RTC_INT_Pos) /*!< NMI_T::NMISTS: RTC_INT Mask */ 03459 03460 #define NMI_NMISTS_TAMPER_INT_Pos (7) /*!< NMI_T::NMISTS: TAMPER_INT Position */ 03461 #define NMI_NMISTS_TAMPER_INT_Msk (0x1ul << NMI_NMISTS_TAMPER_INT_Pos) /*!< NMI_T::NMISTS: TAMPER_INT Mask */ 03462 03463 #define NMI_NMISTS_EINT0_Pos (8) /*!< NMI_T::NMISTS: EINT0 Position */ 03464 #define NMI_NMISTS_EINT0_Msk (0x1ul << NMI_NMISTS_EINT0_Pos) /*!< NMI_T::NMISTS: EINT0 Mask */ 03465 03466 #define NMI_NMISTS_EINT1_Pos (9) /*!< NMI_T::NMISTS: EINT1 Position */ 03467 #define NMI_NMISTS_EINT1_Msk (0x1ul << NMI_NMISTS_EINT1_Pos) /*!< NMI_T::NMISTS: EINT1 Mask */ 03468 03469 #define NMI_NMISTS_EINT2_Pos (10) /*!< NMI_T::NMISTS: EINT2 Position */ 03470 #define NMI_NMISTS_EINT2_Msk (0x1ul << NMI_NMISTS_EINT2_Pos) /*!< NMI_T::NMISTS: EINT2 Mask */ 03471 03472 #define NMI_NMISTS_EINT3_Pos (11) /*!< NMI_T::NMISTS: EINT3 Position */ 03473 #define NMI_NMISTS_EINT3_Msk (0x1ul << NMI_NMISTS_EINT3_Pos) /*!< NMI_T::NMISTS: EINT3 Mask */ 03474 03475 #define NMI_NMISTS_EINT4_Pos (12) /*!< NMI_T::NMISTS: EINT4 Position */ 03476 #define NMI_NMISTS_EINT4_Msk (0x1ul << NMI_NMISTS_EINT4_Pos) /*!< NMI_T::NMISTS: EINT4 Mask */ 03477 03478 #define NMI_NMISTS_EINT5_Pos (13) /*!< NMI_T::NMISTS: EINT5 Position */ 03479 #define NMI_NMISTS_EINT5_Msk (0x1ul << NMI_NMISTS_EINT5_Pos) /*!< NMI_T::NMISTS: EINT5 Mask */ 03480 03481 #define NMI_NMISTS_UART0_INT_Pos (14) /*!< NMI_T::NMISTS: UART0_INT Position */ 03482 #define NMI_NMISTS_UART0_INT_Msk (0x1ul << NMI_NMISTS_UART0_INT_Pos) /*!< NMI_T::NMISTS: UART0_INT Mask */ 03483 03484 #define NMI_NMISTS_UART1_INT_Pos (15) /*!< NMI_T::NMISTS: UART1_INT Position */ 03485 #define NMI_NMISTS_UART1_INT_Msk (0x1ul << NMI_NMISTS_UART1_INT_Pos) /*!< NMI_T::NMISTS: UART1_INT Mask */ 03486 03487 /**@}*/ /* NMI_CONST */ 03488 /**@}*/ /* end of NMI register group */ 03489 /**@}*/ /* end of REGISTER group */ 03490 03491 #if defined ( __CC_ARM ) 03492 #pragma no_anon_unions 03493 #endif 03494 03495 #endif /* __SYS_REG_H__ */
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