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m480_rtc_reg.h
00001 /**************************************************************************//** 00002 * @file rtc_reg.h 00003 * @version V1.00 00004 * @brief RTC register definition header file 00005 * 00006 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. 00007 * 00008 * Redistribution and use in source and binary forms, with or without modification, 00009 * are permitted provided that the following conditions are met: 00010 * 1. Redistributions of source code must retain the above copyright notice, 00011 * this list of conditions and the following disclaimer. 00012 * 2. Redistributions in binary form must reproduce the above copyright notice, 00013 * this list of conditions and the following disclaimer in the documentation 00014 * and/or other materials provided with the distribution. 00015 * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors 00016 * may be used to endorse or promote products derived from this software 00017 * without specific prior written permission. 00018 * 00019 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00020 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00021 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00022 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00023 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00024 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00025 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00026 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00027 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00028 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00029 *****************************************************************************/ 00030 #ifndef __RTC_REG_H__ 00031 #define __RTC_REG_H__ 00032 00033 #if defined ( __CC_ARM ) 00034 #pragma anon_unions 00035 #endif 00036 00037 /** 00038 @addtogroup REGISTER Control Register 00039 @{ 00040 */ 00041 00042 /** 00043 @addtogroup RTC Real Time Clock Controller(RTC) 00044 Memory Mapped Structure for RTC Controller 00045 @{ */ 00046 00047 typedef struct { 00048 00049 00050 /** 00051 * @var RTC_T::INIT 00052 * Offset: 0x00 RTC Initiation Register 00053 * --------------------------------------------------------------------------------------------------- 00054 * |Bits |Field |Descriptions 00055 * | :----: | :----: | :---- | 00056 * |[0] |INIT_ACTIVE|RTC Active Status (Read Only) 00057 * | | |0 = RTC is at reset state. 00058 * | | |1 = RTC is at normal active state. 00059 * |[31:1] |INIT |RTC Initiation (Write Only) 00060 * | | |When RTC block is powered on, RTC is at reset state 00061 * | | |User has to write a number (0xa5eb1357) to INIT to make RTC leaving reset state 00062 * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. 00063 * | | |The INIT is a write-only field and read value will be always 0. 00064 * @var RTC_T::RWEN 00065 * Offset: 0x04 RTC Access Enable Register 00066 * --------------------------------------------------------------------------------------------------- 00067 * |Bits |Field |Descriptions 00068 * | :----: | :----: | :---- | 00069 * |[16] |RWENF |RTC Register Access Enable Flag (Read Only) 00070 * | | |0 = RTC register read/write Disabled. 00071 * | | |1 = RTC register read/write Enabled. 00072 * | | |Note: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also. 00073 * |[24] |RTCBUSY |RTC Write Busy Flag 00074 * | | |This bit indicates RTC registers are writable or not. 00075 * | | |0: RTC registers are writable. 00076 * | | |1: RTC registers can't write, RTC under Busy Status. 00077 * | | |Note: RTCBUSY flag will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles. 00078 * @var RTC_T::FREQADJ 00079 * Offset: 0x08 RTC Frequency Compensation Register 00080 * --------------------------------------------------------------------------------------------------- 00081 * |Bits |Field |Descriptions 00082 * | :----: | :----: | :---- | 00083 * |[21:0] |FREQADJ |Frequency Compensation Register 00084 * | | |User must to get actual LXT frequency for RTC application. 00085 * | | |FCR = 0x200000 * (32768 / LXT frequency). 00086 * | | |Note: This formula is suitable only when RTC clock source is from LXT, RTCSEL (CLK_CLKSEL3[8]) is 0. 00087 * @var RTC_T::TIME 00088 * Offset: 0x0C RTC Time Loading Register 00089 * --------------------------------------------------------------------------------------------------- 00090 * |Bits |Field |Descriptions 00091 * | :----: | :----: | :---- | 00092 * |[3:0] |SEC |1-Sec Time Digit (0~9) 00093 * |[6:4] |TENSEC |10-Sec Time Digit (0~5) 00094 * |[11:8] |MIN |1-Min Time Digit (0~9) 00095 * |[14:12] |TENMIN |10-Min Time Digit (0~5) 00096 * |[19:16] |HR |1-Hour Time Digit (0~9) 00097 * |[21:20] |TENHR |10-Hour Time Digit (0~2) 00098 * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication 00099 * | | |(If RTC_TIME[21] is 1, it indicates PM time message). 00100 * @var RTC_T::CAL 00101 * Offset: 0x10 RTC Calendar Loading Register 00102 * --------------------------------------------------------------------------------------------------- 00103 * |Bits |Field |Descriptions 00104 * | :----: | :----: | :---- | 00105 * |[3:0] |DAY |1-Day Calendar Digit (0~9) 00106 * |[5:4] |TENDAY |10-Day Calendar Digit (0~3) 00107 * |[11:8] |MON |1-Month Calendar Digit (0~9) 00108 * |[12] |TENMON |10-Month Calendar Digit (0~1) 00109 * |[19:16] |YEAR |1-Year Calendar Digit (0~9) 00110 * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9) 00111 * @var RTC_T::CLKFMT 00112 * Offset: 0x14 RTC Time Scale Selection Register 00113 * --------------------------------------------------------------------------------------------------- 00114 * |Bits |Field |Descriptions 00115 * | :----: | :----: | :---- | 00116 * |[0] |24HEN |24-hour / 12-hour Time Scale Selection 00117 * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale 00118 * | | |0 = 12-hour time scale with AM and PM indication selected. 00119 * | | |1 = 24-hour time scale selected. 00120 * @var RTC_T::WEEKDAY 00121 * Offset: 0x18 RTC Day of the Week Register 00122 * --------------------------------------------------------------------------------------------------- 00123 * |Bits |Field |Descriptions 00124 * | :----: | :----: | :---- | 00125 * |[2:0] |WEEKDAY |Day of the Week Register 00126 * | | |000 = Sunday. 00127 * | | |001 = Monday. 00128 * | | |010 = Tuesday. 00129 * | | |011 = Wednesday. 00130 * | | |100 = Thursday. 00131 * | | |101 = Friday. 00132 * | | |110 = Saturday. 00133 * | | |111 = Reserved. 00134 * @var RTC_T::TALM 00135 * Offset: 0x1C RTC Time Alarm Register 00136 * --------------------------------------------------------------------------------------------------- 00137 * |Bits |Field |Descriptions 00138 * | :----: | :----: | :---- | 00139 * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9) 00140 * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5) 00141 * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9) 00142 * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5) 00143 * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9) 00144 * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2) 00145 * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication 00146 * | | |(If RTC_TIME[21] is 1, it indicates PM time message). 00147 * @var RTC_T::CALM 00148 * Offset: 0x20 RTC Calendar Alarm Register 00149 * --------------------------------------------------------------------------------------------------- 00150 * |Bits |Field |Descriptions 00151 * | :----: | :----: | :---- | 00152 * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9) 00153 * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3) 00154 * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9) 00155 * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1) 00156 * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9) 00157 * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9) 00158 * @var RTC_T::LEAPYEAR 00159 * Offset: 0x24 RTC Leap Year Indicator Register 00160 * --------------------------------------------------------------------------------------------------- 00161 * |Bits |Field |Descriptions 00162 * | :----: | :----: | :---- | 00163 * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only) 00164 * | | |0 = This year is not a leap year. 00165 * | | |1 = This year is leap year. 00166 * @var RTC_T::INTEN 00167 * Offset: 0x28 RTC Interrupt Enable Register 00168 * --------------------------------------------------------------------------------------------------- 00169 * |Bits |Field |Descriptions 00170 * | :----: | :----: | :---- | 00171 * |[0] |ALMIEN |Alarm Interrupt Enable Bit 00172 * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated. 00173 * | | |0 = RTC Alarm interrupt Disabled. 00174 * | | |1 = RTC Alarm interrupt Enabled. 00175 * |[1] |TICKIEN |Time Tick Interrupt Enable Bit 00176 * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated. 00177 * | | |0 = RTC Time Tick interrupt Disabled. 00178 * | | |1 = RTC Time Tick interrupt Enabled. 00179 * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit 00180 * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated. 00181 * | | |0 = Tamper 0 interrupt Disabled. 00182 * | | |1 = Tamper 0 interrupt Enabled. 00183 * |[9] |TAMP1IEN |Tamper 1 or Pair 0 Interrupt Enable Bit 00184 * | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated. 00185 * | | |0 = Tamper 1 or Pair 0 interrupt Disabled. 00186 * | | |1 = Tamper 1 or Pair 0 interrupt Enabled. 00187 * |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit 00188 * | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated. 00189 * | | |0 = Tamper 2 interrupt Disabled. 00190 * | | |1 = Tamper 2 interrupt Enabled. 00191 * |[11] |TAMP3IEN |Tamper 3 or Pair 1 Interrupt Enable Bit 00192 * | | |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated. 00193 * | | |0 = Tamper 3 or Pair 1 interrupt Disabled. 00194 * | | |1 = Tamper 3 or Pair 1 interrupt Enabled. 00195 * |[12] |TAMP4IEN |Tamper 4 Interrupt Enable Bit 00196 * | | |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated. 00197 * | | |0 = Tamper 4 interrupt Disabled. 00198 * | | |1 = Tamper 4 interrupt Enabled. 00199 * |[13] |TAMP5IEN |Tamper 5 or Pair 2 Interrupt Enable Bit 00200 * | | |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated. 00201 * | | |0 = Tamper 5 or Pair 2 interrupt Disabled. 00202 * | | |1 = Tamper 5 or Pair 2 interrupt Enabled. 00203 * @var RTC_T::INTSTS 00204 * Offset: 0x2C RTC Interrupt Status Register 00205 * --------------------------------------------------------------------------------------------------- 00206 * |Bits |Field |Descriptions 00207 * | :----: | :----: | :---- | 00208 * |[0] |ALMIF |RTC Alarm Interrupt Flag 00209 * | | |0 = Alarm condition is not matched. 00210 * | | |1 = Alarm condition is matched. 00211 * | | |Note: Write 1 to clear this bit. 00212 * |[1] |TICKIF |RTC Time Tick Interrupt Flag 00213 * | | |0 = Tick condition does not occur. 00214 * | | |1 = Tick condition occur. 00215 * | | |Note: Write 1 to clear this bit. 00216 * |[8] |TAMP0IF |Tamper 0 Interrupt Flag 00217 * | | |This bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]). 00218 * | | |0 = No Tamper 0 interrupt flag is generated. 00219 * | | |1 = Tamper 0 interrupt flag is generated. 00220 * | | |Note1: Write 1 to clear this bit. 00221 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 00222 * |[9] |TAMP1IF |Tamper 1 or Pair 0 Interrupt Flag 00223 * | | |This bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) 00224 * | | |or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated. 00225 * | | |0 = No Tamper 1 or Pair 0 interrupt flag is generated. 00226 * | | |1 = Tamper 1 or Pair 0 interrupt flag is generated. 00227 * | | |Note1: Write 1 to clear this bit. 00228 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 00229 * |[10] |TAMP2IF |Tamper 2 Interrupt Flag 00230 * | | |This bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]). 00231 * | | |0 = No Tamper 2 interrupt flag is generated. 00232 * | | |1 = Tamper 2 interrupt flag is generated. 00233 * | | |Note1: Write 1 to clear this bit. 00234 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 00235 * |[11] |TAMP3IF |Tamper 3 or Pair 1 Interrupt Flag 00236 * | | |This bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) 00237 * | | |or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated 00238 * | | |or TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated. 00239 * | | |0 = No Tamper 3 or Pair 1 interrupt flag is generated. 00240 * | | |1 = Tamper 3 or Pair 1 interrupt flag is generated. 00241 * | | |Note1: Write 1 to clear this bit. 00242 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 00243 * |[12] |TAMP4IF |Tamper 4 Interrupt Flag 00244 * | | |This bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]). 00245 * | | |0 = No Tamper 4 interrupt flag is generated. 00246 * | | |1 = Tamper 4 interrupt flag is generated. 00247 * | | |Note1: Write 1 to clear this bit. 00248 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 00249 * |[13] |TAMP5IF |Tamper 5 or Pair 2 Interrupt Flag 00250 * | | |This bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) 00251 * | | |or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated 00252 * | | |or TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated. 00253 * | | |0 = No Tamper 5 or Pair 2 interrupt flag is generated. 00254 * | | |1 = Tamper 5 or Pair 2 interrupt flag is generated. 00255 * | | |Note1: Write 1 to clear this bit. 00256 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 00257 * @var RTC_T::TICK 00258 * Offset: 0x30 RTC Time Tick Register 00259 * --------------------------------------------------------------------------------------------------- 00260 * |Bits |Field |Descriptions 00261 * | :----: | :----: | :---- | 00262 * |[2:0] |TICK |Time Tick Register 00263 * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. 00264 * | | |000 = Time tick is 1 second. 00265 * | | |001 = Time tick is 1/2 second. 00266 * | | |010 = Time tick is 1/4 second. 00267 * | | |011 = Time tick is 1/8 second. 00268 * | | |100 = Time tick is 1/16 second. 00269 * | | |101 = Time tick is 1/32 second. 00270 * | | |110 = Time tick is 1/64 second. 00271 * | | |111 = Time tick is 1/128 second. 00272 * | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active. 00273 * @var RTC_T::TAMSK 00274 * Offset: 0x34 RTC Time Alarm Mask Register 00275 * --------------------------------------------------------------------------------------------------- 00276 * |Bits |Field |Descriptions 00277 * | :----: | :----: | :---- | 00278 * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9) 00279 * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5) 00280 * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9) 00281 * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5) 00282 * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9) 00283 * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2) 00284 * @var RTC_T::CAMSK 00285 * Offset: 0x38 RTC Calendar Alarm Mask Register 00286 * --------------------------------------------------------------------------------------------------- 00287 * |Bits |Field |Descriptions 00288 * | :----: | :----: | :---- | 00289 * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9) 00290 * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3) 00291 * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9) 00292 * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1) 00293 * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9) 00294 * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9) 00295 * @var RTC_T::SPRCTL 00296 * Offset: 0x3C RTC Spare Functional Control Register 00297 * --------------------------------------------------------------------------------------------------- 00298 * |Bits |Field |Descriptions 00299 * | :----: | :----: | :---- | 00300 * |[2] |SPRRWEN |Spare Register Enable Bit 00301 * | | |0 = Spare register is Disabled. 00302 * | | |1 = Spare register is Enabled. 00303 * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed. 00304 * |[5] |SPRCSTS |SPR Clear Flag 00305 * | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify tamper event is detected. 00306 * | | |0 = Spare register content is not cleared. 00307 * | | |1 = Spare register content is cleared. 00308 * | | |Writes 1 to clear this bit. 00309 * | | |Note: This bit keep 1 when RTC_INTSTS[13:8] not equal zero. 00310 * @var RTC_T::SPR[20] 00311 * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 00312 * --------------------------------------------------------------------------------------------------- 00313 * |Bits |Field |Descriptions 00314 * | :----: | :----: | :---- | 00315 * |[31:0] |SPARE |Spare Register 00316 * | | |This field is used to store back-up information defined by user. 00317 * | | |This field will be cleared by hardware automatically once a tamper pin event is detected. 00318 * | | |Before storing back-up information in to RTC_SPRx register, 00319 * | | |user should check REWNF (RTC_RWEN[16]) is enabled. 00320 * @var RTC_T::LXTCTL 00321 * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register 00322 * --------------------------------------------------------------------------------------------------- 00323 * |Bits |Field |Descriptions 00324 * | :----: | :----: | :---- | 00325 * |[2:1] |GAIN |Oscillator Gain Option 00326 * | | |User can select oscillator gain according to crystal external loading and operating temperature range 00327 * | | |The larger gain value corresponding to stronger driving capability and higher power consumption. 00328 * | | |00 = L0 mode. 00329 * | | |01 = L1 mode. 00330 * | | |10 = L2 mode. 00331 * | | |11 = L3 mode. 00332 * @var RTC_T::GPIOCTL0 00333 * Offset: 0x104 RTC GPIO Control 0 Register 00334 * --------------------------------------------------------------------------------------------------- 00335 * |Bits |Field |Descriptions 00336 * | :----: | :----: | :---- | 00337 * |[1:0] |OPMODE0 |IO Operation Mode 00338 * | | |00 = PF.4 is input only mode, without pull-up resistor. 00339 * | | |01 = PF.4 is output push pull mode. 00340 * | | |10 = PF.4 is open drain mode. 00341 * | | |11 = PF.4 is quasi-bidirectional mode with internal pull up. 00342 * |[2] |DOUT0 |IO Output Data 00343 * | | |0 = PF.4 output low. 00344 * | | |1 = PF.4 output high. 00345 * |[3] |CTLSEL0 |IO Pin State Backup Selection 00346 * | | |When low speed 32 kHz oscillator is disabled, PF.4 pin (X32KO pin) can be used as GPIO function 00347 * | | |User can program CTLSEL0 to decide PF.4 I/O function is controlled by system power domain GPIO module or 00348 * | | |VBAT power domain RTC_GPIOCTL0 control register. 00349 * | | |0 = PF.4 pin I/O function is controlled by GPIO module. 00350 * | | |Hardware auto becomes CTLSEL0 = 1 when system power is turned off. 00351 * | | |1 = PF.4 pin I/O function is controlled by VBAT power domain. 00352 * | | |PF.4 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1. 00353 * | | |Note: CTLSEL0 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. 00354 * |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable 00355 * | | |Determine PF.4 I/O pull-up or pull-down. 00356 * | | |00 = PF.4 pull-up and pull-up disable. 00357 * | | |01 = PF.4 pull-down enable. 00358 * | | |10 = PF.4 pull-up enable. 00359 * | | |11 = PF.4 pull-up and pull-up disable. 00360 * | | |Note: 00361 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 00362 * | | |The independent pull-up control register only valid when OPMODE0 set as input tri-state and open-drain mode. 00363 * | | |The independent pull-down control register only valid when OPMODE0 set as input tri-state mode. 00364 * |[9:8] |OPMODE1 |IO Operation Mode 00365 * | | |00 = PF.5 is input only mode, without pull-up resistor. 00366 * | | |01 = PF.5 is output push pull mode. 00367 * | | |10 = PF.5 is open drain mode. 00368 * | | |11 = PF.5 is quasi-bidirectional mode with internal pull up. 00369 * |[10] |DOUT1 |IO Output Data 00370 * | | |0 = PF.5 output low. 00371 * | | |1 = PF.5 output high. 00372 * |[11] |CTLSEL1 |IO Pin State Backup Selection 00373 * | | |When low speed 32 kHz oscillator is disabled, PF.5 pin (X32KI pin) can be used as GPIO function 00374 * | | |User can program CTLSEL1 to decide PF.5 I/O function is controlled by system power domain GPIO module or 00375 * | | |VBAT power domain RTC_GPIOCTL0 control register. 00376 * | | |0 = PF.5 pin I/O function is controlled by GPIO module. 00377 * | | |Hardware auto becomes CTLSEL1 = 1 when system power is turned off. 00378 * | | |1 = PF.5 pin I/O function is controlled by VBAT power domain. 00379 * | | |PF.5 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1. 00380 * | | |Note: CTLSEL1 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. 00381 * |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable 00382 * | | |Determine PF.5 I/O pull-up or pull-down. 00383 * | | |00 = PF.5 pull-up and pull-up disable. 00384 * | | |01 = PF.5 pull-down enable. 00385 * | | |10 = PF.5 pull-up enable. 00386 * | | |11 = PF.5 pull-up and pull-up disable. 00387 * | | |Note: 00388 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 00389 * | | |The independent pull-up control register only valid when OPMODE1 set as input tri-state and open-drain mode. 00390 * | | |The independent pull-down control register only valid when OPMODE1 set as input tri-state mode. 00391 * |[17:16] |OPMODE2 |IO Operation Mode 00392 * | | |00 = PF.6 is input only mode, without pull-up resistor. 00393 * | | |01 = PF.6 is output push pull mode. 00394 * | | |10 = PF.6 is open drain mode. 00395 * | | |11 = PF.6 is quasi-bidirectional mode with internal pull up. 00396 * |[18] |DOUT2 |IO Output Data 00397 * | | |0 = PF.6 output low. 00398 * | | |1 = PF.6 output high. 00399 * |[19] |CTLSEL2 |IO Pin State Backup Selection 00400 * | | |When TAMP0EN is disabled, PF.6 pin (TAMPER0 pin) can be used as GPIO function 00401 * | | |User can program CTLSEL2 to decide PF.6 I/O function is controlled by system power domain GPIO module or 00402 * | | |VBAT power domain RTC_GPIOCTL0 control register. 00403 * | | |0 = PF.6 pin I/O function is controlled by GPIO module. 00404 * | | |Hardware auto becomes CTLSEL2 = 1 when system power is turned off. 00405 * | | |1 = PF.6 pin I/O function is controlled by VBAT power domain. 00406 * | | |PF.6 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1. 00407 * | | |Note: CTLSEL2 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. 00408 * |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable 00409 * | | |Determine PF.6 I/O pull-up or pull-down. 00410 * | | |00 = PF.6 pull-up and pull-up disable. 00411 * | | |01 = PF.6 pull-down enable. 00412 * | | |10 = PF.6 pull-up enable. 00413 * | | |11 = PF.6 pull-up and pull-up disable. 00414 * | | |Note1: 00415 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 00416 * | | |The independent pull-up control register only valid when OPMODE2 set as input tri-state and open-drain mode. 00417 * | | |The independent pull-down control register only valid when OPMODE2 set as input tri-state mode. 00418 * |[25:24] |OPMODE3 |IO Operation Mode 00419 * | | |00 = PF.7 is input only mode, without pull-up resistor. 00420 * | | |01 = PF.7 is output push pull mode. 00421 * | | |10 = PF.7 is open drain mode. 00422 * | | |11 = PF.7 is quasi-bidirectional mode. 00423 * |[26] |DOUT3 |IO Output Data 00424 * | | |0 = PF.7 output low. 00425 * | | |1 = PF.7 output high. 00426 * |[27] |CTLSEL3 |IO Pin State Backup Selection 00427 * | | |When TAMP1EN is disabled, PF.7 pin (TAMPER1 pin) can be used as GPIO function 00428 * | | |User can program CTLSEL3 to decide PF.7 I/O function is controlled by system power domain GPIO module or 00429 * | | |VBAT power domain RTC_GPIOCTL0 control register. 00430 * | | |0 = PF.7 pin I/O function is controlled by GPIO module. 00431 * | | |Hardware auto becomes CTLSEL3 = 1 when system power is turned off. 00432 * | | |1 = PF.7 pin I/O function is controlled by VBAT power domain. 00433 * | | |PF.7 pin function and I/O status are controlled by OPMODE3[1:0] and DOUT3 after CTLSEL3 is set to 1. 00434 * | | |Note: CTLSEL3 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 00435 * |[29:28] |PUSEL3 |IO Pull-up and Pull-down Enable 00436 * | | |Determine PF.7 I/O pull-up or pull-down. 00437 * | | |00 = PF.7 pull-up and pull-down disable. 00438 * | | |01 = PF.7 pull-down enable. 00439 * | | |10 = PF.7 pull-up enable. 00440 * | | |11 = PF.7 pull-up and pull-down disable. 00441 * | | |Note: 00442 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 00443 * | | |The independent pull-up control register only valid when OPMODE3 set as input tri-state and open-drain mode. 00444 * | | |The independent pull-down control register only valid when OPMODE3 set as input tri-state mode. 00445 * @var RTC_T::GPIOCTL1 00446 * Offset: 0x108 RTC GPIO Control 1 Register 00447 * --------------------------------------------------------------------------------------------------- 00448 * |Bits |Field |Descriptions 00449 * | :----: | :----: | :---- | 00450 * |[1:0] |OPMODE4 |IO Operation Mode 00451 * | | |00 = PF.8 is input only mode, without pull-up resistor. 00452 * | | |01 = PF.8 is output push pull mode. 00453 * | | |10 = PF.8 is open drain mode. 00454 * | | |11 = PF.8 is quasi-bidirectional mode. 00455 * |[2] |DOUT4 |IO Output Data 00456 * | | |0 = PF.8 output low. 00457 * | | |1 = PF.8 output high. 00458 * |[3] |CTLSEL4 |IO Pin State Backup Selection 00459 * | | |When TAMP2EN is disabled, PF.8 pin (TAMPER2 pin) can be used as GPIO function 00460 * | | |User can program CTLSEL4 to decide PF.8 I/O function is controlled by system power domain GPIO module or 00461 * | | |VBAT power domain RTC_GPIOCTL1 control register. 00462 * | | |0 = PF.8 pin I/O function is controlled by GPIO module. 00463 * | | |Hardware auto becomes CTLSEL4 = 1 when system power is turned off. 00464 * | | |1 = PF.8 pin I/O function is controlled by VBAT power domain. 00465 * | | |PF.8 pin function and I/O status are controlled by OPMODE4[1:0] and DOUT4 after CTLSEL4 is set to 1. 00466 * | | |Note: CTLSEL4 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 00467 * |[5:4] |PUSEL4 |IO Pull-up and Pull-down Enable 00468 * | | |Determine PF.8 I/O pull-up or pull-down. 00469 * | | |00 = PF.8 pull-up and pull-down disable. 00470 * | | |01 = PF.8 pull-down enable. 00471 * | | |10 = PF.8 pull-up enable. 00472 * | | |11 = PF.8 pull-up and pull-down disable. 00473 * | | |Note: 00474 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 00475 * | | |The independent pull-up control register only valid when OPMODE4 set as input tri-state and open-drain mode. 00476 * | | |The independent pull-down control register only valid when OPMODE4 set as input tri-state mode. 00477 * |[9:8] |OPMODE5 |IO Operation Mode 00478 * | | |00 = PF.9 is input only mode, without pull-up resistor. 00479 * | | |01 = PF.9 is output push pull mode. 00480 * | | |10 = PF.9 is open drain mode. 00481 * | | |11 = PF.9 is quasi-bidirectional mode. 00482 * |[10] |DOUT5 |IO Output Data 00483 * | | |0 = PF.9 output low. 00484 * | | |1 = PF.9 output high. 00485 * |[11] |CTLSEL5 |IO Pin State Backup Selection 00486 * | | |When TAMP3EN is disabled, PF.9 pin (TAMPER3 pin) can be used as GPIO function 00487 * | | |User can program CTLSEL5 to decide PF.9 I/O function is controlled by system power domain GPIO module or 00488 * | | |VBAT power domain RTC_GPIOCTL1 control register. 00489 * | | |0 = PF.9 pin I/O function is controlled by GPIO module. 00490 * | | |Hardware auto becomes CTLSEL5 = 1 when system power is turned off. 00491 * | | |1 = PF.9 pin I/O function is controlled by VBAT power domain. 00492 * | | |PF.9 pin function and I/O status are controlled by OPMODE5[1:0] and DOUT5 after CTLSEL5 is set to 1. 00493 * | | |Note: CTLSEL5 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. 00494 * |[13:12] |PUSEL5 |IO Pull-up and Pull-down Enable 00495 * | | |Determine PF.9 I/O pull-up or pull-down. 00496 * | | |00 = PF.9 pull-up and pull-down disable. 00497 * | | |01 = PF.9 pull-down enable. 00498 * | | |10 = PF.9 pull-up enable. 00499 * | | |11 = PF.9 pull-up and pull-down disable. 00500 * | | |Note: 00501 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 00502 * | | |The independent pull-up control register only valid when OPMODE5 set as input tri-state and open-drain mode. 00503 * | | |The independent pull-down control register only valid when OPMODE5 set as input tri-state mode. 00504 * |[17:16] |OPMODE6 |IO Operation Mode 00505 * | | |00 = PF.10 is input only mode, without pull-up resistor. 00506 * | | |01 = PF.10 is output push pull mode. 00507 * | | |10 = PF.10 is open drain mode. 00508 * | | |11 = PF.10 is quasi-bidirectional mode. 00509 * |[18] |DOUT6 |IO Output Data 00510 * | | |0 = PF.10 output low. 00511 * | | |1 = PF.10 output high. 00512 * |[19] |CTLSEL6 |IO Pin State Backup Selection 00513 * | | |When TAMP4EN is disabled, PF.10 pin (TAMPER4 pin) can be used as GPIO function 00514 * | | |User can program CTLSEL6 to decide PF.10 I/O function is controlled by system power domain GPIO module or 00515 * | | |VBAT power domain RTC_GPIOCTL1 control register. 00516 * | | |0 = PF.10 pin I/O function is controlled by GPIO module. 00517 * | | |Hardware auto becomes CTLSEL6 = 1 when system power is turned off. 00518 * | | |1 = PF.10 pin I/O function is controlled by VBAT power domain. 00519 * | | |PF.10 pin function and I/O status are controlled by OPMODE6[1:0] and DOUT6 after CTLSEL6 is set to 1. 00520 * | | |Note: CTLSEL6 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. 00521 * |[21:20] |PUSEL6 |IO Pull-up and Pull-down Enable 00522 * | | |Determine PF.10 I/O pull-up or pull-down. 00523 * | | |00 = PF.10 pull-up and pull-down disable. 00524 * | | |01 = PF.10 pull-down enable. 00525 * | | |10 = PF.10 pull-up enable. 00526 * | | |11 = PF.10 pull-up and pull-down disable. 00527 * | | |Note: 00528 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 00529 * | | |The independent pull-up control register only valid when OPMODE6 set as input tri-state and open-drain mode. 00530 * | | |The independent pull-down control register only valid when OPMODE6 set as input tri-state mode. 00531 * |[25:24] |OPMODE7 |IO Operation Mode 00532 * | | |00 = PF.11 is input only mode, without pull-up resistor. 00533 * | | |01 = PF.11 is output push pull mode. 00534 * | | |10 = PF.11 is open drain mode. 00535 * | | |11 = PF.11 is quasi-bidirectional mode. 00536 * |[26] |DOUT7 |IO Output Data 00537 * | | |0 = PF.11 output low. 00538 * | | |1 = PF.11 output high. 00539 * |[27] |CTLSEL7 |IO Pin State Backup Selection 00540 * | | |When TAMP5EN is disabled, PF.11 pin (TAMPER5 pin) can be used as GPIO function 00541 * | | |User can program CTLSEL7 to decide PF.11 I/O function is controlled by system power domain GPIO module or 00542 * | | |VBAT power domain RTC_GPIOCTL1 control register. 00543 * | | |0 = PF.11 pin I/O function is controlled by GPIO module. 00544 * | | |Hardware auto becomes CTLSEL7 = 1 when system power is turned off. 00545 * | | |1 = PF.11 pin I/O function is controlled by VBAT power domain. 00546 * | | |PF.11 pin function and I/O status are controlled by OPMODE7[1:0] and DOUT7 after CTLSEL7 is set to 1. 00547 * | | |Note: CTLSEL7 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1. 00548 * |[29:28] |PUSEL7 |IO Pull-up and Pull-down Enable 00549 * | | |Determine PF.11 I/O pull-up or pull-down. 00550 * | | |00 = PF.11 pull-up and pull-down disable. 00551 * | | |01 = PF.11 pull-down enable. 00552 * | | |10 = PF.11 pull-up enable. 00553 * | | |11 = PF.11 pull-up and pull-down disable. 00554 * | | |Note: 00555 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 00556 * | | |The independent pull-up control register only valid when OPMODE7 set as input tri-state and open-drain mode. 00557 * | | |The independent pull-down control register only valid when OPMODE7 set as input tri-state mode. 00558 * @var RTC_T::DSTCTL 00559 * Offset: 0x110 RTC Daylight Saving Time Control Register 00560 * --------------------------------------------------------------------------------------------------- 00561 * |Bits |Field |Descriptions 00562 * | :----: | :----: | :---- | 00563 * |[0] |ADDHR |Add 1 Hour 00564 * | | |0 = No effect. 00565 * | | |1 = Indicates RTC hour digit has been added one hour for summer time change. 00566 * |[1] |SUBHR |Subtract 1 Hour 00567 * | | |0 = No effect. 00568 * | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change. 00569 * |[2] |DSBAK |Daylight Saving Back 00570 * | | |0= Normal mode. 00571 * | | |1= Daylight saving mode. 00572 * @var RTC_T::TAMPCTL 00573 * Offset: 0x120 RTC Tamper Pin Control Register 00574 * --------------------------------------------------------------------------------------------------- 00575 * |Bits |Field |Descriptions 00576 * | :----: | :----: | :---- | 00577 * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select 00578 * | | |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. 00579 * | | |0 = Tamper input is from Tamper 2. 00580 * | | |1 = Tamper input is from Tamper 0. 00581 * | | |Note: This bit has effect only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set 00582 * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select 00583 * | | |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. 00584 * | | |0 = Tamper input is from Tamper 4. 00585 * | | |1 = Tamper input is from Tamper 0. 00586 * | | |Note: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set 00587 * |[3:2] |DYNSRC |Dynamic Reference Pattern 00588 * | | |This fields determine the new reference pattern when current pattern run out in dynamic pair mode. 00589 * | | |00 or 10 = The new reference pattern is generated by random number generator when the reference pattern run out. 00590 * | | |01 = The new reference pattern is repeated previous random value when the reference pattern run out. 00591 * | | |11 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out. 00592 * | | |Note: After revise this bit, the SEEDRLD (RTC_TAMPCTL[4]) should be set. 00593 * |[4] |SEEDRLD |Reload New Seed for PRNG Engine 00594 * | | |Setting this bit, the tamper configuration will be reload. 00595 * | | |0 = Generating key based on the current seed. 00596 * | | |1 = Reload new seed. 00597 * | | |Note: Before set this bit, the tamper configuration should be set to complete. 00598 * |[7:5] |DYNRATE |Dynamic Change Rate 00599 * | | |This item is choice the dynamic tamper output change rate. 00600 * | | |000 = 210 * RTC_CLK. 00601 * | | |001 = 211 * RTC_CLK. 00602 * | | |010 = 212 * RTC_CLK. 00603 * | | |011 = 213 * RTC_CLK. 00604 * | | |100 = 214 * RTC_CLK. 00605 * | | |101 = 215 * RTC_CLK. 00606 * | | |110 = 216 * RTC_CLK. 00607 * | | |111 = 217 * RTC_CLK. 00608 * | | |Note: After revise this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately. 00609 * |[8] |TAMP0EN |Tamper0 Detect Enable Bit 00610 * | | |0 = Tamper 0 detect Disabled. 00611 * | | |1 = Tamper 0 detect Enabled. 00612 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. 00613 * |[9] |TAMP0LV |Tamper 0 Level 00614 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 00615 * | | |0 = Detect voltage level is low. 00616 * | | |1 = Detect voltage level is high. 00617 * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit 00618 * | | |0 = Tamper 0 de-bounce Disabled. 00619 * | | |1 = Tamper 0 de-bounce Enabled. 00620 * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit 00621 * | | |0 = Tamper 1 detect Disabled. 00622 * | | |1 = Tamper 1 detect Enabled. 00623 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. 00624 * |[13] |TAMP1LV |Tamper 1 Level 00625 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 00626 * | | |0 = Detect voltage level is low. 00627 * | | |1 = Detect voltage level is high. 00628 * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit 00629 * | | |0 = Tamper 1 de-bounce Disabled. 00630 * | | |1 = Tamper 1 de-bounce Enabled. 00631 * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit 00632 * | | |0 = Static detect. 00633 * | | |1 = Dynamic detect. 00634 * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit 00635 * | | |0 = Tamper 2 detect Disabled. 00636 * | | |1 = Tamper 2 detect Enabled. 00637 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. 00638 * |[17] |TAMP2LV |Tamper 2 Level 00639 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 00640 * | | |0 = Detect voltage level is low. 00641 * | | |1 = Detect voltage level is high. 00642 * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit 00643 * | | |0 = Tamper 2 de-bounce Disabled. 00644 * | | |1 = Tamper 2 de-bounce Enabled. 00645 * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit 00646 * | | |0 = Tamper 3 detect Disabled. 00647 * | | |1 = Tamper 3 detect Enabled. 00648 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. 00649 * |[21] |TAMP3LV |Tamper 3 Level 00650 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 00651 * | | |0 = Detect voltage level is low. 00652 * | | |1 = Detect voltage level is high. 00653 * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit 00654 * | | |0 = Tamper 3 de-bounce Disabled. 00655 * | | |1 = Tamper 3 de-bounce Enabled. 00656 * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit 00657 * | | |0 = Static detect. 00658 * | | |1 = Dynamic detect. 00659 * |[24] |TAMP4EN |Tamper4 Detect Enable Bit 00660 * | | |0 = Tamper 4 detect Disabled. 00661 * | | |1 = Tamper 4 detect Enabled. 00662 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. 00663 * |[25] |TAMP4LV |Tamper 4 Level 00664 * | | |This bit depends on level attribute of tamper pin for static tamper detection. 00665 * | | |0 = Detect voltage level is low. 00666 * | | |1 = Detect voltage level is high. 00667 * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit 00668 * | | |0 = Tamper 4 de-bounce Disabled. 00669 * | | |1 = Tamper 4 de-bounce Enabled. 00670 * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit 00671 * | | |0 = Tamper 5 detect Disabled. 00672 * | | |1 = Tamper 5 detect Enabled. 00673 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. 00674 * |[29] |TAMP5LV |Tamper 5 Level 00675 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 00676 * | | |0 = Detect voltage level is low. 00677 * | | |1 = Detect voltage level is high. 00678 * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit 00679 * | | |0 = Tamper 5 de-bounce Disabled. 00680 * | | |1 = Tamper 5 de-bounce Enabled. 00681 * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit 00682 * | | |0 = Static detect. 00683 * | | |1 = Dynamic detect. 00684 * @var RTC_T::TAMPSEED 00685 * Offset: 0x128 RTC Tamper Dynamic Seed Register 00686 * --------------------------------------------------------------------------------------------------- 00687 * |Bits |Field |Descriptions 00688 * | :----: | :----: | :---- | 00689 * |[31:0] |SEED |Seed Value 00690 * @var RTC_T::TAMPTIME 00691 * Offset: 0x130 RTC Tamper Time Register 00692 * --------------------------------------------------------------------------------------------------- 00693 * |Bits |Field |Descriptions 00694 * | :----: | :----: | :---- | 00695 * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9) 00696 * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5) 00697 * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9) 00698 * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5) 00699 * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9) 00700 * |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2) 00701 * | | |Note: 24-hour time scale only. 00702 * @var RTC_T::TAMPCAL 00703 * Offset: 0x134 RTC Tamper Calendar Register 00704 * --------------------------------------------------------------------------------------------------- 00705 * |Bits |Field |Descriptions 00706 * | :----: | :----: | :---- | 00707 * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9) 00708 * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3) 00709 * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9) 00710 * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1) 00711 * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9) 00712 * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9) 00713 */ 00714 __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */ 00715 __IO uint32_t RWEN; /*!< [0x0004] RTC Access Enable Register */ 00716 __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */ 00717 __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */ 00718 __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */ 00719 __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */ 00720 __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */ 00721 __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */ 00722 __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */ 00723 __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */ 00724 __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */ 00725 __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */ 00726 __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */ 00727 __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */ 00728 __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */ 00729 __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */ 00730 __IO uint32_t SPR[20]; /*!< [0x0040] ~ [0x008c] RTC Spare Register 0 ~ 19 */ 00731 /// @cond HIDDEN_SYMBOLS 00732 __I uint32_t RESERVE0[28]; 00733 /// @endcond //HIDDEN_SYMBOLS 00734 __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */ 00735 __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */ 00736 __IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */ 00737 /// @cond HIDDEN_SYMBOLS 00738 __I uint32_t RESERVE1[1]; 00739 /// @endcond //HIDDEN_SYMBOLS 00740 __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */ 00741 /// @cond HIDDEN_SYMBOLS 00742 __I uint32_t RESERVE2[3]; 00743 /// @endcond //HIDDEN_SYMBOLS 00744 __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */ 00745 /// @cond HIDDEN_SYMBOLS 00746 __I uint32_t RESERVE3[1]; 00747 /// @endcond //HIDDEN_SYMBOLS 00748 __IO uint32_t TAMPSEED; /*!< [0x0128] RTC Tamper Dynamic Seed Register */ 00749 /// @cond HIDDEN_SYMBOLS 00750 __I uint32_t RESERVE4[1]; 00751 /// @endcond //HIDDEN_SYMBOLS 00752 __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */ 00753 __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */ 00754 00755 } RTC_T; 00756 00757 /** 00758 @addtogroup RTC_CONST RTC Bit Field Definition 00759 Constant Definitions for RTC Controller 00760 @{ */ 00761 00762 #define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: INIT_ACTIVE Position */ 00763 #define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: INIT_ACTIVE Mask */ 00764 00765 #define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */ 00766 #define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */ 00767 00768 #define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */ 00769 #define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */ 00770 00771 #define RTC_RWEN_RTCBUSY_Pos (24) /*!< RTC_T::RWEN: RTCBUSY Position */ 00772 #define RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos) /*!< RTC_T::RWEN: RTCBUSY Mask */ 00773 00774 #define RTC_FREQADJ_FREQADJ_Pos (0) /*!< RTC_T::FREQADJ: FREQADJ Position */ 00775 #define RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FREQADJ_FREQADJ_Pos) /*!< RTC_T::FREQADJ: FREQADJ Mask */ 00776 00777 #define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */ 00778 #define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */ 00779 00780 #define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */ 00781 #define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */ 00782 00783 #define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */ 00784 #define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */ 00785 00786 #define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */ 00787 #define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */ 00788 00789 #define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */ 00790 #define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */ 00791 00792 #define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */ 00793 #define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */ 00794 00795 #define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */ 00796 #define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */ 00797 00798 #define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */ 00799 #define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */ 00800 00801 #define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */ 00802 #define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */ 00803 00804 #define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */ 00805 #define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */ 00806 00807 #define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */ 00808 #define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */ 00809 00810 #define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */ 00811 #define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */ 00812 00813 #define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */ 00814 #define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */ 00815 00816 #define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */ 00817 #define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */ 00818 00819 #define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */ 00820 #define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */ 00821 00822 #define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */ 00823 #define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */ 00824 00825 #define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */ 00826 #define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */ 00827 00828 #define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */ 00829 #define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */ 00830 00831 #define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */ 00832 #define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */ 00833 00834 #define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */ 00835 #define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */ 00836 00837 #define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */ 00838 #define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */ 00839 00840 #define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */ 00841 #define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */ 00842 00843 #define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */ 00844 #define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */ 00845 00846 #define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */ 00847 #define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */ 00848 00849 #define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */ 00850 #define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */ 00851 00852 #define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */ 00853 #define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */ 00854 00855 #define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */ 00856 #define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */ 00857 00858 #define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */ 00859 #define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */ 00860 00861 #define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */ 00862 #define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */ 00863 00864 #define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */ 00865 #define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */ 00866 00867 #define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */ 00868 #define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */ 00869 00870 #define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */ 00871 #define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */ 00872 00873 #define RTC_INTEN_TAMP3IEN_Pos (11) /*!< RTC_T::INTEN: TAMP3IEN Position */ 00874 #define RTC_INTEN_TAMP3IEN_Msk (0x1ul << RTC_INTEN_TAMP3IEN_Pos) /*!< RTC_T::INTEN: TAMP3IEN Mask */ 00875 00876 #define RTC_INTEN_TAMP4IEN_Pos (12) /*!< RTC_T::INTEN: TAMP4IEN Position */ 00877 #define RTC_INTEN_TAMP4IEN_Msk (0x1ul << RTC_INTEN_TAMP4IEN_Pos) /*!< RTC_T::INTEN: TAMP4IEN Mask */ 00878 00879 #define RTC_INTEN_TAMP5IEN_Pos (13) /*!< RTC_T::INTEN: TAMP5IEN Position */ 00880 #define RTC_INTEN_TAMP5IEN_Msk (0x1ul << RTC_INTEN_TAMP5IEN_Pos) /*!< RTC_T::INTEN: TAMP5IEN Mask */ 00881 00882 #define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */ 00883 #define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */ 00884 00885 #define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */ 00886 #define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */ 00887 00888 #define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */ 00889 #define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */ 00890 00891 #define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */ 00892 #define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */ 00893 00894 #define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */ 00895 #define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */ 00896 00897 #define RTC_INTSTS_TAMP3IF_Pos (11) /*!< RTC_T::INTSTS: TAMP3IF Position */ 00898 #define RTC_INTSTS_TAMP3IF_Msk (0x1ul << RTC_INTSTS_TAMP3IF_Pos) /*!< RTC_T::INTSTS: TAMP3IF Mask */ 00899 00900 #define RTC_INTSTS_TAMP4IF_Pos (12) /*!< RTC_T::INTSTS: TAMP4IF Position */ 00901 #define RTC_INTSTS_TAMP4IF_Msk (0x1ul << RTC_INTSTS_TAMP4IF_Pos) /*!< RTC_T::INTSTS: TAMP4IF Mask */ 00902 00903 #define RTC_INTSTS_TAMP5IF_Pos (13) /*!< RTC_T::INTSTS: TAMP5IF Position */ 00904 #define RTC_INTSTS_TAMP5IF_Msk (0x1ul << RTC_INTSTS_TAMP5IF_Pos) /*!< RTC_T::INTSTS: TAMP5IF Mask */ 00905 00906 #define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */ 00907 #define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */ 00908 00909 #define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */ 00910 #define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */ 00911 00912 #define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */ 00913 #define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */ 00914 00915 #define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */ 00916 #define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */ 00917 00918 #define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */ 00919 #define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */ 00920 00921 #define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */ 00922 #define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */ 00923 00924 #define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */ 00925 #define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */ 00926 00927 #define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */ 00928 #define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */ 00929 00930 #define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */ 00931 #define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */ 00932 00933 #define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */ 00934 #define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */ 00935 00936 #define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */ 00937 #define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */ 00938 00939 #define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */ 00940 #define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */ 00941 00942 #define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */ 00943 #define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */ 00944 00945 #define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */ 00946 #define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */ 00947 00948 #define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */ 00949 #define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */ 00950 00951 #define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */ 00952 #define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */ 00953 00954 #define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */ 00955 #define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */ 00956 00957 #define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */ 00958 #define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */ 00959 00960 #define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */ 00961 #define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */ 00962 00963 #define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */ 00964 #define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */ 00965 00966 #define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */ 00967 #define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */ 00968 00969 #define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */ 00970 #define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */ 00971 00972 #define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */ 00973 #define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */ 00974 00975 #define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */ 00976 #define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */ 00977 00978 #define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */ 00979 #define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */ 00980 00981 #define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */ 00982 #define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */ 00983 00984 #define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */ 00985 #define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */ 00986 00987 #define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */ 00988 #define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */ 00989 00990 #define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */ 00991 #define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */ 00992 00993 #define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */ 00994 #define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */ 00995 00996 #define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */ 00997 #define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */ 00998 00999 #define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */ 01000 #define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */ 01001 01002 #define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */ 01003 #define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */ 01004 01005 #define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */ 01006 #define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */ 01007 01008 #define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */ 01009 #define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */ 01010 01011 #define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */ 01012 #define RTC_LXTCTL_GAIN_Msk (0x3ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */ 01013 01014 #define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */ 01015 #define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */ 01016 01017 #define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */ 01018 #define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */ 01019 01020 #define RTC_GPIOCTL0_CTLSEL0_Pos (3) /*!< RTC_T::GPIOCTL0: CTLSEL0 Position */ 01021 #define RTC_GPIOCTL0_CTLSEL0_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL0_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL0 Mask */ 01022 01023 #define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */ 01024 #define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */ 01025 01026 #define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */ 01027 #define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */ 01028 01029 #define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */ 01030 #define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */ 01031 01032 #define RTC_GPIOCTL0_CTLSEL1_Pos (11) /*!< RTC_T::GPIOCTL0: CTLSEL1 Position */ 01033 #define RTC_GPIOCTL0_CTLSEL1_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL1_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL1 Mask */ 01034 01035 #define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */ 01036 #define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */ 01037 01038 #define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */ 01039 #define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */ 01040 01041 #define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */ 01042 #define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */ 01043 01044 #define RTC_GPIOCTL0_CTLSEL2_Pos (19) /*!< RTC_T::GPIOCTL0: CTLSEL2 Position */ 01045 #define RTC_GPIOCTL0_CTLSEL2_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL2_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL2 Mask */ 01046 01047 #define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */ 01048 #define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */ 01049 01050 #define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */ 01051 #define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */ 01052 01053 #define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */ 01054 #define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */ 01055 01056 #define RTC_GPIOCTL0_CTLSEL3_Pos (27) /*!< RTC_T::GPIOCTL0: CTLSEL3 Position */ 01057 #define RTC_GPIOCTL0_CTLSEL3_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL3_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL3 Mask */ 01058 01059 #define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */ 01060 #define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */ 01061 01062 #define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */ 01063 #define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */ 01064 01065 #define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */ 01066 #define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */ 01067 01068 #define RTC_GPIOCTL1_CTLSEL4_Pos (3) /*!< RTC_T::GPIOCTL1: CTLSEL4 Position */ 01069 #define RTC_GPIOCTL1_CTLSEL4_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL4_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL4 Mask */ 01070 01071 #define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */ 01072 #define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */ 01073 01074 #define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */ 01075 #define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */ 01076 01077 #define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */ 01078 #define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */ 01079 01080 #define RTC_GPIOCTL1_CTLSEL5_Pos (11) /*!< RTC_T::GPIOCTL1: CTLSEL5 Position */ 01081 #define RTC_GPIOCTL1_CTLSEL5_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL5_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL5 Mask */ 01082 01083 #define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */ 01084 #define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */ 01085 01086 #define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */ 01087 #define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */ 01088 01089 #define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */ 01090 #define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */ 01091 01092 #define RTC_GPIOCTL1_CTLSEL6_Pos (19) /*!< RTC_T::GPIOCTL1: CTLSEL6 Position */ 01093 #define RTC_GPIOCTL1_CTLSEL6_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL6_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL6 Mask */ 01094 01095 #define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */ 01096 #define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */ 01097 01098 #define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */ 01099 #define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */ 01100 01101 #define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */ 01102 #define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */ 01103 01104 #define RTC_GPIOCTL1_CTLSEL7_Pos (27) /*!< RTC_T::GPIOCTL1: CTLSEL7 Position */ 01105 #define RTC_GPIOCTL1_CTLSEL7_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL7_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL7 Mask */ 01106 01107 #define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */ 01108 #define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */ 01109 01110 #define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */ 01111 #define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */ 01112 01113 #define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */ 01114 #define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */ 01115 01116 #define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */ 01117 #define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */ 01118 01119 #define RTC_TAMPCTL_DYN1ISS_Pos (0) /*!< RTC_T::TAMPCTL: DYN1ISS Position */ 01120 #define RTC_TAMPCTL_DYN1ISS_Msk (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos) /*!< RTC_T::TAMPCTL: DYN1ISS Mask */ 01121 01122 #define RTC_TAMPCTL_DYN2ISS_Pos (1) /*!< RTC_T::TAMPCTL: DYN2ISS Position */ 01123 #define RTC_TAMPCTL_DYN2ISS_Msk (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos) /*!< RTC_T::TAMPCTL: DYN2ISS Mask */ 01124 01125 #define RTC_TAMPCTL_DYNSRC_Pos (2) /*!< RTC_T::TAMPCTL: DYNSRC Position */ 01126 #define RTC_TAMPCTL_DYNSRC_Msk (0x3ul << RTC_TAMPCTL_DYNSRC_Pos) /*!< RTC_T::TAMPCTL: DYNSRC Mask */ 01127 01128 #define RTC_TAMPCTL_SEEDRLD_Pos (4) /*!< RTC_T::TAMPCTL: SEEDRLD Position */ 01129 #define RTC_TAMPCTL_SEEDRLD_Msk (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos) /*!< RTC_T::TAMPCTL: SEEDRLD Mask */ 01130 01131 #define RTC_TAMPCTL_DYNRATE_Pos (5) /*!< RTC_T::TAMPCTL: DYNRATE Position */ 01132 #define RTC_TAMPCTL_DYNRATE_Msk (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< RTC_T::TAMPCTL: DYNRATE Mask */ 01133 01134 #define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */ 01135 #define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */ 01136 01137 #define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */ 01138 #define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */ 01139 01140 #define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */ 01141 #define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */ 01142 01143 #define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */ 01144 #define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */ 01145 01146 #define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */ 01147 #define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */ 01148 01149 #define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */ 01150 #define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */ 01151 01152 #define RTC_TAMPCTL_DYNPR0EN_Pos (15) /*!< RTC_T::TAMPCTL: DYNPR0EN Position */ 01153 #define RTC_TAMPCTL_DYNPR0EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR0EN Mask */ 01154 01155 #define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */ 01156 #define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */ 01157 01158 #define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */ 01159 #define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */ 01160 01161 #define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */ 01162 #define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */ 01163 01164 #define RTC_TAMPCTL_TAMP3EN_Pos (20) /*!< RTC_T::TAMPCTL: TAMP3EN Position */ 01165 #define RTC_TAMPCTL_TAMP3EN_Msk (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos) /*!< RTC_T::TAMPCTL: TAMP3EN Mask */ 01166 01167 #define RTC_TAMPCTL_TAMP3LV_Pos (21) /*!< RTC_T::TAMPCTL: TAMP3LV Position */ 01168 #define RTC_TAMPCTL_TAMP3LV_Msk (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos) /*!< RTC_T::TAMPCTL: TAMP3LV Mask */ 01169 01170 #define RTC_TAMPCTL_TAMP3DBEN_Pos (22) /*!< RTC_T::TAMPCTL: TAMP3DBEN Position */ 01171 #define RTC_TAMPCTL_TAMP3DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask */ 01172 01173 #define RTC_TAMPCTL_DYNPR1EN_Pos (23) /*!< RTC_T::TAMPCTL: DYNPR1EN Position */ 01174 #define RTC_TAMPCTL_DYNPR1EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR1EN Mask */ 01175 01176 #define RTC_TAMPCTL_TAMP4EN_Pos (24) /*!< RTC_T::TAMPCTL: TAMP4EN Position */ 01177 #define RTC_TAMPCTL_TAMP4EN_Msk (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos) /*!< RTC_T::TAMPCTL: TAMP4EN Mask */ 01178 01179 #define RTC_TAMPCTL_TAMP4LV_Pos (25) /*!< RTC_T::TAMPCTL: TAMP4LV Position */ 01180 #define RTC_TAMPCTL_TAMP4LV_Msk (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos) /*!< RTC_T::TAMPCTL: TAMP4LV Mask */ 01181 01182 #define RTC_TAMPCTL_TAMP4DBEN_Pos (26) /*!< RTC_T::TAMPCTL: TAMP4DBEN Position */ 01183 #define RTC_TAMPCTL_TAMP4DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask */ 01184 01185 #define RTC_TAMPCTL_TAMP5EN_Pos (28) /*!< RTC_T::TAMPCTL: TAMP5EN Position */ 01186 #define RTC_TAMPCTL_TAMP5EN_Msk (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos) /*!< RTC_T::TAMPCTL: TAMP5EN Mask */ 01187 01188 #define RTC_TAMPCTL_TAMP5LV_Pos (29) /*!< RTC_T::TAMPCTL: TAMP5LV Position */ 01189 #define RTC_TAMPCTL_TAMP5LV_Msk (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos) /*!< RTC_T::TAMPCTL: TAMP5LV Mask */ 01190 01191 #define RTC_TAMPCTL_TAMP5DBEN_Pos (30) /*!< RTC_T::TAMPCTL: TAMP5DBEN Position */ 01192 #define RTC_TAMPCTL_TAMP5DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask */ 01193 01194 #define RTC_TAMPCTL_DYNPR2EN_Pos (31) /*!< RTC_T::TAMPCTL: DYNPR2EN Position */ 01195 #define RTC_TAMPCTL_DYNPR2EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR2EN Mask */ 01196 01197 #define RTC_TAMPSEED_SEED_Pos (0) /*!< RTC_T::TAMPSEED: SEED Position */ 01198 #define RTC_TAMPSEED_SEED_Msk (0xfffffffful << RTC_TAMPSEED_SEED_Pos) /*!< RTC_T::TAMPSEED: SEED Mask */ 01199 01200 #define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */ 01201 #define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */ 01202 01203 #define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */ 01204 #define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */ 01205 01206 #define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */ 01207 #define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */ 01208 01209 #define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */ 01210 #define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */ 01211 01212 #define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */ 01213 #define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */ 01214 01215 #define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */ 01216 #define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */ 01217 01218 #define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */ 01219 #define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */ 01220 01221 #define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */ 01222 #define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */ 01223 01224 #define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */ 01225 #define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */ 01226 01227 #define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */ 01228 #define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */ 01229 01230 #define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */ 01231 #define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */ 01232 01233 #define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */ 01234 #define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */ 01235 01236 01237 /**@}*/ /* RTC_CONST */ 01238 /**@}*/ /* end of RTC register group */ 01239 /**@}*/ /* end of REGISTER group */ 01240 01241 #if defined ( __CC_ARM ) 01242 #pragma no_anon_unions 01243 #endif 01244 01245 #endif /* __RTC_REG_H__ */
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