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m480_hsusbd_reg.h
00001 /**************************************************************************//** 00002 * @file hsusbd_reg.h 00003 * @version V1.00 00004 * @brief HSUSBD register definition header file 00005 * 00006 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. 00007 * 00008 * Redistribution and use in source and binary forms, with or without modification, 00009 * are permitted provided that the following conditions are met: 00010 * 1. Redistributions of source code must retain the above copyright notice, 00011 * this list of conditions and the following disclaimer. 00012 * 2. Redistributions in binary form must reproduce the above copyright notice, 00013 * this list of conditions and the following disclaimer in the documentation 00014 * and/or other materials provided with the distribution. 00015 * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors 00016 * may be used to endorse or promote products derived from this software 00017 * without specific prior written permission. 00018 * 00019 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00020 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00021 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00022 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00023 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00024 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00025 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00026 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00027 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00028 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00029 *****************************************************************************/ 00030 #ifndef __HSUSBD_REG_H__ 00031 #define __HSUSBD_REG_H__ 00032 00033 #if defined ( __CC_ARM ) 00034 #pragma anon_unions 00035 #endif 00036 00037 /** 00038 @addtogroup REGISTER Control Register 00039 @{ 00040 */ 00041 00042 /** 00043 @addtogroup HSUSBD USB 2.0 Device Controller(HSUSBD) 00044 Memory Mapped Structure for HSUSBD Controller 00045 @{ */ 00046 00047 typedef struct { 00048 00049 /** 00050 * @var HSUSBD_EP_T::EPDAT 00051 * Offset: 0x00 Endpoint n Data Register 00052 * --------------------------------------------------------------------------------------------------- 00053 * |Bits |Field |Descriptions 00054 * | :----: | :----: | :---- | 00055 * |[31:0] |EPDAT |Endpoint A~L Data Register 00056 * | | |Endpoint A~L data buffer for the buffer transaction (read or write). 00057 * | | |Note: Only word access is supported. 00058 * @var HSUSBD_EP_T::EPDAT_BYTE 00059 * Offset: 0x00 Endpoint n Data Register 00060 * --------------------------------------------------------------------------------------------------- 00061 * |Bits |Field |Descriptions 00062 * | :----: | :----: | :---- | 00063 * |[7:0] |EPDAT |Endpoint A~L Data Register 00064 * | | |Endpoint A~L data buffer for the buffer transaction (read or write). 00065 * | | |Note: Only byte access is supported. 00066 * @var HSUSBD_EP_T::EPINTSTS 00067 * Offset: 0x04 Endpoint n Interrupt Status Register 00068 * --------------------------------------------------------------------------------------------------- 00069 * |Bits |Field |Descriptions 00070 * | :----: | :----: | :---- | 00071 * |[0] |BUFFULLIF |Buffer Full 00072 * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write) 00073 * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading). 00074 * | | |0 = The endpoint packet buffer is not full. 00075 * | | |1 = The endpoint packet buffer is full. 00076 * | | |Note: This bit is read-only. 00077 * |[1] |BUFEMPTYIF|Buffer Empty 00078 * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes. 00079 * | | |0 = The endpoint buffer is not empty. 00080 * | | |1 = The endpoint buffer is empty. 00081 * | | |For an OUT endpoint: 00082 * | | |0 = The currently selected buffer has not a count of 0. 00083 * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read). 00084 * | | |Note: This bit is read-only. 00085 * |[2] |SHORTTXIF |Short Packet Transferred Interrupt 00086 * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS). 00087 * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS). 00088 * | | |Note: Write 1 to clear this bit to 0. 00089 * |[3] |TXPKIF |Data Packet Transmitted Interrupt 00090 * | | |0 = Not a data packet is transmitted from the endpoint to the host. 00091 * | | |1 = A data packet is transmitted from the endpoint to the host. 00092 * | | |Note: Write 1 to clear this bit to 0. 00093 * |[4] |RXPKIF |Data Packet Received Interrupt 00094 * | | |0 = No data packet is received from the host by the endpoint. 00095 * | | |1 = A data packet is received from the host by the endpoint. 00096 * | | |Note: Write 1 to clear this bit to 0. 00097 * |[5] |OUTTKIF |Data OUT Token Interrupt 00098 * | | |0 = A Data OUT token has not been received from the host. 00099 * | | |1 = A Data OUT token has been received from the host 00100 * | | |This bit also set by PING token (in high-speed only). 00101 * | | |Note: Write 1 to clear this bit to 0. 00102 * |[6] |INTKIF |Data IN Token Interrupt 00103 * | | |0 = Not Data IN token has been received from the host. 00104 * | | |1 = A Data IN token has been received from the host. 00105 * | | |Note: Write 1 to clear this bit to 0. 00106 * |[7] |PINGIF |PING Token Interrupt 00107 * | | |0 = A Data PING token has not been received from the host. 00108 * | | |1 = A Data PING token has been received from the host. 00109 * | | |Note: Write 1 to clear this bit to 0. 00110 * |[8] |NAKIF |USB NAK Sent 00111 * | | |0 = The last USB IN packet could be provided, and was acknowledged with an ACK. 00112 * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK. 00113 * | | |Note: Write 1 to clear this bit to 0. 00114 * |[9] |STALLIF |USB STALL Sent 00115 * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL. 00116 * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL. 00117 * | | |Note: Write 1 to clear this bit to 0. 00118 * |[10] |NYETIF |NYET Sent 00119 * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet. 00120 * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet. 00121 * | | |Note: Write 1 to clear this bit to 0. 00122 * |[11] |ERRIF |ERR Sent 00123 * | | |0 = No any error in the transaction. 00124 * | | |1 = There occurs any error in the transaction. 00125 * | | |Note: Write 1 to clear this bit to 0. 00126 * |[12] |SHORTRXIF |Bulk Out Short Packet Received 00127 * | | |0 = No bulk out short packet is received. 00128 * | | |1 = Received bulk out short packet (including zero length packet). 00129 * | | |Note: Write 1 to clear this bit to 0. 00130 * @var HSUSBD_EP_T::EPINTEN 00131 * Offset: 0x08 Endpoint n Interrupt Enable Register 00132 * --------------------------------------------------------------------------------------------------- 00133 * |Bits |Field |Descriptions 00134 * | :----: | :----: | :---- | 00135 * |[0] |BUFFULLIEN|Buffer Full Interrupt 00136 * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus. 00137 * | | |0 = Buffer full interrupt Disabled. 00138 * | | |1 = Buffer full interrupt Enabled. 00139 * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt 00140 * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus. 00141 * | | |0 = Buffer empty interrupt Disabled. 00142 * | | |1 = Buffer empty interrupt Enabled. 00143 * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Bit 00144 * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host. 00145 * | | |0 = Short data packet interrupt Disabled. 00146 * | | |1 = Short data packet interrupt Enabled. 00147 * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Bit 00148 * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host. 00149 * | | |0 = Data packet has been received from the host interrupt Disabled. 00150 * | | |1 = Data packet has been received from the host interrupt Enabled. 00151 * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Bit 00152 * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host. 00153 * | | |0 = Data packet has been transmitted to the host interrupt Disabled. 00154 * | | |1 = Data packet has been transmitted to the host interrupt Enabled. 00155 * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Bit 00156 * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host. 00157 * | | |0 = Data OUT token interrupt Disabled. 00158 * | | |1 = Data OUT token interrupt Enabled. 00159 * |[6] |INTKIEN |Data IN Token Interrupt Enable Bit 00160 * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host. 00161 * | | |0 = Data IN token interrupt Disabled. 00162 * | | |1 = Data IN token interrupt Enabled. 00163 * |[7] |PINGIEN |PING Token Interrupt Enable Bit 00164 * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host. 00165 * | | |0 = PING token interrupt Disabled. 00166 * | | |1 = PING token interrupt Enabled. 00167 * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Bit 00168 * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host. 00169 * | | |0 = NAK token interrupt Disabled. 00170 * | | |1 = NAK token interrupt Enabled. 00171 * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Bit 00172 * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host. 00173 * | | |0 = STALL token interrupt Disabled. 00174 * | | |1 = STALL token interrupt Enabled. 00175 * |[10] |NYETIEN |NYET Interrupt Enable Bit 00176 * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint. 00177 * | | |0 = NYET condition interrupt Disabled. 00178 * | | |1 = NYET condition interrupt Enabled. 00179 * |[11] |ERRIEN |ERR Interrupt Enable Bit 00180 * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint. 00181 * | | |0 = Error event interrupt Disabled. 00182 * | | |1 = Error event interrupt Enabled. 00183 * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Bit 00184 * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint. 00185 * | | |0 = Bulk out interrupt Disabled. 00186 * | | |1 = Bulk out interrupt Enabled. 00187 * @var HSUSBD_EP_T::EPDATCNT 00188 * Offset: 0x0C Endpoint n Data Available Count Register 00189 * --------------------------------------------------------------------------------------------------- 00190 * |Bits |Field |Descriptions 00191 * | :----: | :----: | :---- | 00192 * |[15:0] |DATCNT |Data Count 00193 * | | |For an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.), this register returns the number of valid bytes in the IN endpoint packet buffer. 00194 * | | |For an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.), this register returns the number of received valid bytes in the Host OUT transfer. 00195 * |[30:16] |DMALOOP |DMA Loop 00196 * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer. 00197 * @var HSUSBD_EP_T::EPRSPCTL 00198 * Offset: 0x10 Endpoint n Response Control Register 00199 * --------------------------------------------------------------------------------------------------- 00200 * |Bits |Field |Descriptions 00201 * | :----: | :----: | :---- | 00202 * |[0] |FLUSH |Buffer Flush 00203 * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared 00204 * | | |This bit is self-clearing 00205 * | | |This bit should always be written after an configuration event. 00206 * | | |0 = The packet buffer is not flushed. 00207 * | | |1 = The packet buffer is flushed by user. 00208 * |[2:1] |MODE |Mode Control 00209 * | | |The two bits decide the operation mode of the in-endpoint. 00210 * | | |00: Auto-Validate Mode 00211 * | | |01: Manual-Validate Mode 00212 * | | |10: Fly Mode 00213 * | | |11: Reserved 00214 * | | |These bits are not valid for an out-endpoint 00215 * | | |The auto validate mode will be activated when the reserved mode is selected 00216 * |[3] |TOGGLE |Endpoint Toggle 00217 * | | |This bit is used to clear the endpoint data toggle bit 00218 * | | |Reading this bit returns the current state of the endpoint data toggle bit. 00219 * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host 00220 * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3]. 00221 * | | |0 = Not clear the endpoint data toggle bit. 00222 * | | |1 = Clear the endpoint data toggle bit. 00223 * |[4] |HALT |Endpoint Halt 00224 * | | |This bit is used to send a STALL handshake as response to the token from the host 00225 * | | |When an Endpoint Set Feature (ep_halt) is detected by the local CPU, it must write a '1' to this bit. 00226 * | | |0 = Not send a STALL handshake as response to the token from the host. 00227 * | | |1 = Send a STALL handshake as response to the token from the host. 00228 * |[5] |ZEROLEN |Zero Length 00229 * | | |This bit is used to send a zero-length packet response to an IN-token 00230 * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token 00231 * | | |This bit gets cleared once the zero length data packet is sent. 00232 * | | |0 = A zero packet is not sent to the host on reception of an IN-token. 00233 * | | |1 = A zero packet is sent to the host on reception of an IN-token. 00234 * |[6] |SHORTTXEN |Short Packet Transfer Enable 00235 * | | |This bit is applicable only in case of Auto-Validate Method 00236 * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer 00237 * | | |This bit gets cleared once the data packet is sent. 00238 * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint. 00239 * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint. 00240 * |[7] |DISBUF |Buffer Disable Bit 00241 * | | |This bit is used to receive unknown size OUT short packet 00242 * | | |The received packet size is reference USBD_EPxDATCNT register. 00243 * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received. 00244 * | | |1 = Buffer Disabled when Bulk-OUT short packet is received. 00245 * @var HSUSBD_EP_T::EPMPS 00246 * Offset: 0x14 Endpoint n Maximum Packet Size Register 00247 * --------------------------------------------------------------------------------------------------- 00248 * |Bits |Field |Descriptions 00249 * | :----: | :----: | :---- | 00250 * |[10:0] |EPMPS |Endpoint Maximum Packet Size 00251 * | | |This field determines the Maximum Packet Size of the Endpoint. 00252 * @var HSUSBD_EP_T::EPTXCNT 00253 * Offset: 0x18 Endpoint n Transfer Count Register 00254 * --------------------------------------------------------------------------------------------------- 00255 * |Bits |Field |Descriptions 00256 * | :----: | :----: | :---- | 00257 * |[10:0] |TXCNT |Endpoint Transfer Count 00258 * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method. 00259 * | | |For OUT endpoints, this field has no effect. 00260 * @var HSUSBD_EP_T::EPCFG 00261 * Offset: 0x1C Endpoint n Configuration Register 00262 * --------------------------------------------------------------------------------------------------- 00263 * |Bits |Field |Descriptions 00264 * | :----: | :----: | :---- | 00265 * |[0] |EPEN |Endpoint Valid 00266 * | | |When set, this bit enables this endpoint 00267 * | | |This bit has no effect on Endpoint 0, which is always enabled. 00268 * | | |0 = The endpoint Disabled. 00269 * | | |1 = The endpoint Enabled. 00270 * |[2:1] |EPTYPE |Endpoint Type 00271 * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type. 00272 * | | |00 = Reserved. 00273 * | | |01 = Bulk. 00274 * | | |10 = Interrupt. 00275 * | | |11 = Isochronous. 00276 * |[3] |EPDIR |Endpoint Direction 00277 * | | |0 = out-endpoint (Host OUT to Device). 00278 * | | |1 = in-endpoint (Host IN to Device). 00279 * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number. 00280 * |[7:4] |EPNUM |Endpoint Number 00281 * | | |This field selects the number of the endpoint. Valid numbers 1 to 15. 00282 * | | |Note: Do not support two endpoints have same endpoint number. 00283 * @var HSUSBD_EP_T::EPBUFST 00284 * Offset: 0x20 Endpoint n RAM Start Address Register 00285 * --------------------------------------------------------------------------------------------------- 00286 * |Bits |Field |Descriptions 00287 * | :----: | :----: | :---- | 00288 * |[11:0] |SADDR |Endpoint Start Address 00289 * | | |This is the start-address of the RAM space allocated for the endpoint A~L. 00290 * @var HSUSBD_EP_T::EPBUFEND 00291 * Offset: 0x24 Endpoint n RAM End Address Register 00292 * --------------------------------------------------------------------------------------------------- 00293 * |Bits |Field |Descriptions 00294 * | :----: | :----: | :---- | 00295 * |[11:0] |EADDR |Endpoint End Address 00296 * | | |This is the end-address of the RAM space allocated for the endpoint A~L. 00297 */ 00298 00299 union { 00300 __IO uint32_t EPDAT; 00301 __IO uint8_t EPDAT_BYTE; 00302 00303 }; /*!< [0x0000] Endpoint n Data Register */ 00304 00305 __IO uint32_t EPINTSTS; /*!< [0x0004] Endpoint n Interrupt Status Register */ 00306 __IO uint32_t EPINTEN; /*!< [0x0008] Endpoint n Interrupt Enable Register */ 00307 __I uint32_t EPDATCNT; /*!< [0x000c] Endpoint n Data Available Count Register */ 00308 __IO uint32_t EPRSPCTL; /*!< [0x0010] Endpoint n Response Control Register */ 00309 __IO uint32_t EPMPS; /*!< [0x0014] Endpoint n Maximum Packet Size Register */ 00310 __IO uint32_t EPTXCNT; /*!< [0x0018] Endpoint n Transfer Count Register */ 00311 __IO uint32_t EPCFG; /*!< [0x001c] Endpoint n Configuration Register */ 00312 __IO uint32_t EPBUFST; /*!< [0x0020] Endpoint n RAM Start Address Register */ 00313 __IO uint32_t EPBUFEND; /*!< [0x0024] Endpoint n RAM End Address Register */ 00314 00315 } HSUSBD_EP_T; 00316 00317 typedef struct { 00318 00319 /** 00320 * @var HSUSBD_T::GINTSTS 00321 * Offset: 0x00 Global Interrupt Status Register 00322 * --------------------------------------------------------------------------------------------------- 00323 * |Bits |Field |Descriptions 00324 * | :----: | :----: | :---- | 00325 * |[0] |USBIF |USB Interrupt 00326 * | | |This bit conveys the interrupt status for USB specific events endpoint 00327 * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt. 00328 * | | |0 = No interrupt event occurred. 00329 * | | |1 = The related interrupt event is occurred. 00330 * |[1] |CEPIF |Control Endpoint Interrupt 00331 * | | |This bit conveys the interrupt status for control endpoint 00332 * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt. 00333 * | | |0 = No interrupt event occurred. 00334 * | | |1 = The related interrupt event is occurred. 00335 * |[2] |EPAIF |Endpoint a Interrupt 00336 * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt. 00337 * | | |0 = No interrupt event occurred. 00338 * | | |1 = The related interrupt event is occurred. 00339 * |[3] |EPBIF |Endpoint B Interrupt 00340 * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt. 00341 * | | |0 = No interrupt event occurred. 00342 * | | |1 = The related interrupt event is occurred. 00343 * |[4] |EPCIF |Endpoint C Interrupt 00344 * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt. 00345 * | | |0 = No interrupt event occurred. 00346 * | | |1 = The related interrupt event is occurred. 00347 * |[5] |EPDIF |Endpoint D Interrupt 00348 * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt. 00349 * | | |0 = No interrupt event occurred. 00350 * | | |1 = The related interrupt event is occurred. 00351 * |[6] |EPEIF |Endpoint E Interrupt 00352 * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt. 00353 * | | |0 = No interrupt event occurred. 00354 * | | |1 = The related interrupt event is occurred. 00355 * |[7] |EPFIF |Endpoint F Interrupt 00356 * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt. 00357 * | | |0 = No interrupt event occurred. 00358 * | | |1 = The related interrupt event is occurred. 00359 * |[8] |EPGIF |Endpoint G Interrupt 00360 * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt. 00361 * | | |0 = No interrupt event occurred. 00362 * | | |1 = The related interrupt event is occurred. 00363 * |[9] |EPHIF |Endpoint H Interrupt 00364 * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt. 00365 * | | |0 = No interrupt event occurred. 00366 * | | |1 = The related interrupt event is occurred. 00367 * |[10] |EPIIF |Endpoint I Interrupt 00368 * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt. 00369 * | | |0 = No interrupt event occurred. 00370 * | | |1 = The related interrupt event is occurred. 00371 * |[11] |EPJIF |Endpoint J Interrupt 00372 * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt. 00373 * | | |0 = No interrupt event occurred. 00374 * | | |1 = The related interrupt event is occurred. 00375 * |[12] |EPKIF |Endpoint K Interrupt 00376 * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt. 00377 * | | |0 = No interrupt event occurred. 00378 * | | |1 = The related interrupt event is occurred. 00379 * |[13] |EPLIF |Endpoint L Interrupt 00380 * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt. 00381 * | | |0 = No interrupt event occurred. 00382 * | | |1 = The related interrupt event is occurred. 00383 * @var HSUSBD_T::GINTEN 00384 * Offset: 0x08 Global Interrupt Enable Register 00385 * --------------------------------------------------------------------------------------------------- 00386 * |Bits |Field |Descriptions 00387 * | :----: | :----: | :---- | 00388 * |[0] |USBIEN |USB Interrupt Enable Bit 00389 * | | |When set, this bit enables a local interrupt to be generated when a USB event occurs on the bus. 00390 * | | |0 = The related interrupt Disabled. 00391 * | | |1 = The related interrupt Enabled. 00392 * |[1] |CEPIEN |Control Endpoint Interrupt Enable Bit 00393 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint. 00394 * | | |0 = The related interrupt Disabled. 00395 * | | |1 = The related interrupt Enabled. 00396 * |[2] |EPAIEN |Interrupt Enable Control for Endpoint a 00397 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A. 00398 * | | |0 = The related interrupt Disabled. 00399 * | | |1 = The related interrupt Enabled. 00400 * |[3] |EPBIEN |Interrupt Enable Control for Endpoint B 00401 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B 00402 * | | |0 = The related interrupt Disabled. 00403 * | | |1 = The related interrupt Enabled. 00404 * |[4] |EPCIEN |Interrupt Enable Control for Endpoint C 00405 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C 00406 * | | |0 = The related interrupt Disabled. 00407 * | | |1 = The related interrupt Enabled. 00408 * |[5] |EPDIEN |Interrupt Enable Control for Endpoint D 00409 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D 00410 * | | |0 = The related interrupt Disabled. 00411 * | | |1 = The related interrupt Enabled. 00412 * |[6] |EPEIEN |Interrupt Enable Control for Endpoint E 00413 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E 00414 * | | |0 = The related interrupt Disabled. 00415 * | | |1 = The related interrupt Enabled. 00416 * |[7] |EPFIEN |Interrupt Enable Control for Endpoint F 00417 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F 00418 * | | |0 = The related interrupt Disabled. 00419 * | | |1 = The related interrupt Enabled. 00420 * |[8] |EPGIEN |Interrupt Enable Control for Endpoint G 00421 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G 00422 * | | |0 = The related interrupt Disabled. 00423 * | | |1 = The related interrupt Enabled. 00424 * |[9] |EPHIEN |Interrupt Enable Control for Endpoint H 00425 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H 00426 * | | |0 = The related interrupt Disabled. 00427 * | | |1 = The related interrupt Enabled. 00428 * |[10] |EPIIEN |Interrupt Enable Control for Endpoint I 00429 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I 00430 * | | |0 = The related interrupt Disabled. 00431 * | | |1 = The related interrupt Enabled. 00432 * |[11] |EPJIEN |Interrupt Enable Control for Endpoint J 00433 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J 00434 * | | |0 = The related interrupt Disabled. 00435 * | | |1 = The related interrupt Enabled. 00436 * |[12] |EPKIEN |Interrupt Enable Control for Endpoint K 00437 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K 00438 * | | |0 = The related interrupt Disabled. 00439 * | | |1 = The related interrupt Enabled. 00440 * |[13] |EPLIEN |Interrupt Enable Control for Endpoint L 00441 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L 00442 * | | |0 = The related interrupt Disabled. 00443 * | | |1 = The related interrupt Enabled. 00444 * @var HSUSBD_T::BUSINTSTS 00445 * Offset: 0x10 USB Bus Interrupt Status Register 00446 * --------------------------------------------------------------------------------------------------- 00447 * |Bits |Field |Descriptions 00448 * | :----: | :----: | :---- | 00449 * |[0] |SOFIF |SOF Receive Control 00450 * | | |This bit indicates when a start-of-frame packet has been received. 00451 * | | |0 = No start-of-frame packet has been received. 00452 * | | |1 = Start-of-frame packet has been received. 00453 * | | |Note: Write 1 to clear this bit to 0. 00454 * |[1] |RSTIF |Reset Status 00455 * | | |When set, this bit indicates that either the USB root port reset is end. 00456 * | | |0 = No USB root port reset is end. 00457 * | | |1 = USB root port reset is end. 00458 * | | |Note: Write 1 to clear this bit to 0. 00459 * |[2] |RESUMEIF |Resume 00460 * | | |When set, this bit indicates that a device resume has occurred. 00461 * | | |0 = No device resume has occurred. 00462 * | | |1 = Device resume has occurred. 00463 * | | |Note: Write 1 to clear this bit to 0. 00464 * |[3] |SUSPENDIF |Suspend Request 00465 * | | |This bit is set as default and it has to be cleared by writing '1' before the USB reset 00466 * | | |This bit is also set when a USB Suspend request is detected from the host. 00467 * | | |0 = No USB Suspend request is detected from the host. 00468 * | | |1= USB Suspend request is detected from the host. 00469 * | | |Note: Write 1 to clear this bit to 0. 00470 * |[4] |HISPDIF |High-speed Settle 00471 * | | |0 = No valid high-speed reset protocol is detected. 00472 * | | |1 = Valid high-speed reset protocol is over and the device has settled in high-speed. 00473 * | | |Note: Write 1 to clear this bit to 0. 00474 * |[5] |DMADONEIF |DMA Completion Interrupt 00475 * | | |0 = No DMA transfer over. 00476 * | | |1 = DMA transfer is over. 00477 * | | |Note: Write 1 to clear this bit to 0. 00478 * |[6] |PHYCLKVLDIF|Usable Clock Interrupt 00479 * | | |0 = Usable clock is not available. 00480 * | | |1 = Usable clock is available from the transceiver. 00481 * | | |Note: Write 1 to clear this bit to 0. 00482 * |[8] |VBUSDETIF |VBUS Detection Interrupt Status 00483 * | | |0 = No VBUS is plug-in. 00484 * | | |1 = VBUS is plug-in. 00485 * | | |Note: Write 1 to clear this bit to 0. 00486 * @var HSUSBD_T::BUSINTEN 00487 * Offset: 0x14 USB Bus Interrupt Enable Register 00488 * --------------------------------------------------------------------------------------------------- 00489 * |Bits |Field |Descriptions 00490 * | :----: | :----: | :---- | 00491 * |[0] |SOFIEN |SOF Interrupt 00492 * | | |This bit enables the SOF interrupt. 00493 * | | |0 = SOF interrupt Disabled. 00494 * | | |1 = SOF interrupt Enabled. 00495 * |[1] |RSTIEN |Reset Status 00496 * | | |This bit enables the USB-Reset interrupt. 00497 * | | |0 = USB-Reset interrupt Disabled. 00498 * | | |1 = USB-Reset interrupt Enabled. 00499 * |[2] |RESUMEIEN |Resume 00500 * | | |This bit enables the Resume interrupt. 00501 * | | |0 = Resume interrupt Disabled. 00502 * | | |1 = Resume interrupt Enabled. 00503 * |[3] |SUSPENDIEN|Suspend Request 00504 * | | |This bit enables the Suspend interrupt. 00505 * | | |0 = Suspend interrupt Disabled. 00506 * | | |1 = Suspend interrupt Enabled. 00507 * |[4] |HISPDIEN |High-speed Settle 00508 * | | |This bit enables the high-speed settle interrupt. 00509 * | | |0 = High-speed settle interrupt Disabled. 00510 * | | |1 = High-speed settle interrupt Enabled. 00511 * |[5] |DMADONEIEN|DMA Completion Interrupt 00512 * | | |This bit enables the DMA completion interrupt 00513 * | | |0 = DMA completion interrupt Disabled. 00514 * | | |1 = DMA completion interrupt Enabled. 00515 * |[6] |PHYCLKVLDIEN|Usable Clock Interrupt 00516 * | | |This bit enables the usable clock interrupt. 00517 * | | |0 = Usable clock interrupt Disabled. 00518 * | | |1 = Usable clock interrupt Enabled. 00519 * |[8] |VBUSDETIEN|VBUS Detection Interrupt Enable Bit 00520 * | | |This bit enables the VBUS floating detection interrupt. 00521 * | | |0 = VBUS floating detection interrupt Disabled. 00522 * | | |1 = VBUS floating detection interrupt Enabled. 00523 * @var HSUSBD_T::OPER 00524 * Offset: 0x18 USB Operational Register 00525 * --------------------------------------------------------------------------------------------------- 00526 * |Bits |Field |Descriptions 00527 * | :----: | :----: | :---- | 00528 * |[0] |RESUMEEN |Generate Resume 00529 * | | |0 = No Resume sequence to be initiated to the host. 00530 * | | |1 = A Resume sequence to be initiated to the host if device remote wakeup is enabled 00531 * | | |This bit is self-clearing. 00532 * |[1] |HISPDEN |USB High-speed 00533 * | | |0 = The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host. 00534 * | | |1 = The USB device controller to initiate a chirp-sequence during reset protocol. 00535 * |[2] |CURSPD |USB Current Speed 00536 * | | |0 = The device has settled in Full Speed. 00537 * | | |1 = The USB device controller has settled in High-speed. 00538 * @var HSUSBD_T::FRAMECNT 00539 * Offset: 0x1C USB Frame Count Register 00540 * --------------------------------------------------------------------------------------------------- 00541 * |Bits |Field |Descriptions 00542 * | :----: | :----: | :---- | 00543 * |[2:0] |MFRAMECNT |Micro-frame Counter 00544 * | | |This field contains the micro-frame number for the frame number in the frame counter field. 00545 * |[13:3] |FRAMECNT |Frame Counter 00546 * | | |This field contains the frame count from the most recent start-of-frame packet. 00547 * @var HSUSBD_T::FADDR 00548 * Offset: 0x20 USB Function Address Register 00549 * --------------------------------------------------------------------------------------------------- 00550 * |Bits |Field |Descriptions 00551 * | :----: | :----: | :---- | 00552 * |[6:0] |FADDR |USB Function Address 00553 * | | |This field contains the current USB address of the device 00554 * | | |This field is cleared when a root port reset is detected 00555 * @var HSUSBD_T::TEST 00556 * Offset: 0x24 USB Test Mode Register 00557 * --------------------------------------------------------------------------------------------------- 00558 * |Bits |Field |Descriptions 00559 * | :----: | :----: | :---- | 00560 * |[2:0] |TESTMODE |Test Mode Selection 00561 * | | |000 = Normal Operation. 00562 * | | |001 = Test_J. 00563 * | | |010 = Test_K. 00564 * | | |011 = Test_SE0_NAK. 00565 * | | |100 = Test_Packet. 00566 * | | |101 = Test_Force_Enable. 00567 * | | |110 = Reserved. 00568 * | | |111 = Reserved. 00569 * | | |Note: This field is cleared when root port reset is detected. 00570 * @var HSUSBD_T::CEPDAT 00571 * Offset: 0x28 Control-Endpoint Data Buffer 00572 * --------------------------------------------------------------------------------------------------- 00573 * |Bits |Field |Descriptions 00574 * | :----: | :----: | :---- | 00575 * |[31:0] |DAT |Control-endpoint Data Buffer 00576 * | | |Control endpoint data buffer for the buffer transaction (read or write). 00577 * | | |Note: Only word access is supported. 00578 * @var HSUSBD_T::CEPDAT_BYTE 00579 * Offset: 0x28 Control-Endpoint Data Buffer 00580 * --------------------------------------------------------------------------------------------------- 00581 * |Bits |Field |Descriptions 00582 * | :----: | :----: | :---- | 00583 * |[7:0] |DAT |Control-endpoint Data Buffer 00584 * | | |Control endpoint data buffer for the buffer transaction (read or write). 00585 * | | |Note: Only byte access is supported. 00586 * @var HSUSBD_T::CEPCTL 00587 * Offset: 0x2C Control-Endpoint Control Register 00588 * --------------------------------------------------------------------------------------------------- 00589 * |Bits |Field |Descriptions 00590 * | :----: | :----: | :---- | 00591 * |[0] |NAKCLR |No Acknowledge Control 00592 * | | |This bit plays a crucial role in any control transfer. 00593 * | | |0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase 00594 * | | |This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request. 00595 * | | |1 = This bit is set to one by the USB device controller, whenever a setup token is received 00596 * | | |The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit. 00597 * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated. 00598 * |[1] |STALLEN |Stall Enable Bit 00599 * | | |When this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter 00600 * | | |This is typically used for response to invalid/unsupported requests 00601 * | | |When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL 00602 * | | |It is automatically cleared on receipt of a next setup-token 00603 * | | |So, the local CPU need not write again to clear this bit. 00604 * | | |0 = No sends a stall handshake in response to any in or out token thereafter. 00605 * | | |1 = The control endpoint sends a stall handshake in response to any in or out token thereafter. 00606 * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated. 00607 * |[2] |ZEROLEN |Zero Packet Length 00608 * | | |This bit is valid for Auto Validation mode only. 00609 * | | |0 = No zero length packet to the host during Data stage to an IN token. 00610 * | | |1 = USB device controller can send a zero length packet to the host during Data stage to an IN token 00611 * | | |This bit gets cleared once the zero length data packet is sent 00612 * | | |So, the local CPU need not write again to clear this bit. 00613 * |[3] |FLUSH |CEP-flush Bit 00614 * | | |0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared. 00615 * | | |1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared 00616 * | | |This bit is self-cleaning. 00617 * @var HSUSBD_T::CEPINTEN 00618 * Offset: 0x30 Control-Endpoint Interrupt Enable 00619 * --------------------------------------------------------------------------------------------------- 00620 * |Bits |Field |Descriptions 00621 * | :----: | :----: | :---- | 00622 * |[0] |SETUPTKIEN|Setup Token Interrupt Enable Bit 00623 * | | |0 = The SETUP token interrupt in Control Endpoint Disabled. 00624 * | | |1 = The SETUP token interrupt in Control Endpoint Enabled. 00625 * |[1] |SETUPPKIEN|Setup Packet Interrupt 00626 * | | |0 = The SETUP packet interrupt in Control Endpoint Disabled. 00627 * | | |1 = The SETUP packet interrupt in Control Endpoint Enabled. 00628 * |[2] |OUTTKIEN |Out Token Interrupt 00629 * | | |0 = The OUT token interrupt in Control Endpoint Disabled. 00630 * | | |1 = The OUT token interrupt in Control Endpoint Enabled. 00631 * |[3] |INTKIEN |In Token Interrupt 00632 * | | |0 = The IN token interrupt in Control Endpoint Disabled. 00633 * | | |1 = The IN token interrupt in Control Endpoint Enabled. 00634 * |[4] |PINGIEN |Ping Token Interrupt 00635 * | | |0 = The ping token interrupt in Control Endpoint Disabled. 00636 * | | |1 = The ping token interrupt Control Endpoint Enabled. 00637 * |[5] |TXPKIEN |Data Packet Transmitted Interrupt 00638 * | | |0 = The data packet transmitted interrupt in Control Endpoint Disabled. 00639 * | | |1 = The data packet transmitted interrupt in Control Endpoint Enabled. 00640 * |[6] |RXPKIEN |Data Packet Received Interrupt 00641 * | | |0 = The data received interrupt in Control Endpoint Disabled. 00642 * | | |1 = The data received interrupt in Control Endpoint Enabled. 00643 * |[7] |NAKIEN |NAK Sent Interrupt 00644 * | | |0 = The NAK sent interrupt in Control Endpoint Disabled. 00645 * | | |1 = The NAK sent interrupt in Control Endpoint Enabled. 00646 * |[8] |STALLIEN |STALL Sent Interrupt 00647 * | | |0 = The STALL sent interrupt in Control Endpoint Disabled. 00648 * | | |1 = The STALL sent interrupt in Control Endpoint Enabled. 00649 * |[9] |ERRIEN |USB Error Interrupt 00650 * | | |0 = The USB Error interrupt in Control Endpoint Disabled. 00651 * | | |1 = The USB Error interrupt in Control Endpoint Enabled. 00652 * |[10] |STSDONEIEN|Status Completion Interrupt 00653 * | | |0 = The Status Completion interrupt in Control Endpoint Disabled. 00654 * | | |1 = The Status Completion interrupt in Control Endpoint Enabled. 00655 * |[11] |BUFFULLIEN|Buffer Full Interrupt 00656 * | | |0 = The buffer full interrupt in Control Endpoint Disabled. 00657 * | | |1 = The buffer full interrupt in Control Endpoint Enabled. 00658 * |[12] |BUFEMPTYIEN|Buffer Empty Interrupt 00659 * | | |0 = The buffer empty interrupt in Control Endpoint Disabled. 00660 * | | |1= The buffer empty interrupt in Control Endpoint Enabled. 00661 * @var HSUSBD_T::CEPINTSTS 00662 * Offset: 0x34 Control-Endpoint Interrupt Status 00663 * --------------------------------------------------------------------------------------------------- 00664 * |Bits |Field |Descriptions 00665 * | :----: | :----: | :---- | 00666 * |[0] |SETUPTKIF |Setup Token Interrupt 00667 * | | |0 = Not a Setup token is received. 00668 * | | |1 = A Setup token is received. Writing 1 clears this status bit 00669 * | | |Note: Write 1 to clear this bit to 0. 00670 * |[1] |SETUPPKIF |Setup Packet Interrupt 00671 * | | |This bit must be cleared (by writing 1) before the next setup packet can be received 00672 * | | |If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer. 00673 * | | |0 = Not a Setup packet has been received from the host. 00674 * | | |1 = A Setup packet has been received from the host. 00675 * | | |Note: Write 1 to clear this bit to 0. 00676 * |[2] |OUTTKIF |Out Token Interrupt 00677 * | | |0 = The control-endpoint does not received an OUT token from the host. 00678 * | | |1 = The control-endpoint receives an OUT token from the host. 00679 * | | |Note: Write 1 to clear this bit to 0. 00680 * |[3] |INTKIF |in Token Interrupt 00681 * | | |0 = The control-endpoint does not received an IN token from the host. 00682 * | | |1 = The control-endpoint receives an IN token from the host. 00683 * | | |Note: Write 1 to clear this bit to 0. 00684 * |[4] |PINGIF |Ping Token Interrupt 00685 * | | |0 = The control-endpoint does not received a ping token from the host. 00686 * | | |1 = The control-endpoint receives a ping token from the host. 00687 * | | |Note: Write 1 to clear this bit to 0. 00688 * |[5] |TXPKIF |Data Packet Transmitted Interrupt 00689 * | | |0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. 00690 * | | |1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. 00691 * | | |Note: Write 1 to clear this bit to 0. 00692 * |[6] |RXPKIF |Data Packet Received Interrupt 00693 * | | |0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. 00694 * | | |1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. 00695 * | | |Note: Write 1 to clear this bit to 0. 00696 * |[7] |NAKIF |NAK Sent Interrupt 00697 * | | |0 = Not a NAK-token is sent in response to an IN/OUT token. 00698 * | | |1 = A NAK-token is sent in response to an IN/OUT token. 00699 * | | |Note: Write 1 to clear this bit to 0. 00700 * |[8] |STALLIF |STALL Sent Interrupt 00701 * | | |0 = Not a stall-token is sent in response to an IN/OUT token. 00702 * | | |1 = A stall-token is sent in response to an IN/OUT token. 00703 * | | |Note: Write 1 to clear this bit to 0. 00704 * |[9] |ERRIF |USB Error Interrupt 00705 * | | |0 = No error had occurred during the transaction. 00706 * | | |1 = An error had occurred during the transaction. 00707 * | | |Note: Write 1 to clear this bit to 0. 00708 * |[10] |STSDONEIF |Status Completion Interrupt 00709 * | | |0 = Not a USB transaction has completed successfully. 00710 * | | |1 = The status stage of a USB transaction has completed successfully. 00711 * | | |Note: Write 1 to clear this bit to 0. 00712 * |[11] |BUFFULLIF |Buffer Full Interrupt 00713 * | | |0 = The control-endpoint buffer is not full. 00714 * | | |1 = The control-endpoint buffer is full. 00715 * | | |Note: Write 1 to clear this bit to 0. 00716 * |[12] |BUFEMPTYIF|Buffer Empty Interrupt 00717 * | | |0 = The control-endpoint buffer is not empty. 00718 * | | |1 = The control-endpoint buffer is empty. 00719 * | | |Note: Write 1 to clear this bit to 0. 00720 * @var HSUSBD_T::CEPTXCNT 00721 * Offset: 0x38 Control-Endpoint In-transfer Data Count 00722 * --------------------------------------------------------------------------------------------------- 00723 * |Bits |Field |Descriptions 00724 * | :----: | :----: | :---- | 00725 * |[7:0] |TXCNT |In-transfer Data Count 00726 * | | |There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register 00727 * | | |When zero is written into this field, a zero length packet is sent to the host 00728 * | | |When the count written in the register is more than the MPS, the data sent will be of only MPS. 00729 * @var HSUSBD_T::CEPRXCNT 00730 * Offset: 0x3C Control-Endpoint Out-transfer Data Count 00731 * --------------------------------------------------------------------------------------------------- 00732 * |Bits |Field |Descriptions 00733 * | :----: | :----: | :---- | 00734 * |[7:0] |RXCNT |Out-transfer Data Count 00735 * | | |The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer. 00736 * @var HSUSBD_T::CEPDATCNT 00737 * Offset: 0x40 Control-Endpoint data count 00738 * --------------------------------------------------------------------------------------------------- 00739 * |Bits |Field |Descriptions 00740 * | :----: | :----: | :---- | 00741 * |[15:0] |DATCNT |Control-endpoint Data Count 00742 * | | |The USB device controller maintains the count of the data of control-endpoint. 00743 * @var HSUSBD_T::SETUP1_0 00744 * Offset: 0x44 Setup1 & Setup0 bytes 00745 * --------------------------------------------------------------------------------------------------- 00746 * |Bits |Field |Descriptions 00747 * | :----: | :----: | :---- | 00748 * |[7:0] |SETUP0 |Setup Byte 0[7:0] 00749 * | | |This register provides byte 0 of the last setup packet received 00750 * | | |For a Standard Device Request, the following bmRequestType information is returned. 00751 * | | |Bit 7(Direction): 00752 * | | | 0: Host to device 00753 * | | | 1: Device to host 00754 * | | |Bit 6-5 (Type): 00755 * | | | 00: Standard 00756 * | | | 01: Class 00757 * | | | 10: Vendor 00758 * | | | 11: Reserved 00759 * | | |Bit 4-0 (Recipient) 00760 * | | | 00000: Device 00761 * | | | 00001: Interface 00762 * | | | 00010: Endpoint 00763 * | | | 00011: Other 00764 * | | | Others: Reserved 00765 * |[15:8] |SETUP1 |Setup Byte 1[15:8] 00766 * | | |This register provides byte 1 of the last setup packet received 00767 * | | |For a Standard Device Request, the following bRequest Code information is returned. 00768 * | | |00000000 = Get Status. 00769 * | | |00000001 = Clear Feature. 00770 * | | |00000010 = Reserved. 00771 * | | |00000011 = Set Feature. 00772 * | | |00000100 = Reserved. 00773 * | | |00000101 = Set Address. 00774 * | | |00000110 = Get Descriptor. 00775 * | | |00000111 = Set Descriptor. 00776 * | | |00001000 = Get Configuration. 00777 * | | |00001001 = Set Configuration. 00778 * | | |00001010 = Get Interface. 00779 * | | |00001011 = Set Interface. 00780 * | | |00001100 = Sync Frame. 00781 * @var HSUSBD_T::SETUP3_2 00782 * Offset: 0x48 Setup3 & Setup2 Bytes 00783 * --------------------------------------------------------------------------------------------------- 00784 * |Bits |Field |Descriptions 00785 * | :----: | :----: | :---- | 00786 * |[7:0] |SETUP2 |Setup Byte 2 [7:0] 00787 * | | |This register provides byte 2 of the last setup packet received 00788 * | | |For a Standard Device Request, the least significant byte of the wValue field is returned 00789 * |[15:8] |SETUP3 |Setup Byte 3 [15:8] 00790 * | | |This register provides byte 3 of the last setup packet received 00791 * | | |For a Standard Device Request, the most significant byte of the wValue field is returned. 00792 * @var HSUSBD_T::SETUP5_4 00793 * Offset: 0x4C Setup5 & Setup4 Bytes 00794 * --------------------------------------------------------------------------------------------------- 00795 * |Bits |Field |Descriptions 00796 * | :----: | :----: | :---- | 00797 * |[7:0] |SETUP4 |Setup Byte 4[7:0] 00798 * | | |This register provides byte 4 of the last setup packet received 00799 * | | |For a Standard Device Request, the least significant byte of the wIndex is returned. 00800 * |[15:8] |SETUP5 |Setup Byte 5[15:8] 00801 * | | |This register provides byte 5 of the last setup packet received 00802 * | | |For a Standard Device Request, the most significant byte of the wIndex field is returned. 00803 * @var HSUSBD_T::SETUP7_6 00804 * Offset: 0x50 Setup7 & Setup6 Bytes 00805 * --------------------------------------------------------------------------------------------------- 00806 * |Bits |Field |Descriptions 00807 * | :----: | :----: | :---- | 00808 * |[7:0] |SETUP6 |Setup Byte 6[7:0] 00809 * | | |This register provides byte 6 of the last setup packet received 00810 * | | |For a Standard Device Request, the least significant byte of the wLength field is returned. 00811 * |[15:8] |SETUP7 |Setup Byte 7[15:8] 00812 * | | |This register provides byte 7 of the last setup packet received 00813 * | | |For a Standard Device Request, the most significant byte of the wLength field is returned. 00814 * @var HSUSBD_T::CEPBUFST 00815 * Offset: 0x54 Control Endpoint RAM Start Address Register 00816 * --------------------------------------------------------------------------------------------------- 00817 * |Bits |Field |Descriptions 00818 * | :----: | :----: | :---- | 00819 * |[11:0] |SADDR |Control-endpoint Start Address 00820 * | | |This is the start-address of the RAM space allocated for the control-endpoint. 00821 * @var HSUSBD_T::CEPBUFEND 00822 * Offset: 0x58 Control Endpoint RAM End Address Register 00823 * --------------------------------------------------------------------------------------------------- 00824 * |Bits |Field |Descriptions 00825 * | :----: | :----: | :---- | 00826 * |[11:0] |EADDR |Control-endpoint End Address 00827 * | | |This is the end-address of the RAM space allocated for the control-endpoint. 00828 * @var HSUSBD_T::DMACTL 00829 * Offset: 0x5C DMA Control Status Register 00830 * --------------------------------------------------------------------------------------------------- 00831 * |Bits |Field |Descriptions 00832 * | :----: | :----: | :---- | 00833 * |[3:0] |EPNUM |DMA Endpoint Address Bits 00834 * | | |Used to define the Endpoint Address 00835 * |[4] |DMARD |DMA Operation 00836 * | | |0 : The operation is a DMA write (read from USB buffer) 00837 * | | |DMA will check endpoint data available count (USBD_EPxDATCNT) according to EPNM setting before to perform DMA write operation. 00838 * | | |1 : The operation is a DMA read (write to USB buffer). 00839 * |[5] |DMAEN |DMA Enable Bit 00840 * | | |0 : DMA function Disabled. 00841 * | | |1 : DMA function Enabled. 00842 * |[6] |SGEN |Scatter Gather Function Enable Bit 00843 * | | |0 : Scatter gather function Disabled. 00844 * | | |1 : Scatter gather function Enabled. 00845 * |[7] |DMARST |Reset DMA State Machine 00846 * | | |0 : No reset the DMA state machine. 00847 * | | |1 : Reset the DMA state machine. 00848 * |[8] |SVINEP |Serve IN Endpoint 00849 * | | |This bit is used to specify DMA serving endpoint-IN endpoint or OUT endpoint. 00850 * | | |0: DMA serves OUT endpoint 00851 * | | |1: DMA serves IN endpoint 00852 * @var HSUSBD_T::DMACNT 00853 * Offset: 0x60 DMA Count Register 00854 * --------------------------------------------------------------------------------------------------- 00855 * |Bits |Field |Descriptions 00856 * | :----: | :----: | :---- | 00857 * |[19:0] |DMACNT |DMA Transfer Count 00858 * | | |The transfer count of the DMA operation to be performed is written to this register. 00859 * @var HSUSBD_T::DMAADDR 00860 * Offset: 0x700 AHB DMA Address Register 00861 * --------------------------------------------------------------------------------------------------- 00862 * |Bits |Field |Descriptions 00863 * | :----: | :----: | :---- | 00864 * |[31:0] |DMAADDR |DMAADDR 00865 * | | |The register specifies the address from which the DMA has to read / write 00866 * | | |The address must WORD (32-bit) aligned. 00867 * @var HSUSBD_T::PHYCTL 00868 * Offset: 0x704 USB PHY Control Register 00869 * --------------------------------------------------------------------------------------------------- 00870 * |Bits |Field |Descriptions 00871 * | :----: | :----: | :---- | 00872 * |[8] |DPPUEN |DP Pull-up 00873 * | | |0 = Pull-up resistor on D+ Disabled. 00874 * | | |1 = Pull-up resistor on D+ Enabled. 00875 * |[9] |PHYEN |PHY Suspend Enable Bit 00876 * | | |0 = The USB PHY is suspend. 00877 * | | |1 = The USB PHY is not suspend. 00878 * |[24] |WKEN |Wake-up Enable Bit 00879 * | | |0 = The wake-up function Disabled. 00880 * | | |1 = The wake-up function Enabled. 00881 * |[31] |VBUSDET |VBUS Status 00882 * | | |0 = The VBUS is not detected yet. 00883 * | | |1 = The VBUS is detected. 00884 */ 00885 00886 __I uint32_t GINTSTS; /*!< [0x0000] Global Interrupt Status Register */ 00887 /// @cond HIDDEN_SYMBOLS 00888 __I uint32_t RESERVE0[1]; 00889 /// @endcond //HIDDEN_SYMBOLS 00890 __IO uint32_t GINTEN; /*!< [0x0008] Global Interrupt Enable Register */ 00891 /// @cond HIDDEN_SYMBOLS 00892 __I uint32_t RESERVE1[1]; 00893 /// @endcond //HIDDEN_SYMBOLS 00894 __IO uint32_t BUSINTSTS; /*!< [0x0010] USB Bus Interrupt Status Register */ 00895 __IO uint32_t BUSINTEN; /*!< [0x0014] USB Bus Interrupt Enable Register */ 00896 __IO uint32_t OPER; /*!< [0x0018] USB Operational Register */ 00897 __I uint32_t FRAMECNT; /*!< [0x001c] USB Frame Count Register */ 00898 __IO uint32_t FADDR; /*!< [0x0020] USB Function Address Register */ 00899 __IO uint32_t TEST; /*!< [0x0024] USB Test Mode Register */ 00900 00901 union { 00902 __IO uint32_t CEPDAT; 00903 __IO uint8_t CEPDAT_BYTE; 00904 00905 }; /*!< [0x0028] Control-Endpoint Data Buffer */ 00906 00907 __IO uint32_t CEPCTL; /*!< [0x002c] Control-Endpoint Control Register */ 00908 __IO uint32_t CEPINTEN; /*!< [0x0030] Control-Endpoint Interrupt Enable */ 00909 __IO uint32_t CEPINTSTS; /*!< [0x0034] Control-Endpoint Interrupt Status */ 00910 __IO uint32_t CEPTXCNT; /*!< [0x0038] Control-Endpoint In-transfer Data Count */ 00911 __I uint32_t CEPRXCNT; /*!< [0x003c] Control-Endpoint Out-transfer Data Count */ 00912 __I uint32_t CEPDATCNT; /*!< [0x0040] Control-Endpoint data count */ 00913 __I uint32_t SETUP1_0; /*!< [0x0044] Setup1 & Setup0 bytes */ 00914 __I uint32_t SETUP3_2; /*!< [0x0048] Setup3 & Setup2 Bytes */ 00915 __I uint32_t SETUP5_4; /*!< [0x004c] Setup5 & Setup4 Bytes */ 00916 __I uint32_t SETUP7_6; /*!< [0x0050] Setup7 & Setup6 Bytes */ 00917 __IO uint32_t CEPBUFST; /*!< [0x0054] Control Endpoint RAM Start Address Register */ 00918 __IO uint32_t CEPBUFEND; /*!< [0x0058] Control Endpoint RAM End Address Register */ 00919 __IO uint32_t DMACTL; /*!< [0x005c] DMA Control Status Register */ 00920 __IO uint32_t DMACNT; /*!< [0x0060] DMA Count Register */ 00921 00922 HSUSBD_EP_T EP[12]; 00923 00924 /// @cond HIDDEN_SYMBOLS 00925 __I uint32_t RESERVE2[303]; 00926 /// @endcond //HIDDEN_SYMBOLS 00927 __IO uint32_t DMAADDR; /*!< [0x0700] AHB DMA Address Register */ 00928 __IO uint32_t PHYCTL; /*!< [0x0704] USB PHY Control Register */ 00929 00930 } HSUSBD_T; 00931 00932 /** 00933 @addtogroup HSUSBD_CONST HSUSBD Bit Field Definition 00934 Constant Definitions for HSUSBD Controller 00935 @{ */ 00936 00937 #define HSUSBD_GINTSTS_USBIF_Pos (0) /*!< HSUSBD_T::GINTSTS: USBIF Position */ 00938 #define HSUSBD_GINTSTS_USBIF_Msk (0x1ul << HSUSBD_GINTSTS_USBIF_Pos) /*!< HSUSBD_T::GINTSTS: USBIF Mask */ 00939 00940 #define HSUSBD_GINTSTS_CEPIF_Pos (1) /*!< HSUSBD_T::GINTSTS: CEPIF Position */ 00941 #define HSUSBD_GINTSTS_CEPIF_Msk (0x1ul << HSUSBD_GINTSTS_CEPIF_Pos) /*!< HSUSBD_T::GINTSTS: CEPIF Mask */ 00942 00943 #define HSUSBD_GINTSTS_EPAIF_Pos (2) /*!< HSUSBD_T::GINTSTS: EPAIF Position */ 00944 #define HSUSBD_GINTSTS_EPAIF_Msk (0x1ul << HSUSBD_GINTSTS_EPAIF_Pos) /*!< HSUSBD_T::GINTSTS: EPAIF Mask */ 00945 00946 #define HSUSBD_GINTSTS_EPBIF_Pos (3) /*!< HSUSBD_T::GINTSTS: EPBIF Position */ 00947 #define HSUSBD_GINTSTS_EPBIF_Msk (0x1ul << HSUSBD_GINTSTS_EPBIF_Pos) /*!< HSUSBD_T::GINTSTS: EPBIF Mask */ 00948 00949 #define HSUSBD_GINTSTS_EPCIF_Pos (4) /*!< HSUSBD_T::GINTSTS: EPCIF Position */ 00950 #define HSUSBD_GINTSTS_EPCIF_Msk (0x1ul << HSUSBD_GINTSTS_EPCIF_Pos) /*!< HSUSBD_T::GINTSTS: EPCIF Mask */ 00951 00952 #define HSUSBD_GINTSTS_EPDIF_Pos (5) /*!< HSUSBD_T::GINTSTS: EPDIF Position */ 00953 #define HSUSBD_GINTSTS_EPDIF_Msk (0x1ul << HSUSBD_GINTSTS_EPDIF_Pos) /*!< HSUSBD_T::GINTSTS: EPDIF Mask */ 00954 00955 #define HSUSBD_GINTSTS_EPEIF_Pos (6) /*!< HSUSBD_T::GINTSTS: EPEIF Position */ 00956 #define HSUSBD_GINTSTS_EPEIF_Msk (0x1ul << HSUSBD_GINTSTS_EPEIF_Pos) /*!< HSUSBD_T::GINTSTS: EPEIF Mask */ 00957 00958 #define HSUSBD_GINTSTS_EPFIF_Pos (7) /*!< HSUSBD_T::GINTSTS: EPFIF Position */ 00959 #define HSUSBD_GINTSTS_EPFIF_Msk (0x1ul << HSUSBD_GINTSTS_EPFIF_Pos) /*!< HSUSBD_T::GINTSTS: EPFIF Mask */ 00960 00961 #define HSUSBD_GINTSTS_EPGIF_Pos (8) /*!< HSUSBD_T::GINTSTS: EPGIF Position */ 00962 #define HSUSBD_GINTSTS_EPGIF_Msk (0x1ul << HSUSBD_GINTSTS_EPGIF_Pos) /*!< HSUSBD_T::GINTSTS: EPGIF Mask */ 00963 00964 #define HSUSBD_GINTSTS_EPHIF_Pos (9) /*!< HSUSBD_T::GINTSTS: EPHIF Position */ 00965 #define HSUSBD_GINTSTS_EPHIF_Msk (0x1ul << HSUSBD_GINTSTS_EPHIF_Pos) /*!< HSUSBD_T::GINTSTS: EPHIF Mask */ 00966 00967 #define HSUSBD_GINTSTS_EPIIF_Pos (10) /*!< HSUSBD_T::GINTSTS: EPIIF Position */ 00968 #define HSUSBD_GINTSTS_EPIIF_Msk (0x1ul << HSUSBD_GINTSTS_EPIIF_Pos) /*!< HSUSBD_T::GINTSTS: EPIIF Mask */ 00969 00970 #define HSUSBD_GINTSTS_EPJIF_Pos (11) /*!< HSUSBD_T::GINTSTS: EPJIF Position */ 00971 #define HSUSBD_GINTSTS_EPJIF_Msk (0x1ul << HSUSBD_GINTSTS_EPJIF_Pos) /*!< HSUSBD_T::GINTSTS: EPJIF Mask */ 00972 00973 #define HSUSBD_GINTSTS_EPKIF_Pos (12) /*!< HSUSBD_T::GINTSTS: EPKIF Position */ 00974 #define HSUSBD_GINTSTS_EPKIF_Msk (0x1ul << HSUSBD_GINTSTS_EPKIF_Pos) /*!< HSUSBD_T::GINTSTS: EPKIF Mask */ 00975 00976 #define HSUSBD_GINTSTS_EPLIF_Pos (13) /*!< HSUSBD_T::GINTSTS: EPLIF Position */ 00977 #define HSUSBD_GINTSTS_EPLIF_Msk (0x1ul << HSUSBD_GINTSTS_EPLIF_Pos) /*!< HSUSBD_T::GINTSTS: EPLIF Mask */ 00978 00979 #define HSUSBD_GINTEN_USBIEN_Pos (0) /*!< HSUSBD_T::GINTEN: USBIEN Position */ 00980 #define HSUSBD_GINTEN_USBIEN_Msk (0x1ul << HSUSBD_GINTEN_USBIEN_Pos) /*!< HSUSBD_T::GINTEN: USBIEN Mask */ 00981 00982 #define HSUSBD_GINTEN_CEPIEN_Pos (1) /*!< HSUSBD_T::GINTEN: CEPIEN Position */ 00983 #define HSUSBD_GINTEN_CEPIEN_Msk (0x1ul << HSUSBD_GINTEN_CEPIEN_Pos) /*!< HSUSBD_T::GINTEN: CEPIEN Mask */ 00984 00985 #define HSUSBD_GINTEN_EPAIEN_Pos (2) /*!< HSUSBD_T::GINTEN: EPAIEN Position */ 00986 #define HSUSBD_GINTEN_EPAIEN_Msk (0x1ul << HSUSBD_GINTEN_EPAIEN_Pos) /*!< HSUSBD_T::GINTEN: EPAIEN Mask */ 00987 00988 #define HSUSBD_GINTEN_EPBIEN_Pos (3) /*!< HSUSBD_T::GINTEN: EPBIEN Position */ 00989 #define HSUSBD_GINTEN_EPBIEN_Msk (0x1ul << HSUSBD_GINTEN_EPBIEN_Pos) /*!< HSUSBD_T::GINTEN: EPBIEN Mask */ 00990 00991 #define HSUSBD_GINTEN_EPCIEN_Pos (4) /*!< HSUSBD_T::GINTEN: EPCIEN Position */ 00992 #define HSUSBD_GINTEN_EPCIEN_Msk (0x1ul << HSUSBD_GINTEN_EPCIEN_Pos) /*!< HSUSBD_T::GINTEN: EPCIEN Mask */ 00993 00994 #define HSUSBD_GINTEN_EPDIEN_Pos (5) /*!< HSUSBD_T::GINTEN: EPDIEN Position */ 00995 #define HSUSBD_GINTEN_EPDIEN_Msk (0x1ul << HSUSBD_GINTEN_EPDIEN_Pos) /*!< HSUSBD_T::GINTEN: EPDIEN Mask */ 00996 00997 #define HSUSBD_GINTEN_EPEIEN_Pos (6) /*!< HSUSBD_T::GINTEN: EPEIEN Position */ 00998 #define HSUSBD_GINTEN_EPEIEN_Msk (0x1ul << HSUSBD_GINTEN_EPEIEN_Pos) /*!< HSUSBD_T::GINTEN: EPEIEN Mask */ 00999 01000 #define HSUSBD_GINTEN_EPFIEN_Pos (7) /*!< HSUSBD_T::GINTEN: EPFIEN Position */ 01001 #define HSUSBD_GINTEN_EPFIEN_Msk (0x1ul << HSUSBD_GINTEN_EPFIEN_Pos) /*!< HSUSBD_T::GINTEN: EPFIEN Mask */ 01002 01003 #define HSUSBD_GINTEN_EPGIEN_Pos (8) /*!< HSUSBD_T::GINTEN: EPGIEN Position */ 01004 #define HSUSBD_GINTEN_EPGIEN_Msk (0x1ul << HSUSBD_GINTEN_EPGIEN_Pos) /*!< HSUSBD_T::GINTEN: EPGIEN Mask */ 01005 01006 #define HSUSBD_GINTEN_EPHIEN_Pos (9) /*!< HSUSBD_T::GINTEN: EPHIEN Position */ 01007 #define HSUSBD_GINTEN_EPHIEN_Msk (0x1ul << HSUSBD_GINTEN_EPHIEN_Pos) /*!< HSUSBD_T::GINTEN: EPHIEN Mask */ 01008 01009 #define HSUSBD_GINTEN_EPIIEN_Pos (10) /*!< HSUSBD_T::GINTEN: EPIIEN Position */ 01010 #define HSUSBD_GINTEN_EPIIEN_Msk (0x1ul << HSUSBD_GINTEN_EPIIEN_Pos) /*!< HSUSBD_T::GINTEN: EPIIEN Mask */ 01011 01012 #define HSUSBD_GINTEN_EPJIEN_Pos (11) /*!< HSUSBD_T::GINTEN: EPJIEN Position */ 01013 #define HSUSBD_GINTEN_EPJIEN_Msk (0x1ul << HSUSBD_GINTEN_EPJIEN_Pos) /*!< HSUSBD_T::GINTEN: EPJIEN Mask */ 01014 01015 #define HSUSBD_GINTEN_EPKIEN_Pos (12) /*!< HSUSBD_T::GINTEN: EPKIEN Position */ 01016 #define HSUSBD_GINTEN_EPKIEN_Msk (0x1ul << HSUSBD_GINTEN_EPKIEN_Pos) /*!< HSUSBD_T::GINTEN: EPKIEN Mask */ 01017 01018 #define HSUSBD_GINTEN_EPLIEN_Pos (13) /*!< HSUSBD_T::GINTEN: EPLIEN Position */ 01019 #define HSUSBD_GINTEN_EPLIEN_Msk (0x1ul << HSUSBD_GINTEN_EPLIEN_Pos) /*!< HSUSBD_T::GINTEN: EPLIEN Mask */ 01020 01021 #define HSUSBD_BUSINTSTS_SOFIF_Pos (0) /*!< HSUSBD_T::BUSINTSTS: SOFIF Position */ 01022 #define HSUSBD_BUSINTSTS_SOFIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SOFIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SOFIF Mask */ 01023 01024 #define HSUSBD_BUSINTSTS_RSTIF_Pos (1) /*!< HSUSBD_T::BUSINTSTS: RSTIF Position */ 01025 #define HSUSBD_BUSINTSTS_RSTIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RSTIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RSTIF Mask */ 01026 01027 #define HSUSBD_BUSINTSTS_RESUMEIF_Pos (2) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Position */ 01028 #define HSUSBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RESUMEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Mask */ 01029 01030 #define HSUSBD_BUSINTSTS_SUSPENDIF_Pos (3) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Position*/ 01031 #define HSUSBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SUSPENDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Mask */ 01032 01033 #define HSUSBD_BUSINTSTS_HISPDIF_Pos (4) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Position */ 01034 #define HSUSBD_BUSINTSTS_HISPDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_HISPDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Mask */ 01035 01036 #define HSUSBD_BUSINTSTS_DMADONEIF_Pos (5) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Position*/ 01037 #define HSUSBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_DMADONEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Mask */ 01038 01039 #define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos (6) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Position*/ 01040 #define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Mask */ 01041 01042 #define HSUSBD_BUSINTSTS_VBUSDETIF_Pos (8) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Position*/ 01043 #define HSUSBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << HSUSBD_BUSINTSTS_VBUSDETIF_Pos) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Mask */ 01044 01045 #define HSUSBD_BUSINTEN_SOFIEN_Pos (0) /*!< HSUSBD_T::BUSINTEN: SOFIEN Position */ 01046 #define HSUSBD_BUSINTEN_SOFIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SOFIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SOFIEN Mask */ 01047 01048 #define HSUSBD_BUSINTEN_RSTIEN_Pos (1) /*!< HSUSBD_T::BUSINTEN: RSTIEN Position */ 01049 #define HSUSBD_BUSINTEN_RSTIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RSTIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RSTIEN Mask */ 01050 01051 #define HSUSBD_BUSINTEN_RESUMEIEN_Pos (2) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Position */ 01052 #define HSUSBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RESUMEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Mask */ 01053 01054 #define HSUSBD_BUSINTEN_SUSPENDIEN_Pos (3) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Position*/ 01055 #define HSUSBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SUSPENDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Mask */ 01056 01057 #define HSUSBD_BUSINTEN_HISPDIEN_Pos (4) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Position */ 01058 #define HSUSBD_BUSINTEN_HISPDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_HISPDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Mask */ 01059 01060 #define HSUSBD_BUSINTEN_DMADONEIEN_Pos (5) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Position*/ 01061 #define HSUSBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_DMADONEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Mask */ 01062 01063 #define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos (6) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Position*/ 01064 #define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Mask */ 01065 01066 #define HSUSBD_BUSINTEN_VBUSDETIEN_Pos (8) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Position*/ 01067 #define HSUSBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << HSUSBD_BUSINTEN_VBUSDETIEN_Pos) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Mask */ 01068 01069 #define HSUSBD_OPER_RESUMEEN_Pos (0) /*!< HSUSBD_T::OPER: RESUMEEN Position */ 01070 #define HSUSBD_OPER_RESUMEEN_Msk (0x1ul << HSUSBD_OPER_RESUMEEN_Pos) /*!< HSUSBD_T::OPER: RESUMEEN Mask */ 01071 01072 #define HSUSBD_OPER_HISPDEN_Pos (1) /*!< HSUSBD_T::OPER: HISPDEN Position */ 01073 #define HSUSBD_OPER_HISPDEN_Msk (0x1ul << HSUSBD_OPER_HISPDEN_Pos) /*!< HSUSBD_T::OPER: HISPDEN Mask */ 01074 01075 #define HSUSBD_OPER_CURSPD_Pos (2) /*!< HSUSBD_T::OPER: CURSPD Position */ 01076 #define HSUSBD_OPER_CURSPD_Msk (0x1ul << HSUSBD_OPER_CURSPD_Pos) /*!< HSUSBD_T::OPER: CURSPD Mask */ 01077 01078 #define HSUSBD_FRAMECNT_MFRAMECNT_Pos (0) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Position */ 01079 #define HSUSBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << HSUSBD_FRAMECNT_MFRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Mask */ 01080 01081 #define HSUSBD_FRAMECNT_FRAMECNT_Pos (3) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Position */ 01082 #define HSUSBD_FRAMECNT_FRAMECNT_Msk (0x7fful << HSUSBD_FRAMECNT_FRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Mask */ 01083 01084 #define HSUSBD_FADDR_FADDR_Pos (0) /*!< HSUSBD_T::FADDR: FADDR Position */ 01085 #define HSUSBD_FADDR_FADDR_Msk (0x7ful << HSUSBD_FADDR_FADDR_Pos) /*!< HSUSBD_T::FADDR: FADDR Mask */ 01086 01087 #define HSUSBD_TEST_TESTMODE_Pos (0) /*!< HSUSBD_T::TEST: TESTMODE Position */ 01088 #define HSUSBD_TEST_TESTMODE_Msk (0x7ul << HSUSBD_TEST_TESTMODE_Pos) /*!< HSUSBD_T::TEST: TESTMODE Mask */ 01089 01090 #define HSUSBD_CEPDAT_DAT_Pos (0) /*!< HSUSBD_T::CEPDAT: DAT Position */ 01091 #define HSUSBD_CEPDAT_DAT_Msk (0xfffffffful << HSUSBD_CEPDAT_DAT_Pos) /*!< HSUSBD_T::CEPDAT: DAT Mask */ 01092 01093 #define HSUSBD_CEPCTL_NAKCLR_Pos (0) /*!< HSUSBD_T::CEPCTL: NAKCLR Position */ 01094 #define HSUSBD_CEPCTL_NAKCLR_Msk (0x1ul << HSUSBD_CEPCTL_NAKCLR_Pos) /*!< HSUSBD_T::CEPCTL: NAKCLR Mask */ 01095 01096 #define HSUSBD_CEPCTL_STALLEN_Pos (1) /*!< HSUSBD_T::CEPCTL: STALLEN Position */ 01097 #define HSUSBD_CEPCTL_STALLEN_Msk (0x1ul << HSUSBD_CEPCTL_STALLEN_Pos) /*!< HSUSBD_T::CEPCTL: STALLEN Mask */ 01098 01099 #define HSUSBD_CEPCTL_ZEROLEN_Pos (2) /*!< HSUSBD_T::CEPCTL: ZEROLEN Position */ 01100 #define HSUSBD_CEPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_CEPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::CEPCTL: ZEROLEN Mask */ 01101 01102 #define HSUSBD_CEPCTL_FLUSH_Pos (3) /*!< HSUSBD_T::CEPCTL: FLUSH Position */ 01103 #define HSUSBD_CEPCTL_FLUSH_Msk (0x1ul << HSUSBD_CEPCTL_FLUSH_Pos) /*!< HSUSBD_T::CEPCTL: FLUSH Mask */ 01104 01105 #define HSUSBD_CEPINTEN_SETUPTKIEN_Pos (0) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Position*/ 01106 #define HSUSBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Mask */ 01107 01108 #define HSUSBD_CEPINTEN_SETUPPKIEN_Pos (1) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Position*/ 01109 #define HSUSBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Mask */ 01110 01111 #define HSUSBD_CEPINTEN_OUTTKIEN_Pos (2) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Position */ 01112 #define HSUSBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Mask */ 01113 01114 #define HSUSBD_CEPINTEN_INTKIEN_Pos (3) /*!< HSUSBD_T::CEPINTEN: INTKIEN Position */ 01115 #define HSUSBD_CEPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: INTKIEN Mask */ 01116 01117 #define HSUSBD_CEPINTEN_PINGIEN_Pos (4) /*!< HSUSBD_T::CEPINTEN: PINGIEN Position */ 01118 #define HSUSBD_CEPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_CEPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::CEPINTEN: PINGIEN Mask */ 01119 01120 #define HSUSBD_CEPINTEN_TXPKIEN_Pos (5) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Position */ 01121 #define HSUSBD_CEPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Mask */ 01122 01123 #define HSUSBD_CEPINTEN_RXPKIEN_Pos (6) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Position */ 01124 #define HSUSBD_CEPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Mask */ 01125 01126 #define HSUSBD_CEPINTEN_NAKIEN_Pos (7) /*!< HSUSBD_T::CEPINTEN: NAKIEN Position */ 01127 #define HSUSBD_CEPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: NAKIEN Mask */ 01128 01129 #define HSUSBD_CEPINTEN_STALLIEN_Pos (8) /*!< HSUSBD_T::CEPINTEN: STALLIEN Position */ 01130 #define HSUSBD_CEPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STALLIEN Mask */ 01131 01132 #define HSUSBD_CEPINTEN_ERRIEN_Pos (9) /*!< HSUSBD_T::CEPINTEN: ERRIEN Position */ 01133 #define HSUSBD_CEPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_CEPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::CEPINTEN: ERRIEN Mask */ 01134 01135 #define HSUSBD_CEPINTEN_STSDONEIEN_Pos (10) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Position*/ 01136 #define HSUSBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STSDONEIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Mask */ 01137 01138 #define HSUSBD_CEPINTEN_BUFFULLIEN_Pos (11) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Position*/ 01139 #define HSUSBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Mask */ 01140 01141 #define HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos (12) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Position*/ 01142 #define HSUSBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Mask */ 01143 01144 #define HSUSBD_CEPINTSTS_SETUPTKIF_Pos (0) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Position*/ 01145 #define HSUSBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Mask */ 01146 01147 #define HSUSBD_CEPINTSTS_SETUPPKIF_Pos (1) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Position*/ 01148 #define HSUSBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Mask */ 01149 01150 #define HSUSBD_CEPINTSTS_OUTTKIF_Pos (2) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Position */ 01151 #define HSUSBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Mask */ 01152 01153 #define HSUSBD_CEPINTSTS_INTKIF_Pos (3) /*!< HSUSBD_T::CEPINTSTS: INTKIF Position */ 01154 #define HSUSBD_CEPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: INTKIF Mask */ 01155 01156 #define HSUSBD_CEPINTSTS_PINGIF_Pos (4) /*!< HSUSBD_T::CEPINTSTS: PINGIF Position */ 01157 #define HSUSBD_CEPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_CEPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::CEPINTSTS: PINGIF Mask */ 01158 01159 #define HSUSBD_CEPINTSTS_TXPKIF_Pos (5) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Position */ 01160 #define HSUSBD_CEPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Mask */ 01161 01162 #define HSUSBD_CEPINTSTS_RXPKIF_Pos (6) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Position */ 01163 #define HSUSBD_CEPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Mask */ 01164 01165 #define HSUSBD_CEPINTSTS_NAKIF_Pos (7) /*!< HSUSBD_T::CEPINTSTS: NAKIF Position */ 01166 #define HSUSBD_CEPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: NAKIF Mask */ 01167 01168 #define HSUSBD_CEPINTSTS_STALLIF_Pos (8) /*!< HSUSBD_T::CEPINTSTS: STALLIF Position */ 01169 #define HSUSBD_CEPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STALLIF Mask */ 01170 01171 #define HSUSBD_CEPINTSTS_ERRIF_Pos (9) /*!< HSUSBD_T::CEPINTSTS: ERRIF Position */ 01172 #define HSUSBD_CEPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_CEPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::CEPINTSTS: ERRIF Mask */ 01173 01174 #define HSUSBD_CEPINTSTS_STSDONEIF_Pos (10) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Position*/ 01175 #define HSUSBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STSDONEIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Mask */ 01176 01177 #define HSUSBD_CEPINTSTS_BUFFULLIF_Pos (11) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Position*/ 01178 #define HSUSBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Mask */ 01179 01180 #define HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos (12) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Position*/ 01181 #define HSUSBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Mask */ 01182 01183 #define HSUSBD_CEPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::CEPTXCNT: TXCNT Position */ 01184 #define HSUSBD_CEPTXCNT_TXCNT_Msk (0xfful << HSUSBD_CEPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::CEPTXCNT: TXCNT Mask */ 01185 01186 #define HSUSBD_CEPRXCNT_RXCNT_Pos (0) /*!< HSUSBD_T::CEPRXCNT: RXCNT Position */ 01187 #define HSUSBD_CEPRXCNT_RXCNT_Msk (0xfful << HSUSBD_CEPRXCNT_RXCNT_Pos) /*!< HSUSBD_T::CEPRXCNT: RXCNT Mask */ 01188 01189 #define HSUSBD_CEPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::CEPDATCNT: DATCNT Position */ 01190 #define HSUSBD_CEPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_CEPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::CEPDATCNT: DATCNT Mask */ 01191 01192 #define HSUSBD_SETUP1_0_SETUP0_Pos (0) /*!< HSUSBD_T::SETUP1_0: SETUP0 Position */ 01193 #define HSUSBD_SETUP1_0_SETUP0_Msk (0xfful << HSUSBD_SETUP1_0_SETUP0_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP0 Mask */ 01194 01195 #define HSUSBD_SETUP1_0_SETUP1_Pos (8) /*!< HSUSBD_T::SETUP1_0: SETUP1 Position */ 01196 #define HSUSBD_SETUP1_0_SETUP1_Msk (0xfful << HSUSBD_SETUP1_0_SETUP1_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP1 Mask */ 01197 01198 #define HSUSBD_SETUP3_2_SETUP2_Pos (0) /*!< HSUSBD_T::SETUP3_2: SETUP2 Position */ 01199 #define HSUSBD_SETUP3_2_SETUP2_Msk (0xfful << HSUSBD_SETUP3_2_SETUP2_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP2 Mask */ 01200 01201 #define HSUSBD_SETUP3_2_SETUP3_Pos (8) /*!< HSUSBD_T::SETUP3_2: SETUP3 Position */ 01202 #define HSUSBD_SETUP3_2_SETUP3_Msk (0xfful << HSUSBD_SETUP3_2_SETUP3_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP3 Mask */ 01203 01204 #define HSUSBD_SETUP5_4_SETUP4_Pos (0) /*!< HSUSBD_T::SETUP5_4: SETUP4 Position */ 01205 #define HSUSBD_SETUP5_4_SETUP4_Msk (0xfful << HSUSBD_SETUP5_4_SETUP4_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP4 Mask */ 01206 01207 #define HSUSBD_SETUP5_4_SETUP5_Pos (8) /*!< HSUSBD_T::SETUP5_4: SETUP5 Position */ 01208 #define HSUSBD_SETUP5_4_SETUP5_Msk (0xfful << HSUSBD_SETUP5_4_SETUP5_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP5 Mask */ 01209 01210 #define HSUSBD_SETUP7_6_SETUP6_Pos (0) /*!< HSUSBD_T::SETUP7_6: SETUP6 Position */ 01211 #define HSUSBD_SETUP7_6_SETUP6_Msk (0xfful << HSUSBD_SETUP7_6_SETUP6_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP6 Mask */ 01212 01213 #define HSUSBD_SETUP7_6_SETUP7_Pos (8) /*!< HSUSBD_T::SETUP7_6: SETUP7 Position */ 01214 #define HSUSBD_SETUP7_6_SETUP7_Msk (0xfful << HSUSBD_SETUP7_6_SETUP7_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP7 Mask */ 01215 01216 #define HSUSBD_CEPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::CEPBUFST: SADDR Position */ 01217 #define HSUSBD_CEPBUFST_SADDR_Msk (0xffful << HSUSBD_CEPBUFST_SADDR_Pos) /*!< HSUSBD_T::CEPBUFST: SADDR Mask */ 01218 01219 #define HSUSBD_CEPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::CEPBUFEND: EADDR Position */ 01220 #define HSUSBD_CEPBUFEND_EADDR_Msk (0xffful << HSUSBD_CEPBUFEND_EADDR_Pos) /*!< HSUSBD_T::CEPBUFEND: EADDR Mask */ 01221 01222 #define HSUSBD_DMACTL_EPNUM_Pos (0) /*!< HSUSBD_T::DMACTL: EPNUM Position */ 01223 #define HSUSBD_DMACTL_EPNUM_Msk (0xful << HSUSBD_DMACTL_EPNUM_Pos) /*!< HSUSBD_T::DMACTL: EPNUM Mask */ 01224 01225 #define HSUSBD_DMACTL_DMARD_Pos (4) /*!< HSUSBD_T::DMACTL: DMARD Position */ 01226 #define HSUSBD_DMACTL_DMARD_Msk (0x1ul << HSUSBD_DMACTL_DMARD_Pos) /*!< HSUSBD_T::DMACTL: DMARD Mask */ 01227 01228 #define HSUSBD_DMACTL_DMAEN_Pos (5) /*!< HSUSBD_T::DMACTL: DMAEN Position */ 01229 #define HSUSBD_DMACTL_DMAEN_Msk (0x1ul << HSUSBD_DMACTL_DMAEN_Pos) /*!< HSUSBD_T::DMACTL: DMAEN Mask */ 01230 01231 #define HSUSBD_DMACTL_SGEN_Pos (6) /*!< HSUSBD_T::DMACTL: SGEN Position */ 01232 #define HSUSBD_DMACTL_SGEN_Msk (0x1ul << HSUSBD_DMACTL_SGEN_Pos) /*!< HSUSBD_T::DMACTL: SGEN Mask */ 01233 01234 #define HSUSBD_DMACTL_DMARST_Pos (7) /*!< HSUSBD_T::DMACTL: DMARST Position */ 01235 #define HSUSBD_DMACTL_DMARST_Msk (0x1ul << HSUSBD_DMACTL_DMARST_Pos) /*!< HSUSBD_T::DMACTL: DMARST Mask */ 01236 01237 #define HSUSBD_DMACTL_SVINEP_Pos (8) /*!< HSUSBD_T::DMACTL: SVINEP Position */ 01238 #define HSUSBD_DMACTL_SVINEP_Msk (0x1ul << HSUSBD_DMACTL_SVINEP_Pos) /*!< HSUSBD_T::DMACTL: SVINEP Mask */ 01239 01240 #define HSUSBD_DMACNT_DMACNT_Pos (0) /*!< HSUSBD_T::DMACNT: DMACNT Position */ 01241 #define HSUSBD_DMACNT_DMACNT_Msk (0xffffful << HSUSBD_DMACNT_DMACNT_Pos) /*!< HSUSBD_T::DMACNT: DMACNT Mask */ 01242 01243 #define HSUSBD_EPDAT_EPDAT_Pos (0) /*!< HSUSBD_T::EPDAT: EPDAT Position */ 01244 #define HSUSBD_EPDAT_EPDAT_Msk (0xfffffffful << HSUSBD_EPDAT_EPDAT_Pos) /*!< HSUSBD_T::EPDAT: EPDAT Mask */ 01245 01246 #define HSUSBD_EPINTSTS_BUFFULLIF_Pos (0) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Position */ 01247 #define HSUSBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Mask */ 01248 01249 #define HSUSBD_EPINTSTS_BUFEMPTYIF_Pos (1) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Position*/ 01250 #define HSUSBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Mask */ 01251 01252 #define HSUSBD_EPINTSTS_SHORTTXIF_Pos (2) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Position */ 01253 #define HSUSBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTTXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Mask */ 01254 01255 #define HSUSBD_EPINTSTS_TXPKIF_Pos (3) /*!< HSUSBD_T::EPINTSTS: TXPKIF Position */ 01256 #define HSUSBD_EPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: TXPKIF Mask */ 01257 01258 #define HSUSBD_EPINTSTS_RXPKIF_Pos (4) /*!< HSUSBD_T::EPINTSTS: RXPKIF Position */ 01259 #define HSUSBD_EPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: RXPKIF Mask */ 01260 01261 #define HSUSBD_EPINTSTS_OUTTKIF_Pos (5) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Position */ 01262 #define HSUSBD_EPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Mask */ 01263 01264 #define HSUSBD_EPINTSTS_INTKIF_Pos (6) /*!< HSUSBD_T::EPINTSTS: INTKIF Position */ 01265 #define HSUSBD_EPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: INTKIF Mask */ 01266 01267 #define HSUSBD_EPINTSTS_PINGIF_Pos (7) /*!< HSUSBD_T::EPINTSTS: PINGIF Position */ 01268 #define HSUSBD_EPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_EPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::EPINTSTS: PINGIF Mask */ 01269 01270 #define HSUSBD_EPINTSTS_NAKIF_Pos (8) /*!< HSUSBD_T::EPINTSTS: NAKIF Position */ 01271 #define HSUSBD_EPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_EPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::EPINTSTS: NAKIF Mask */ 01272 01273 #define HSUSBD_EPINTSTS_STALLIF_Pos (9) /*!< HSUSBD_T::EPINTSTS: STALLIF Position */ 01274 #define HSUSBD_EPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_EPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::EPINTSTS: STALLIF Mask */ 01275 01276 #define HSUSBD_EPINTSTS_NYETIF_Pos (10) /*!< HSUSBD_T::EPINTSTS: NYETIF Position */ 01277 #define HSUSBD_EPINTSTS_NYETIF_Msk (0x1ul << HSUSBD_EPINTSTS_NYETIF_Pos) /*!< HSUSBD_T::EPINTSTS: NYETIF Mask */ 01278 01279 #define HSUSBD_EPINTSTS_ERRIF_Pos (11) /*!< HSUSBD_T::EPINTSTS: ERRIF Position */ 01280 #define HSUSBD_EPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_EPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::EPINTSTS: ERRIF Mask */ 01281 01282 #define HSUSBD_EPINTSTS_SHORTRXIF_Pos (12) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Position */ 01283 #define HSUSBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTRXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Mask */ 01284 01285 #define HSUSBD_EPINTEN_BUFFULLIEN_Pos (0) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Position */ 01286 #define HSUSBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Mask */ 01287 01288 #define HSUSBD_EPINTEN_BUFEMPTYIEN_Pos (1) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Position*/ 01289 #define HSUSBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Mask */ 01290 01291 #define HSUSBD_EPINTEN_SHORTTXIEN_Pos (2) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Position */ 01292 #define HSUSBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTTXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Mask */ 01293 01294 #define HSUSBD_EPINTEN_TXPKIEN_Pos (3) /*!< HSUSBD_T::EPINTEN: TXPKIEN Position */ 01295 #define HSUSBD_EPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: TXPKIEN Mask */ 01296 01297 #define HSUSBD_EPINTEN_RXPKIEN_Pos (4) /*!< HSUSBD_T::EPINTEN: RXPKIEN Position */ 01298 #define HSUSBD_EPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: RXPKIEN Mask */ 01299 01300 #define HSUSBD_EPINTEN_OUTTKIEN_Pos (5) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Position */ 01301 #define HSUSBD_EPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Mask */ 01302 01303 #define HSUSBD_EPINTEN_INTKIEN_Pos (6) /*!< HSUSBD_T::EPINTEN: INTKIEN Position */ 01304 #define HSUSBD_EPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: INTKIEN Mask */ 01305 01306 #define HSUSBD_EPINTEN_PINGIEN_Pos (7) /*!< HSUSBD_T::EPINTEN: PINGIEN Position */ 01307 #define HSUSBD_EPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_EPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::EPINTEN: PINGIEN Mask */ 01308 01309 #define HSUSBD_EPINTEN_NAKIEN_Pos (8) /*!< HSUSBD_T::EPINTEN: NAKIEN Position */ 01310 #define HSUSBD_EPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_EPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::EPINTEN: NAKIEN Mask */ 01311 01312 #define HSUSBD_EPINTEN_STALLIEN_Pos (9) /*!< HSUSBD_T::EPINTEN: STALLIEN Position */ 01313 #define HSUSBD_EPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_EPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::EPINTEN: STALLIEN Mask */ 01314 01315 #define HSUSBD_EPINTEN_NYETIEN_Pos (10) /*!< HSUSBD_T::EPINTEN: NYETIEN Position */ 01316 #define HSUSBD_EPINTEN_NYETIEN_Msk (0x1ul << HSUSBD_EPINTEN_NYETIEN_Pos) /*!< HSUSBD_T::EPINTEN: NYETIEN Mask */ 01317 01318 #define HSUSBD_EPINTEN_ERRIEN_Pos (11) /*!< HSUSBD_T::EPINTEN: ERRIEN Position */ 01319 #define HSUSBD_EPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_EPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::EPINTEN: ERRIEN Mask */ 01320 01321 #define HSUSBD_EPINTEN_SHORTRXIEN_Pos (12) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Position */ 01322 #define HSUSBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTRXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Mask */ 01323 01324 #define HSUSBD_EPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::EPDATCNT: DATCNT Position */ 01325 #define HSUSBD_EPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_EPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::EPDATCNT: DATCNT Mask */ 01326 01327 #define HSUSBD_EPDATCNT_DMALOOP_Pos (16) /*!< HSUSBD_T::EPDATCNT: DMALOOP Position */ 01328 #define HSUSBD_EPDATCNT_DMALOOP_Msk (0x7ffful << HSUSBD_EPDATCNT_DMALOOP_Pos) /*!< HSUSBD_T::EPDATCNT: DMALOOP Mask */ 01329 01330 #define HSUSBD_EPRSPCTL_FLUSH_Pos (0) /*!< HSUSBD_T::EPRSPCTL: FLUSH Position */ 01331 #define HSUSBD_EPRSPCTL_FLUSH_Msk (0x1ul << HSUSBD_EPRSPCTL_FLUSH_Pos) /*!< HSUSBD_T::EPRSPCTL: FLUSH Mask */ 01332 01333 #define HSUSBD_EPRSPCTL_MODE_Pos (1) /*!< HSUSBD_T::EPRSPCTL: MODE Position */ 01334 #define HSUSBD_EPRSPCTL_MODE_Msk (0x3ul << HSUSBD_EPRSPCTL_MODE_Pos) /*!< HSUSBD_T::EPRSPCTL: MODE Mask */ 01335 01336 #define HSUSBD_EPRSPCTL_TOGGLE_Pos (3) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Position */ 01337 #define HSUSBD_EPRSPCTL_TOGGLE_Msk (0x1ul << HSUSBD_EPRSPCTL_TOGGLE_Pos) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Mask */ 01338 01339 #define HSUSBD_EPRSPCTL_HALT_Pos (4) /*!< HSUSBD_T::EPRSPCTL: HALT Position */ 01340 #define HSUSBD_EPRSPCTL_HALT_Msk (0x1ul << HSUSBD_EPRSPCTL_HALT_Pos) /*!< HSUSBD_T::EPRSPCTL: HALT Mask */ 01341 01342 #define HSUSBD_EPRSPCTL_ZEROLEN_Pos (5) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Position */ 01343 #define HSUSBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_EPRSPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Mask */ 01344 01345 #define HSUSBD_EPRSPCTL_SHORTTXEN_Pos (6) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Position */ 01346 #define HSUSBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << HSUSBD_EPRSPCTL_SHORTTXEN_Pos) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Mask */ 01347 01348 #define HSUSBD_EPRSPCTL_DISBUF_Pos (7) /*!< HSUSBD_T::EPRSPCTL: DISBUF Position */ 01349 #define HSUSBD_EPRSPCTL_DISBUF_Msk (0x1ul << HSUSBD_EPRSPCTL_DISBUF_Pos) /*!< HSUSBD_T::EPRSPCTL: DISBUF Mask */ 01350 01351 #define HSUSBD_EPMPS_EPMPS_Pos (0) /*!< HSUSBD_T::EPMPS: EPMPS Position */ 01352 #define HSUSBD_EPMPS_EPMPS_Msk (0x7fful << HSUSBD_EPMPS_EPMPS_Pos) /*!< HSUSBD_T::EPMPS: EPMPS Mask */ 01353 01354 #define HSUSBD_EPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::EPTXCNT: TXCNT Position */ 01355 #define HSUSBD_EPTXCNT_TXCNT_Msk (0x7fful << HSUSBD_EPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::EPTXCNT: TXCNT Mask */ 01356 01357 #define HSUSBD_EPCFG_EPEN_Pos (0) /*!< HSUSBD_T::EPCFG: EPEN Position */ 01358 #define HSUSBD_EPCFG_EPEN_Msk (0x1ul << HSUSBD_EPCFG_EPEN_Pos) /*!< HSUSBD_T::EPCFG: EPEN Mask */ 01359 01360 #define HSUSBD_EPCFG_EPTYPE_Pos (1) /*!< HSUSBD_T::EPCFG: EPTYPE Position */ 01361 #define HSUSBD_EPCFG_EPTYPE_Msk (0x3ul << HSUSBD_EPCFG_EPTYPE_Pos) /*!< HSUSBD_T::EPCFG: EPTYPE Mask */ 01362 01363 #define HSUSBD_EPCFG_EPDIR_Pos (3) /*!< HSUSBD_T::EPCFG: EPDIR Position */ 01364 #define HSUSBD_EPCFG_EPDIR_Msk (0x1ul << HSUSBD_EPCFG_EPDIR_Pos) /*!< HSUSBD_T::EPCFG: EPDIR Mask */ 01365 01366 #define HSUSBD_EPCFG_EPNUM_Pos (4) /*!< HSUSBD_T::EPCFG: EPNUM Position */ 01367 #define HSUSBD_EPCFG_EPNUM_Msk (0xful << HSUSBD_EPCFG_EPNUM_Pos) /*!< HSUSBD_T::EPCFG: EPNUM Mask */ 01368 01369 #define HSUSBD_EPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::EPBUFST: SADDR Position */ 01370 #define HSUSBD_EPBUFST_SADDR_Msk (0xffful << HSUSBD_EPBUFST_SADDR_Pos) /*!< HSUSBD_T::EPBUFST: SADDR Mask */ 01371 01372 #define HSUSBD_EPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::EPBUFEND: EADDR Position */ 01373 #define HSUSBD_EPBUFEND_EADDR_Msk (0xffful << HSUSBD_EPBUFEND_EADDR_Pos) /*!< HSUSBD_T::EPBUFEND: EADDR Mask */ 01374 01375 #define HSUSBD_DMAADDR_DMAADDR_Pos (0) /*!< HSUSBD_T::DMAADDR: DMAADDR Position */ 01376 #define HSUSBD_DMAADDR_DMAADDR_Msk (0xfffffffful << HSUSBD_DMAADDR_DMAADDR_Pos) /*!< HSUSBD_T::DMAADDR: DMAADDR Mask */ 01377 01378 #define HSUSBD_PHYCTL_DPPUEN_Pos (8) /*!< HSUSBD_T::PHYCTL: DPPUEN Position */ 01379 #define HSUSBD_PHYCTL_DPPUEN_Msk (0x1ul << HSUSBD_PHYCTL_DPPUEN_Pos) /*!< HSUSBD_T::PHYCTL: DPPUEN Mask */ 01380 01381 #define HSUSBD_PHYCTL_PHYEN_Pos (9) /*!< HSUSBD_T::PHYCTL: PHYEN Position */ 01382 #define HSUSBD_PHYCTL_PHYEN_Msk (0x1ul << HSUSBD_PHYCTL_PHYEN_Pos) /*!< HSUSBD_T::PHYCTL: PHYEN Mask */ 01383 01384 #define HSUSBD_PHYCTL_WKEN_Pos (24) /*!< HSUSBD_T::PHYCTL: WKEN Position */ 01385 #define HSUSBD_PHYCTL_WKEN_Msk (0x1ul << HSUSBD_PHYCTL_WKEN_Pos) /*!< HSUSBD_T::PHYCTL: WKEN Mask */ 01386 01387 #define HSUSBD_PHYCTL_VBUSDET_Pos (31) /*!< HSUSBD_T::PHYCTL: VBUSDET Position */ 01388 #define HSUSBD_PHYCTL_VBUSDET_Msk (0x1ul << HSUSBD_PHYCTL_VBUSDET_Pos) /*!< HSUSBD_T::PHYCTL: VBUSDET Mask */ 01389 01390 /**@}*/ /* HSUSBD_CONST */ 01391 /**@}*/ /* end of HSUSBD register group */ 01392 /**@}*/ /* end of REGISTER group */ 01393 01394 #if defined ( __CC_ARM ) 01395 #pragma no_anon_unions 01396 #endif 01397 01398 #endif /* __HSUSBD_REG_H__ */
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