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m480_fmc_reg.h
00001 /**************************************************************************//** 00002 * @file fmc_reg.h 00003 * @version V1.00 00004 * @brief FMC register definition header file 00005 * 00006 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. 00007 * 00008 * Redistribution and use in source and binary forms, with or without modification, 00009 * are permitted provided that the following conditions are met: 00010 * 1. Redistributions of source code must retain the above copyright notice, 00011 * this list of conditions and the following disclaimer. 00012 * 2. Redistributions in binary form must reproduce the above copyright notice, 00013 * this list of conditions and the following disclaimer in the documentation 00014 * and/or other materials provided with the distribution. 00015 * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors 00016 * may be used to endorse or promote products derived from this software 00017 * without specific prior written permission. 00018 * 00019 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00020 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00021 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00022 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00023 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00024 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00025 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00026 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00027 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00028 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00029 *****************************************************************************/ 00030 #ifndef __FMC_REG_H__ 00031 #define __FMC_REG_H__ 00032 00033 #if defined ( __CC_ARM ) 00034 #pragma anon_unions 00035 #endif 00036 00037 /** 00038 @addtogroup REGISTER Control Register 00039 @{ 00040 */ 00041 00042 /** 00043 @addtogroup FMC Flash Memory Controller(FMC) 00044 Memory Mapped Structure for FMC Controller 00045 @{ */ 00046 00047 typedef struct { 00048 /** 00049 * @var FMC_T::ISPCTL 00050 * Offset: 0x00 ISP Control Register 00051 * --------------------------------------------------------------------------------------------------- 00052 * |Bits |Field |Descriptions 00053 * | :----: | :----: | :---- | 00054 * |[0] |ISPEN |ISP Enable Bit (Write Protect) 00055 * | | |ISP function enable bit. Set this bit to enable ISP function. 00056 * | | |0 = ISP function Disabled. 00057 * | | |1 = ISP function Enabled. 00058 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00059 * |[1] |BS |Boot Select (Write Protect) 00060 * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively 00061 * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from 00062 * | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened 00063 * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1. 00064 * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1. 00065 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00066 * |[2] |SPUEN |SPROM Update Enable Bit (Write Protect) 00067 * | | |0 = SPROM cannot be updated. 00068 * | | |1 = SPROM can be updated. 00069 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00070 * |[3] |APUEN |APROM Update Enable Bit (Write Protect) 00071 * | | |0 = APROM cannot be updated when the chip runs in APROM. 00072 * | | |1 = APROM can be updated when the chip runs in APROM. 00073 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00074 * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect) 00075 * | | |0 = CONFIG cannot be updated. 00076 * | | |1 = CONFIG can be updated. 00077 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00078 * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect) 00079 * | | |LDROM update enable bit. 00080 * | | |0 = LDROM cannot be updated. 00081 * | | |1 = LDROM can be updated. 00082 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00083 * |[6] |ISPFF |ISP Fail Flag (Write Protect) 00084 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: 00085 * | | |This bit needs to be cleared by writing 1 to it. 00086 * | | |(1) APROM writes to itself if APUEN is set to 0. 00087 * | | |(2) LDROM writes to itself if LDUEN is set to 0. 00088 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. 00089 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 00090 * | | |(5) SPROM is programmed at SPROM secured mode. 00091 * | | |(6) Page Erase command at LOCK mode with ICE connection 00092 * | | |(7) Erase or Program command at brown-out detected 00093 * | | |(8) Destination address is illegal, such as over an available range. 00094 * | | |(9) Invalid ISP commands 00095 * | | |(10) Vector address is mapping to SPROM region 00096 * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1 00097 * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 00098 * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1 00099 * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. 00100 * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1 00101 * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A 00102 * | | |(17) Read any content of boot loader with ICE connection 00103 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00104 * |[16] |BL |Boot Loader Booting (Write Protect) 00105 * | | |This bit is initiated with the inversed value of MBS (CONFIG0[5]) 00106 * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded 00107 * | | |This bit is used to check chip boot from Boot Loader or not 00108 * | | |User should keep original value of this bit when updating FMC_ISPCTL register. 00109 * | | |0 = Booting from APROM or LDROM. 00110 * | | |1 = Booting from Boot Loader. 00111 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00112 * @var FMC_T::ISPADDR 00113 * Offset: 0x04 ISP Address Register 00114 * --------------------------------------------------------------------------------------------------- 00115 * |Bits |Field |Descriptions 00116 * | :----: | :----: | :---- | 00117 * |[31:0] |ISPADDR |ISP Address 00118 * | | |The NuMicro M480 series is equipped with embedded flash 00119 * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation 00120 * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. 00121 * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 4 Kbytes alignment is necessary for CRC32 checksum calculation. 00122 * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte) 00123 * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte). 00124 * @var FMC_T::ISPDAT 00125 * Offset: 0x08 ISP Data Register 00126 * --------------------------------------------------------------------------------------------------- 00127 * |Bits |Field |Descriptions 00128 * | :----: | :----: | :---- | 00129 * |[31:0] |ISPDAT |ISP Data 00130 * | | |Write data to this register before ISP program operation. 00131 * | | |Read data from this register after ISP read operation. 00132 * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff 00133 * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 4 Kbytes alignment 00134 * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result 00135 * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect 00136 * @var FMC_T::ISPCMD 00137 * Offset: 0x0C ISP Command Register 00138 * --------------------------------------------------------------------------------------------------- 00139 * |Bits |Field |Descriptions 00140 * | :----: | :----: | :---- | 00141 * |[6:0] |CMD |ISP Command 00142 * | | |ISP command table is shown below: 00143 * | | |0x00= FLASH Read. 00144 * | | |0x04= Read Unique ID. 00145 * | | |0x08= Read Flash All-One Result. 00146 * | | |0x0B= Read Company ID. 00147 * | | |0x0C= Read Device ID. 00148 * | | |0x0D= Read Checksum. 00149 * | | |0x21= FLASH 32-bit Program. 00150 * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP. 00151 * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1. 00152 * | | |0x25= FLASH Block Erase. Erase four pages alignment of APROM in BANK0 or BANK1.. 00153 * | | |0x27= FLASH Multi-Word Program. 00154 * | | |0x28= Run Flash All-One Verification. 00155 * | | |0x2D= Run Checksum Calculation. 00156 * | | |0x2E= Vector Remap. 00157 * | | |0x40= FLASH 64-bit Read. 00158 * | | |0x61= FLASH 64-bit Program. 00159 * | | |The other commands are invalid. 00160 * @var FMC_T::ISPTRG 00161 * Offset: 0x10 ISP Trigger Control Register 00162 * --------------------------------------------------------------------------------------------------- 00163 * |Bits |Field |Descriptions 00164 * | :----: | :----: | :---- | 00165 * |[0] |ISPGO |ISP Start Trigger (Write Protect) 00166 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 00167 * | | |0 = ISP operation is finished. 00168 * | | |1 = ISP is progressed. 00169 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00170 * @var FMC_T::DFBA 00171 * Offset: 0x14 Data Flash Base Address 00172 * --------------------------------------------------------------------------------------------------- 00173 * |Bits |Field |Descriptions 00174 * | :----: | :----: | :---- | 00175 * |[31:0] |DFBA |Data Flash Base Address 00176 * | | |This register indicates Data Flash start address. It is a read only register. 00177 * | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1 00178 * | | |This register is valid when DFEN (CONFIG0[0]) =0 . 00179 * @var FMC_T::ISPSTS 00180 * Offset: 0x40 ISP Status Register 00181 * --------------------------------------------------------------------------------------------------- 00182 * |Bits |Field |Descriptions 00183 * | :----: | :----: | :---- | 00184 * |[0] |ISPBUSY |ISP Busy Flag (Read Only) 00185 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 00186 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). 00187 * | | |0 = ISP operation is finished. 00188 * | | |1 = ISP is progressed. 00189 * |[2:1] |CBS |Boot Selection of CONFIG (Read Only) 00190 * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. 00191 * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1. 00192 * | | |00 = LDROM with IAP mode. 00193 * | | |01 = LDROM without IAP mode. 00194 * | | |10 = APROM with IAP mode. 00195 * | | |11 = APROM without IAP mode. 00196 * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only) 00197 * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened 00198 * | | |0 = Booting from Boot Loader. 00199 * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting) 00200 * |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only) 00201 * | | |This bit is set if flash access cycle auto-tuning function is disabled 00202 * | | |The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready. 00203 * | | |0 = Flash access cycle auto-tuning is enabled. 00204 * | | |1 = Flash access cycle auto-tuning is disabled. 00205 * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only) 00206 * | | |This bit is set if data is mismatched at ISP programming verification 00207 * | | |This bit is clear by performing ISP flash erase or ISP read CID operation 00208 * | | |0 = Flash Program is success. 00209 * | | |1 = Flash Program is fail. Program data is different with data in the flash memory 00210 * |[6] |ISPFF |ISP Fail Flag (Write Protect) 00211 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] 00212 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: 00213 * | | |(1) APROM writes to itself if APUEN is set to 0. 00214 * | | |(2) LDROM writes to itself if LDUEN is set to 0. 00215 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. 00216 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 00217 * | | |(5) SPROM is programmed at SPROM secured mode. 00218 * | | |(6) Page Erase command at LOCK mode with ICE connection 00219 * | | |(7) Erase or Program command at brown-out detected 00220 * | | |(8) Destination address is illegal, such as over an available range. 00221 * | | |(9) Invalid ISP commands 00222 * | | |(10) Vector address is mapping to SPROM region. 00223 * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1 00224 * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 00225 * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1 00226 * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. 00227 * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. 00228 * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A 00229 * | | |(17) Read any content of boot loader with ICE connection 00230 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00231 * |[7] |ALLONE |Flash All-one Verification Flag 00232 * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1 00233 * | | |0 = All of flash bits are 1 after "Run Flash All-One Verification" complete. 00234 * | | |1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete. 00235 * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only) 00236 * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9u2019h000} ~ {VECMAP[14:0], 9u2019h1FF} 00237 * |[31] |SCODE |Security Code Active Flag 00238 * | | |This bit is set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active; this bit is clear by SPROM page erase operation. 00239 * | | |0 = Secured code is inactive. 00240 * | | |1 = Secured code is active. 00241 * @var FMC_T::CYCCTL 00242 * Offset: 0x4C Flash Access Cycle Control Register 00243 * --------------------------------------------------------------------------------------------------- 00244 * |Bits |Field |Descriptions 00245 * | :----: | :----: | :---- | 00246 * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect) 00247 * | | |0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;. 00248 * | | |The HCLK working frequency range range is<27MHz 00249 * | | |0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;. 00250 * | | | The optimized HCLK working frequency range is 27~54 MHz 00251 * | | |0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;. 00252 * | | |The optimized HCLK working frequency range is 54~81MHz 00253 * | | |0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;. 00254 * | | | The optimized HCLK working frequency range is81~108MHz 00255 * | | |0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;. 00256 * | | |The optimized HCLK working frequency range is 108~135MHz 00257 * | | |0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;. 00258 * | | | The optimized HCLK working frequency range is 135~162MHz 00259 * | | |0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;. 00260 * | | | The optimized HCLK working frequency range is 162~192MHz 00261 * | | |1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;. 00262 * | | |The optimized HCLK working frequency range is >192MHz 00263 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00264 * @var FMC_T::KPKEY0 00265 * Offset: 0x50 KPROM KEY0 Data Register 00266 * --------------------------------------------------------------------------------------------------- 00267 * |Bits |Field |Descriptions 00268 * | :----: | :----: | :---- | 00269 * |[31:0] |KPKEY0 |KPROM KEY0 Data (Write Only) 00270 * | | |Write KPKEY0 data to this register before KEY Comparison operation. 00271 * @var FMC_T::KPKEY1 00272 * Offset: 0x54 KPROM KEY1 Data Register 00273 * --------------------------------------------------------------------------------------------------- 00274 * |Bits |Field |Descriptions 00275 * | :----: | :----: | :---- | 00276 * |[31:0] |KPKEY1 |KPROM KEY1 Data (Write Only) 00277 * | | |Write KPKEY1 data to this register before KEY Comparison operation. 00278 * @var FMC_T::KPKEY2 00279 * Offset: 0x58 KPROM KEY2 Data Register 00280 * --------------------------------------------------------------------------------------------------- 00281 * |Bits |Field |Descriptions 00282 * | :----: | :----: | :---- | 00283 * |[31:0] |KPKEY2 |KPROM KEY2 Data (Write Only) 00284 * | | |Write KPKEY2 data to this register before KEY Comparison operation. 00285 * @var FMC_T::KPKEYTRG 00286 * Offset: 0x5C KPROM KEY Comparison Trigger Control Register 00287 * --------------------------------------------------------------------------------------------------- 00288 * |Bits |Field |Descriptions 00289 * | :----: | :----: | :---- | 00290 * |[0] |KPKEYGO |KPROM KEY Comparison Start Trigger (Write Protection) 00291 * | | |Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished 00292 * | | |This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0. 00293 * | | |0 = KEY comparison operation is finished. 00294 * | | |1 = KEY comparison is progressed. 00295 * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. 00296 * |[1] |TCEN |Timeout Counting Enable (Write Protection) 00297 * | | |0 = Timeout counting is disabled. 00298 * | | |1 = Timeout counting is enabled if input key is matched after key comparison finish. 00299 * | | |10 minutes is at least for timeout, and average is about 20 minutes. 00300 * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. 00301 * @var FMC_T::KPKEYSTS 00302 * Offset: 0x60 KPROM KEY Comparison Status Register 00303 * --------------------------------------------------------------------------------------------------- 00304 * |Bits |Field |Descriptions 00305 * | :----: | :----: | :---- | 00306 * |[0] |KEYBUSY |KEY Comparison Busy (Read Only) 00307 * | | |0 = KEY comparison is finished. 00308 * | | |1 = KEY comparison is busy. 00309 * |[1] |KEYLOCK |KEY LOCK Flag 00310 * | | |This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection 00311 * | | |After Mass Erase operation, users must reset or power on /off to clear this bit to 0 00312 * | | |This bit also can be set to 1 while 00313 * | | | - CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or 00314 * | | | - KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or 00315 * | | | - KEYENROM is programmed a non-0xFF value or 00316 * | | | - Timeout event or 00317 * | | | - FORBID(FMC_KPKEYSTS[3]) is 1 00318 * | | |0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection. 00319 * | | |1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection. 00320 * | | |SPROM write protect is depended on SPFLAG. 00321 * | | |CONFIG write protect is depended on CFGFLAG 00322 * |[2] |KEYMATCH |KEY Match Flag (Read Only) 00323 * | | |This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched 00324 * | | |This bit is also cleared to 0 while 00325 * | | | - CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or 00326 * | | | - Timeout event or 00327 * | | | - KPROM is erased or 00328 * | | | - KEYENROM is programmed to a non-0xFF value. 00329 * | | | - Chip is in power down mode. 00330 * | | |0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting. 00331 * | | |1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting. 00332 * |[3] |FORBID |KEY Comparison Forbidden Flag (Read Only) 00333 * | | |This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]). 00334 * | | |0 = KEY comparison is not forbidden. 00335 * | | |1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger. 00336 * |[4] |KEYFLAG |KEY Protection Enabled Flag (Read Only) 00337 * | | |This bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset 00338 * | | |This bit is cleared to 0 by hardware while KPROM is erased 00339 * | | |This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value. 00340 * | | |0 = Security Key protection is disabled. 00341 * | | |1 = Security Key protection is enabled. 00342 * |[5] |CFGFLAG |CONFIG Write-protection Enabled Flag (Read Only) 00343 * | | |This bit is set while the KEYENROM [0] is 0 at power-on or reset 00344 * | | |This bit is cleared to 0 by hardware while KPROM is erased 00345 * | | |This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0. 00346 * | | |0 = CONFIG write-protection is disabled. 00347 * | | |1 = CONFIG write-protection is enabled. 00348 * |[6] |SPFLAG |SPROM Write-protection Enabled Flag (Read Only) 00349 * | | |This bit is set while the KEYENROM [1] is 0 at power-on or reset 00350 * | | |This bit is cleared to 0 by hardware while KPROM is erased 00351 * | | |This bit is set to 1 by hardware while KEYENROM[1] is programmed to 0. 00352 * | | |0 = SPROM write-protection is disabled. 00353 * | | |1 = SPROM write-protection is enabled. 00354 * @var FMC_T::KPKEYCNT 00355 * Offset: 0x64 KPROM KEY-Unmatched Counting Register 00356 * --------------------------------------------------------------------------------------------------- 00357 * |Bits |Field |Descriptions 00358 * | :----: | :----: | :---- | 00359 * |[5:0] |KPKECNT |Error Key Entry Counter at Each Power-on (Read Only) 00360 * | | |KPKECNT is increased when entry keys is wrong in Security Key protection 00361 * | | |KPKECNT is cleared to 0 if key comparison is matched or system power-on. 00362 * |[13:8] |KPKEMAX |Maximum Number for Error Key Entry at Each Power-on (Read Only) 00363 * | | |KPKEMAX is the maximum error key entry number at each power-on 00364 * | | |When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated 00365 * | | |KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting 00366 * | | |The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX. 00367 * @var FMC_T::KPCNT 00368 * Offset: 0x68 KPROM KEY-Unmatched Power-On Counting Register 00369 * --------------------------------------------------------------------------------------------------- 00370 * |Bits |Field |Descriptions 00371 * | :----: | :----: | :---- | 00372 * |[3:0] |KPCNT |Power-on Counter for Error Key Entry(Read Only) 00373 * | | |KPCNT is the power-on counting for error key entry in Security Key protection 00374 * | | |KPCNT is cleared to 0 if key comparison is matched. 00375 * |[11:8] |KPMAX |Power-on Maximum Number for Error Key Entry (Read Only) 00376 * | | |KPMAX is the power-on maximum number for error key entry 00377 * | | |When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated 00378 * | | |KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting 00379 * | | |The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX 00380 * @var FMC_T::MPDAT0 00381 * Offset: 0x80 ISP Data0 Register 00382 * --------------------------------------------------------------------------------------------------- 00383 * |Bits |Field |Descriptions 00384 * | :----: | :----: | :---- | 00385 * |[31:0] |ISPDAT0 |ISP Data 0 00386 * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data 00387 * @var FMC_T::MPDAT1 00388 * Offset: 0x84 ISP Data1 Register 00389 * --------------------------------------------------------------------------------------------------- 00390 * |Bits |Field |Descriptions 00391 * | :----: | :----: | :---- | 00392 * |[31:0] |ISPDAT1 |ISP Data 1 00393 * | | |This register is the second 32-bit data for 64-bit/multi-word programming. 00394 * @var FMC_T::MPDAT2 00395 * Offset: 0x88 ISP Data2 Register 00396 * --------------------------------------------------------------------------------------------------- 00397 * |Bits |Field |Descriptions 00398 * | :----: | :----: | :---- | 00399 * |[31:0] |ISPDAT2 |ISP Data 2 00400 * | | |This register is the third 32-bit data for multi-word programming. 00401 * @var FMC_T::MPDAT3 00402 * Offset: 0x8C ISP Data3 Register 00403 * --------------------------------------------------------------------------------------------------- 00404 * |Bits |Field |Descriptions 00405 * | :----: | :----: | :---- | 00406 * |[31:0] |ISPDAT3 |ISP Data 3 00407 * | | |This register is the fourth 32-bit data for multi-word programming. 00408 * @var FMC_T::MPSTS 00409 * Offset: 0xC0 ISP Multi-Program Status Register 00410 * --------------------------------------------------------------------------------------------------- 00411 * |Bits |Field |Descriptions 00412 * | :----: | :----: | :---- | 00413 * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only) 00414 * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished. 00415 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). 00416 * | | |0 = ISP Multi-Word program operation is finished. 00417 * | | |1 = ISP Multi-Word program operation is progressed. 00418 * |[1] |PPGO |ISP Multi-program Status (Read Only) 00419 * | | |0 = ISP multi-word program operation is not active. 00420 * | | |1 = ISP multi-word program operation is in progress. 00421 * |[2] |ISPFF |ISP Fail Flag (Read Only) 00422 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] 00423 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: 00424 * | | |(1) APROM writes to itself if APUEN is set to 0. 00425 * | | |(2) LDROM writes to itself if LDUEN is set to 0. 00426 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. 00427 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 00428 * | | |(5) SPROM is programmed at SPROM secured mode. 00429 * | | |(6) Page Erase command at LOCK mode with ICE connection 00430 * | | |(7) Erase or Program command at brown-out detected 00431 * | | |(8) Destination address is illegal, such as over an available range. 00432 * | | |(9) Invalid ISP commands 00433 * | | |(10) Vector address is mapping to SPROM region. 00434 * |[4] |D0 |ISP DATA 0 Flag (Read Only) 00435 * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete. 00436 * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete. 00437 * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete. 00438 * |[5] |D1 |ISP DATA 1 Flag (Read Only) 00439 * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete. 00440 * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete. 00441 * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete. 00442 * |[6] |D2 |ISP DATA 2 Flag (Read Only) 00443 * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete. 00444 * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete. 00445 * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete. 00446 * |[7] |D3 |ISP DATA 3 Flag (Read Only) 00447 * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete. 00448 * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete. 00449 * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete. 00450 * @var FMC_T::MPADDR 00451 * Offset: 0xC4 ISP Multi-Program Address Register 00452 * --------------------------------------------------------------------------------------------------- 00453 * |Bits |Field |Descriptions 00454 * | :----: | :----: | :---- | 00455 * |[31:0] |MPADDR |ISP Multi-word Program Address 00456 * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. 00457 * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete. 00458 */ 00459 __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */ 00460 __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */ 00461 __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */ 00462 __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */ 00463 __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */ 00464 __I uint32_t DFBA; /*!< [0x0014] Data Flash Base Address */ 00465 /// @cond HIDDEN_SYMBOLS 00466 __I uint32_t RESERVE0[10]; 00467 /// @endcond //HIDDEN_SYMBOLS 00468 __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */ 00469 /// @cond HIDDEN_SYMBOLS 00470 __I uint32_t RESERVE1[2]; 00471 /// @endcond //HIDDEN_SYMBOLS 00472 __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */ 00473 __O uint32_t KPKEY0; /*!< [0x0050] KPROM KEY0 Data Register */ 00474 __O uint32_t KPKEY1; /*!< [0x0054] KPROM KEY1 Data Register */ 00475 __O uint32_t KPKEY2; /*!< [0x0058] KPROM KEY2 Data Register */ 00476 __IO uint32_t KPKEYTRG; /*!< [0x005c] KPROM KEY Comparison Trigger Control Register */ 00477 __IO uint32_t KPKEYSTS; /*!< [0x0060] KPROM KEY Comparison Status Register */ 00478 __I uint32_t KPKEYCNT; /*!< [0x0064] KPROM KEY-Unmatched Counting Register */ 00479 __I uint32_t KPCNT; /*!< [0x0068] KPROM KEY-Unmatched Power-On Counting Register */ 00480 /// @cond HIDDEN_SYMBOLS 00481 __I uint32_t RESERVE2[5]; 00482 /// @endcond //HIDDEN_SYMBOLS 00483 __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */ 00484 __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */ 00485 __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */ 00486 __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */ 00487 /// @cond HIDDEN_SYMBOLS 00488 __I uint32_t RESERVE3[12]; 00489 /// @endcond //HIDDEN_SYMBOLS 00490 __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */ 00491 __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */ 00492 00493 } FMC_T; 00494 00495 /** 00496 @addtogroup FMC_CONST FMC Bit Field Definition 00497 Constant Definitions for FMC Controller 00498 @{ */ 00499 00500 #define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */ 00501 #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */ 00502 00503 #define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */ 00504 #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */ 00505 00506 #define FMC_ISPCTL_SPUEN_Pos (2) /*!< FMC_T::ISPCTL: SPUEN Position */ 00507 #define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos) /*!< FMC_T::ISPCTL: SPUEN Mask */ 00508 00509 #define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */ 00510 #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */ 00511 00512 #define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */ 00513 #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */ 00514 00515 #define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */ 00516 #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */ 00517 00518 #define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */ 00519 #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */ 00520 00521 #define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */ 00522 #define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */ 00523 00524 #define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */ 00525 #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */ 00526 00527 #define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */ 00528 #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */ 00529 00530 #define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */ 00531 #define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */ 00532 00533 #define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */ 00534 #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */ 00535 00536 #define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */ 00537 #define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */ 00538 00539 #define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */ 00540 #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */ 00541 00542 #define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */ 00543 #define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */ 00544 00545 #define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */ 00546 #define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */ 00547 00548 #define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */ 00549 #define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */ 00550 00551 #define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */ 00552 #define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */ 00553 00554 #define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */ 00555 #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */ 00556 00557 #define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */ 00558 #define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */ 00559 00560 #define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */ 00561 #define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */ 00562 00563 #define FMC_ISPSTS_SCODE_Pos (31) /*!< FMC_T::ISPSTS: SCODE Position */ 00564 #define FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos) /*!< FMC_T::ISPSTS: SCODE Mask */ 00565 00566 #define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */ 00567 #define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */ 00568 00569 #define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */ 00570 #define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */ 00571 00572 #define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */ 00573 #define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */ 00574 00575 #define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */ 00576 #define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */ 00577 00578 #define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */ 00579 #define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */ 00580 00581 #define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */ 00582 #define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */ 00583 00584 #define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */ 00585 #define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */ 00586 00587 #define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */ 00588 #define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */ 00589 00590 #define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */ 00591 #define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */ 00592 00593 #define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */ 00594 #define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */ 00595 00596 #define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */ 00597 #define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */ 00598 00599 #define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */ 00600 #define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */ 00601 00602 #define FMC_KPKEYSTS_SPFLAG_Pos (6) /*!< FMC_T::KPKEYSTS: SPFLAG Position */ 00603 #define FMC_KPKEYSTS_SPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SPFLAG Mask */ 00604 00605 #define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */ 00606 #define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */ 00607 00608 #define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */ 00609 #define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */ 00610 00611 #define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */ 00612 #define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */ 00613 00614 #define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */ 00615 #define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */ 00616 00617 #define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */ 00618 #define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */ 00619 00620 #define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */ 00621 #define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */ 00622 00623 #define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */ 00624 #define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */ 00625 00626 #define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */ 00627 #define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */ 00628 00629 #define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */ 00630 #define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */ 00631 00632 #define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */ 00633 #define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */ 00634 00635 #define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */ 00636 #define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */ 00637 00638 #define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */ 00639 #define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */ 00640 00641 #define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */ 00642 #define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */ 00643 00644 #define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */ 00645 #define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */ 00646 00647 #define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */ 00648 #define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */ 00649 00650 #define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */ 00651 #define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */ 00652 00653 /**@}*/ /* FMC_CONST */ 00654 /**@}*/ /* end of FMC register group */ 00655 /**@}*/ /* end of REGISTER group */ 00656 00657 #if defined ( __CC_ARM ) 00658 #pragma no_anon_unions 00659 #endif 00660 00661 #endif /* __FMC_REG_H__ */
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