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m480_clk_reg.h
00001 /**************************************************************************//** 00002 * @file clk_reg.h 00003 * @version V1.00 00004 * @brief CLK register definition header file 00005 * 00006 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. 00007 * 00008 * Redistribution and use in source and binary forms, with or without modification, 00009 * are permitted provided that the following conditions are met: 00010 * 1. Redistributions of source code must retain the above copyright notice, 00011 * this list of conditions and the following disclaimer. 00012 * 2. Redistributions in binary form must reproduce the above copyright notice, 00013 * this list of conditions and the following disclaimer in the documentation 00014 * and/or other materials provided with the distribution. 00015 * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors 00016 * may be used to endorse or promote products derived from this software 00017 * without specific prior written permission. 00018 * 00019 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00020 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00021 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00022 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00023 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00024 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00025 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00026 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00027 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00028 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00029 *****************************************************************************/ 00030 #ifndef __CLK_REG_H__ 00031 #define __CLK_REG_H__ 00032 00033 #if defined ( __CC_ARM ) 00034 #pragma anon_unions 00035 #endif 00036 00037 /** 00038 @addtogroup REGISTER Control Register 00039 @{ 00040 */ 00041 00042 /** 00043 @addtogroup CLK System Clock Controller(CLK) 00044 Memory Mapped Structure for CLK Controller 00045 @{ */ 00046 00047 typedef struct { 00048 00049 00050 /** 00051 * @var CLK_T::PWRCTL 00052 * Offset: 0x00 System Power-down Control Register 00053 * --------------------------------------------------------------------------------------------------- 00054 * |Bits |Field |Descriptions 00055 * | :----: | :----: | :---- | 00056 * |[0] |HXTEN |HXT Enable Bit (Write Protect) 00057 * | | |The bit default value is set by flash controller user configuration register CONFIG0 [26] 00058 * | | |When the default clock source is from HXT, this bit is set to 1 automatically. 00059 * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled. 00060 * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled. 00061 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00062 * |[1] |LXTEN |LXT Enable Bit (Write Protect) 00063 * | | |0 = 32.768 kHz external low speed crystal (LXT) Disabled. 00064 * | | |1 = 32.768 kHz external low speed crystal (LXT) Enabled. 00065 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00066 * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) 00067 * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled. 00068 * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled. 00069 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00070 * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) 00071 * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. 00072 * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. 00073 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00074 * |[4] |PDWKDLY |Enable the Wake-up Delay Counter (Write Protect) 00075 * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. 00076 * | | |The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 12 MHz internal high speed RC oscillator (HIRC). 00077 * | | |0 = Clock cycles delay Disabled. 00078 * | | |1 = Clock cycles delay Enabled. 00079 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00080 * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) 00081 * | | |0 = Power-down mode wake-up interrupt Disabled. 00082 * | | |1 = Power-down mode wake-up interrupt Enabled. 00083 * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high. 00084 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 00085 * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status 00086 * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode. 00087 * | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter. 00088 * | | |Note1: Write 1 to clear the bit to 0. 00089 * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. 00090 * |[7] |PDEN |System Power-down Enable (Write Protect) 00091 * | | |When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. 00092 * | | |When chip wakes up from Power-down mode, this bit is auto cleared 00093 * | | |Users need to set this bit again for next Power-down. 00094 * | | |In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. 00095 * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection 00096 * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. 00097 * | | |0 = Chip will not enter Power-down mode after CPU sleep command WFI. 00098 * | | |1 = Chip enters Power-down mode after CPU sleep command WFI. 00099 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00100 * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect) 00101 * | | |This is a protected register. Please refer to open lock sequence to program it. 00102 * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally 00103 * | | |If gain control is enabled, crystal will consume more power than gain control off. 00104 * | | |00 = HXT frequency is lower than from 8 MHz. 00105 * | | |01 = HXT frequency is from 8 MHz to 12 MHz. 00106 * | | |10 = HXT frequency is from 12 MHz to 16 MHz. 00107 * | | |11 = HXT frequency is higher than 16 MHz. 00108 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00109 * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect) 00110 * | | |This is a protected register. Please refer to open lock sequence to program it. 00111 * | | |0 = Select INV type. 00112 * | | |1 = Select GM type. 00113 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00114 * |[13] |HXTTBEN |HXT Crystal TURBO Mode (Write Protect) 00115 * | | |This is a protected register. Please refer to open lock sequence to program it. 00116 * | | |0 = HXT Crystal TURBO mode disabled. 00117 * | | |1 = HXT Crystal TURBO mode enabled. 00118 * |[17:16] |HIRCSTBS |HIRC Stable Count Select (Write Protect) 00119 * | | |00 = HIRC stable count is 64 clocks. 00120 * | | |01 = HIRC stable count is 24 clocks. 00121 * | | |others = Reserved. 00122 * @var CLK_T::AHBCLK 00123 * Offset: 0x04 AHB Devices Clock Enable Control Register 00124 * --------------------------------------------------------------------------------------------------- 00125 * |Bits |Field |Descriptions 00126 * | :----: | :----: | :---- | 00127 * |[1] |PDMACKEN |PDMA Controller Clock Enable Bit 00128 * | | |0 = PDMA peripheral clock Disabled. 00129 * | | |1 = PDMA peripheral clock Enabled. 00130 * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit 00131 * | | |0 = Flash ISP peripheral clock Disabled. 00132 * | | |1 = Flash ISP peripheral clock Enabled. 00133 * |[3] |EBICKEN |EBI Controller Clock Enable Bit 00134 * | | |0 = EBI peripheral clock Disabled. 00135 * | | |1 = EBI peripheral clock Enabled. 00136 * |[5] |EMACCKEN |Ethernet Controller Clock Enable Bit 00137 * | | |0 = Ethernet Controller engine clock Disabled. 00138 * | | |1 = Ethernet Controller engine clock Enabled. 00139 * |[6] |SDH0CKEN |SD0 Controller Clock Enable Bit 00140 * | | |0 = SD0 engine clock Disabled. 00141 * | | |1 = SD0 engine clock Enabled. 00142 * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit 00143 * | | |0 = CRC peripheral clock Disabled. 00144 * | | |1 = CRC peripheral clock Enabled. 00145 * |[10] |HSUSBDCKEN|HSUSB Device Clock Enable Bit 00146 * | | |0 = HSUSB device controller's clock Disabled. 00147 * | | |1 = HSUSB device controller's clock Enabled. 00148 * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit 00149 * | | |0 = Cryptographic Accelerator clock Disabled. 00150 * | | |1 = Cryptographic Accelerator clock Enabled. 00151 * |[14] |SPIMCKEN |SPIM Controller Clock Enable Bit 00152 * | | |0 = SPIM controller clock Disabled. 00153 * | | |1 = SPIM controller clock Enabled. 00154 * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode 00155 * | | |0 = FMC clock Disabled when chip is under IDLE mode. 00156 * | | |1 = FMC clock Enabled when chip is under IDLE mode. 00157 * |[16] |USBHCKEN |USB HOST Controller Clock Enable Bit 00158 * | | |0 = USB HOST peripheral clock Disabled. 00159 * | | |1 = USB HOST peripheral clock Enabled. 00160 * |[17] |SDH1CKEN |SD1 Controller Clock Enable Bit 00161 * | | |0 = SD1 engine clock Disabled. 00162 * | | |1 = SD1 engine clock Enabled. 00163 * @var CLK_T::APBCLK0 00164 * Offset: 0x08 APB Devices Clock Enable Control Register 0 00165 * --------------------------------------------------------------------------------------------------- 00166 * |Bits |Field |Descriptions 00167 * | :----: | :----: | :---- | 00168 * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect) 00169 * | | |0 = Watchdog timer clock Disabled. 00170 * | | |1 = Watchdog timer clock Enabled. 00171 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00172 * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit 00173 * | | |This bit is used to control the RTC APB clock only 00174 * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]) 00175 * | | |It can be selected to 32.768 kHz external low speed crystal or 10 kHz internal low speed RC oscillator (LIRC). 00176 * | | |0 = RTC clock Disabled. 00177 * | | |1 = RTC clock Enabled. 00178 * |[2] |TMR0CKEN |Timer0 Clock Enable Bit 00179 * | | |0 = Timer0 clock Disabled. 00180 * | | |1 = Timer0 clock Enabled. 00181 * |[3] |TMR1CKEN |Timer1 Clock Enable Bit 00182 * | | |0 = Timer1 clock Disabled. 00183 * | | |1 = Timer1 clock Enabled. 00184 * |[4] |TMR2CKEN |Timer2 Clock Enable Bit 00185 * | | |0 = Timer2 clock Disabled. 00186 * | | |1 = Timer2 clock Enabled. 00187 * |[5] |TMR3CKEN |Timer3 Clock Enable Bit 00188 * | | |0 = Timer3 clock Disabled. 00189 * | | |1 = Timer3 clock Enabled. 00190 * |[6] |CLKOCKEN |CLKO Clock Enable Bit 00191 * | | |0 = CLKO clock Disabled. 00192 * | | |1 = CLKO clock Enabled. 00193 * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit 00194 * | | |0 = Analog comparator 0/1 clock Disabled. 00195 * | | |1 = Analog comparator 0/1 clock Enabled. 00196 * |[8] |I2C0CKEN |I2C0 Clock Enable Bit 00197 * | | |0 = I2C0 clock Disabled. 00198 * | | |1 = I2C0 clock Enabled. 00199 * |[9] |I2C1CKEN |I2C1 Clock Enable Bit 00200 * | | |0 = I2C1 clock Disabled. 00201 * | | |1 = I2C1 clock Enabled. 00202 * |[10] |I2C2CKEN |I2C2 Clock Enable Bit 00203 * | | |0 = I2C2 clock Disabled. 00204 * | | |1 = I2C2 clock Enabled. 00205 * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit 00206 * | | |0 = QSPI0 clock Disabled. 00207 * | | |1 = QSPI0 clock Enabled. 00208 * |[13] |SPI0CKEN |SPI0 Clock Enable Bit 00209 * | | |0 = SPI0 clock Disabled. 00210 * | | |1 = SPI0 clock Enabled. 00211 * |[14] |SPI1CKEN |SPI1 Clock Enable Bit 00212 * | | |0 = SPI1 clock Disabled. 00213 * | | |1 = SPI1 clock Enabled. 00214 * |[15] |SPI2CKEN |SPI2 Clock Enable Bit 00215 * | | |0 = SPI2 clock Disabled. 00216 * | | |1 = SPI2 clock Enabled. 00217 * |[16] |UART0CKEN |UART0 Clock Enable Bit 00218 * | | |0 = UART0 clock Disabled. 00219 * | | |1 = UART0 clock Enabled. 00220 * |[17] |UART1CKEN |UART1 Clock Enable Bit 00221 * | | |0 = UART1 clock Disabled. 00222 * | | |1 = UART1 clock Enabled. 00223 * |[18] |UART2CKEN |UART2 Clock Enable Bit 00224 * | | |0 = UART2 clock Disabled. 00225 * | | |1 = UART2 clock Enabled. 00226 * |[19] |UART3CKEN |UART3 Clock Enable Bit 00227 * | | |0 = UART3 clock Disabled. 00228 * | | |1 = UART3 clock Enabled. 00229 * |[20] |UART4CKEN |UART4 Clock Enable Bit 00230 * | | |0 = UART4 clock Disabled. 00231 * | | |1 = UART4 clock Enabled. 00232 * |[21] |UART5CKEN |UART5 Clock Enable Bit 00233 * | | |0 = UART5 clock Disabled. 00234 * | | |1 = UART5 clock Enabled. 00235 * |[24] |CAN0CKEN |CAN0 Clock Enable Bit 00236 * | | |0 = CAN0 clock Disabled. 00237 * | | |1 = CAN0 clock Enabled. 00238 * |[25] |CAN1CKEN |CAN1 Clock Enable Bit 00239 * | | |0 = CAN1 clock Disabled. 00240 * | | |1 = CAN1 clock Enabled. 00241 * |[26] |OTGCKEN |USB OTG Clock Enable Bit 00242 * | | |0 = USB OTG clock Disabled. 00243 * | | |1 = USB OTG clock Enabled. 00244 * |[27] |USBDCKEN |USB Device Clock Enable Bit 00245 * | | |0 = USB Device clock Disabled. 00246 * | | |1 = USB Device clock Enabled. 00247 * |[28] |EADCCKEN |Enhanced Analog-digital-converter (EADC) Clock Enable Bit 00248 * | | |0 = EADC clock Disabled. 00249 * | | |1 = EADC clock Enabled. 00250 * |[29] |I2S0CKEN |I2S0 Clock Enable Bit 00251 * | | |0 = I2S0 Clock Disabled. 00252 * | | |1 = I2S0 Clock Enabled. 00253 * |[30] |HSOTGCKEN |HSUSB OTG Clock Enable Bit 00254 * | | |0 = HSUSB OTG clock Disabled. 00255 * | | |1 = HSUSB OTG clock Enabled. 00256 * @var CLK_T::APBCLK1 00257 * Offset: 0x0C APB Devices Clock Enable Control Register 1 00258 * --------------------------------------------------------------------------------------------------- 00259 * |Bits |Field |Descriptions 00260 * | :----: | :----: | :---- | 00261 * |[0] |SC0CKEN |SC0 Clock Enable Bit 00262 * | | |0 = SC0 clock Disabled. 00263 * | | |1 = SC0 clock Enabled. 00264 * |[1] |SC1CKEN |SC1 Clock Enable Bit 00265 * | | |0 = SC1 clock Disabled. 00266 * | | |1 = SC1 clock Enabled. 00267 * |[2] |SC2CKEN |SC2 Clock Enable Bit 00268 * | | |0 = SC2 clock Disabled. 00269 * | | |1 = SC2 clock Enabled. 00270 * |[6] |SPI3CKEN |SPI3 Clock Enable Bit 00271 * | | |0 = SPI3 clock Disabled. 00272 * | | |1 = SPI3 clock Enabled. 00273 * |[8] |USCI0CKEN |USCI0 Clock Enable Bit 00274 * | | |0 = USCI0 clock Disabled. 00275 * | | |1 = USCI0 clock Enabled. 00276 * |[9] |USCI1CKEN |USCI1 Clock Enable Bit 00277 * | | |0 = USCI1 clock Disabled. 00278 * | | |1 = USCI1 clock Enabled. 00279 * |[12] |DACCKEN |DAC Clock Enable Bit 00280 * | | |0 = DAC clock Disabled. 00281 * | | |1 = DAC clock Enabled. 00282 * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit 00283 * | | |0 = EPWM0 clock Disabled. 00284 * | | |1 = EPWM0 clock Enabled. 00285 * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit 00286 * | | |0 = EPWM1 clock Disabled. 00287 * | | |1 = EPWM1 clock Enabled. 00288 * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit 00289 * | | |0 = BPWM0 clock Disabled. 00290 * | | |1 = BPWM0 clock Enabled. 00291 * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit 00292 * | | |0 = BPWM1 clock Disabled. 00293 * | | |1 = BPWM1 clock Enabled. 00294 * |[22] |QEI0CKEN |QEI0 Clock Enable Bit 00295 * | | |0 = QEI0 clock Disabled. 00296 * | | |1 = QEI0 clock Enabled. 00297 * |[23] |QEI1CKEN |QEI1 Clock Enable Bit 00298 * | | |0 = QEI1 clock Disabled. 00299 * | | |1 = QEI1 clock Enabled. 00300 * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit 00301 * | | |0 = ECAP0 clock Disabled. 00302 * | | |1 = ECAP0 clock Enabled. 00303 * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit 00304 * | | |0 = ECAP1 clock Disabled. 00305 * | | |1 = ECAP1 clock Enabled. 00306 * |[30] |OPACKEN |OP Amplifier (OPA) Clock Enable Bit 00307 * | | |0 = OPA clock Disabled. 00308 * | | |1 = OPA clock Enabled. 00309 * @var CLK_T::CLKSEL0 00310 * Offset: 0x10 Clock Source Select Control Register 0 00311 * --------------------------------------------------------------------------------------------------- 00312 * |Bits |Field |Descriptions 00313 * | :----: | :----: | :---- | 00314 * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect) 00315 * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. 00316 * | | |The default value is reloaded from the value of CFOSC (CONFIG0[26]) in user configuration register of Flash controller by any reset 00317 * | | |Therefore the default value is either 000b or 111b. 00318 * | | |000 = Clock source from HXT. 00319 * | | |001 = Clock source from LXT. 00320 * | | |010 = Clock source from PLL. 00321 * | | |011 = Clock source from LIRC. 00322 * | | |111 = Clock source from HIRC. 00323 * | | |Other = Reserved. 00324 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00325 * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect) 00326 * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. 00327 * | | |000 = Clock source from HXT. 00328 * | | |001 = Clock source from LXT. 00329 * | | |010 = Clock source from HXT/2. 00330 * | | |011 = Clock source from HCLK/2. 00331 * | | |111 = Clock source from HIRC/2. 00332 * | | |Note: if SysTick clock source is not from HCLK (i.e 00333 * | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2. 00334 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00335 * |[21:20] |SDH0SEL |SD0 Engine Clock Source Selection (Write Protect) 00336 * | | |00 = Clock source from HXT clock. 00337 * | | |01 = Clock source from PLL clock. 00338 * | | |10 = Clock source from HCLK. 00339 * | | |11 = Clock source from HIRC clock. 00340 * |[23:22] |SDH1SEL |SD1 Engine Clock Source Selection (Write Protect) 00341 * | | |00 = Clock source from HXT clock. 00342 * | | |01 = Clock source from PLL clock. 00343 * | | |10 = Clock source from HCLK. 00344 * | | |11 = Clock source from HIRC clock. 00345 * @var CLK_T::CLKSEL1 00346 * Offset: 0x14 Clock Source Select Control Register 1 00347 * --------------------------------------------------------------------------------------------------- 00348 * |Bits |Field |Descriptions 00349 * | :----: | :----: | :---- | 00350 * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect) 00351 * | | |00 = Reserved. 00352 * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 00353 * | | |10 = Clock source from HCLK/2048. 00354 * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 00355 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00356 * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection 00357 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00358 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 00359 * | | |010 = Clock source from PCLK0. 00360 * | | |011 = Clock source from external clock TM0 pin. 00361 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 00362 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00363 * | | |Others = Reserved. 00364 * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection 00365 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00366 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 00367 * | | |010 = Clock source from PCLK0. 00368 * | | |011 = Clock source from external clock TM1 pin. 00369 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 00370 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00371 * | | |Others = Reserved. 00372 * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection 00373 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00374 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 00375 * | | |010 = Clock source from PCLK1. 00376 * | | |011 = Clock source from external clock TM2 pin. 00377 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 00378 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00379 * | | |Others = Reserved. 00380 * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection 00381 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00382 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 00383 * | | |010 = Clock source from PCLK1. 00384 * | | |011 = Clock source from external clock TM3 pin. 00385 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 00386 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00387 * | | |Others = Reserved. 00388 * |[25:24] |UART0SEL |UART0 Clock Source Selection 00389 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00390 * | | |01 = Clock source from PLL. 00391 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 00392 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00393 * |[27:26] |UART1SEL |UART1 Clock Source Selection 00394 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00395 * | | |01 = Clock source from PLL. 00396 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 00397 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00398 * |[29:28] |CLKOSEL |Clock Divider Clock Source Selection 00399 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00400 * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 00401 * | | |10 = Clock source from HCLK. 00402 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00403 * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection 00404 * | | |10 = Clock source from HCLK/2048. 00405 * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 00406 * | | |Others = Reserved. 00407 * @var CLK_T::CLKSEL2 00408 * Offset: 0x18 Clock Source Select Control Register 2 00409 * --------------------------------------------------------------------------------------------------- 00410 * |Bits |Field |Descriptions 00411 * | :----: | :----: | :---- | 00412 * |[0] |EPWM0SEL |EPWM0 Clock Source Selection 00413 * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL. 00414 * | | |0 = Clock source from PLL. 00415 * | | |1 = Clock source from PCLK0. 00416 * |[1] |EPWM1SEL |EPWM1 Clock Source Selection 00417 * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL. 00418 * | | |0 = Clock source from PLL. 00419 * | | |1 = Clock source from PCLK1. 00420 * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection 00421 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00422 * | | |01 = Clock source from PLL. 00423 * | | |10 = Clock source from PCLK0. 00424 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00425 * |[5:4] |SPI0SEL |SPI0 Clock Source Selection 00426 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00427 * | | |01 = Clock source from PLL. 00428 * | | |10 = Clock source from PCLK1. 00429 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00430 * |[7:6] |SPI1SEL |SPI1 Clock Source Selection 00431 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00432 * | | |01 = Clock source from PLL. 00433 * | | |10 = Clock source from PCLK0. 00434 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00435 * |[8] |BPWM0SEL |BPWM0 Clock Source Selection 00436 * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL. 00437 * | | |0 = Clock source from PLL. 00438 * | | |1 = Clock source from PCLK0. 00439 * |[9] |BPWM1SEL |BPWM1 Clock Source Selection 00440 * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL. 00441 * | | |0 = Clock source from PLL. 00442 * | | |1 = Clock source from PCLK1. 00443 * |[11:10] |SPI2SEL |SPI2 Clock Source Selection 00444 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00445 * | | |01 = Clock source from PLL. 00446 * | | |10 = Clock source from PCLK1. 00447 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00448 * |[13:12] |SPI3SEL |SPI3 Clock Source Selection 00449 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00450 * | | |01 = Clock source from PLL. 00451 * | | |10 = Clock source from PCLK0. 00452 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00453 * @var CLK_T::CLKSEL3 00454 * Offset: 0x1C Clock Source Select Control Register 3 00455 * --------------------------------------------------------------------------------------------------- 00456 * |Bits |Field |Descriptions 00457 * | :----: | :----: | :---- | 00458 * |[1:0] |SC0SEL |SC0 Clock Source Selection 00459 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00460 * | | |01 = Clock source from PLL. 00461 * | | |10 = Clock source from PCLK0. 00462 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00463 * |[3:2] |SC1SEL |SC0 Clock Source Selection 00464 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00465 * | | |01 = Clock source from PLL. 00466 * | | |10 = Clock source from PCLK1. 00467 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00468 * |[5:4] |SC2SEL |SC2 Clock Source Selection 00469 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00470 * | | |01 = Clock source from PLL. 00471 * | | |10 = Clock source from PCLK0. 00472 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00473 * |[8] |RTCSEL |RTC Clock Source Selection 00474 * | | |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 00475 * | | |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 00476 * |[17:16] |I2S0SEL |I2S0 Clock Source Selection 00477 * | | |00 = Clock source from HXT clock. 00478 * | | |01 = Clock source from PLL clock. 00479 * | | |10 = Clock source from PCLK. 00480 * | | |11 = Clock source from HIRC clock. 00481 * |[25:24] |UART2SEL |UART2 Clock Source Selection 00482 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00483 * | | |01 = Clock source from PLL. 00484 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 00485 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00486 * |[27:26] |UART3SEL |UART3 Clock Source Selection 00487 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00488 * | | |01 = Clock source from PLL. 00489 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 00490 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00491 * |[29:28] |UART4SEL |UART4 Clock Source Selection 00492 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00493 * | | |01 = Clock source from PLL. 00494 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 00495 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00496 * |[31:30] |UART5SEL |UART5 Clock Source Selection 00497 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 00498 * | | |01 = Clock source from PLL. 00499 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 00500 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 00501 * @var CLK_T::CLKDIV0 00502 * Offset: 0x20 Clock Divider Number Register 0 00503 * --------------------------------------------------------------------------------------------------- 00504 * |Bits |Field |Descriptions 00505 * | :----: | :----: | :---- | 00506 * |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source 00507 * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). 00508 * |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock 00509 * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1). 00510 * |[11:8] |UART0DIV |UART0 Clock Divide Number From UART0 Clock Source 00511 * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). 00512 * |[15:12] |UART1DIV |UART1 Clock Divide Number From UART1 Clock Source 00513 * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). 00514 * |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source 00515 * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1). 00516 * |[31:24] |SDH0DIV |SD0 Clock Divide Number From SD0 Clock Source 00517 * | | |SD0 clock frequency = (SD0 clock source frequency) / (SDH0DIV + 1). 00518 * @var CLK_T::CLKDIV1 00519 * Offset: 0x24 Clock Divider Number Register 1 00520 * --------------------------------------------------------------------------------------------------- 00521 * |Bits |Field |Descriptions 00522 * | :----: | :----: | :---- | 00523 * |[7:0] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source 00524 * | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1). 00525 * |[15:8] |SC1DIV |SC1 Clock Divide Number From SC1 Clock Source 00526 * | | |SC1 clock frequency = (SC1 clock source frequency ) / (SC1DIV + 1). 00527 * |[23:16] |SC2DIV |SC2 Clock Divide Number From SC2 Clock Source 00528 * | | |SC2 clock frequency = (SC2 clock source frequency ) / (SC2DIV + 1). 00529 * @var CLK_T::CLKDIV3 00530 * Offset: 0x2C Clock Divider Number Register 3 00531 * --------------------------------------------------------------------------------------------------- 00532 * |Bits |Field |Descriptions 00533 * | :----: | :----: | :---- | 00534 * |[23:16] |EMACDIV |Ethernet Clock Divide Number Form HCLK 00535 * | | |EMAC MDCLK clock frequency = (HCLK) / (EMACDIV + 1). 00536 * |[31:24] |SDH1DIV |SD1 Clock Divide Number From SD1 Clock Source 00537 * | | |SD1 clock frequency = (SD1 clock source frequency) / (SDH1DIV + 1). 00538 * @var CLK_T::CLKDIV4 00539 * Offset: 0x30 Clock Divider Number Register 4 00540 * --------------------------------------------------------------------------------------------------- 00541 * |Bits |Field |Descriptions 00542 * | :----: | :----: | :---- | 00543 * |[3:0] |UART2DIV |UART2 Clock Divide Number From UART2 Clock Source 00544 * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). 00545 * |[7:4] |UART3DIV |UART3 Clock Divide Number From UART3 Clock Source 00546 * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). 00547 * |[11:8] |UART4DIV |UART4 Clock Divide Number From UART4 Clock Source 00548 * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). 00549 * |[15:12] |UART5DIV |UART5 Clock Divide Number From UART5 Clock Source 00550 * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). 00551 * @var CLK_T::PCLKDIV 00552 * Offset: 0x34 APB Clock Divider Register 00553 * --------------------------------------------------------------------------------------------------- 00554 * |Bits |Field |Descriptions 00555 * | :----: | :----: | :---- | 00556 * |[2:0] |APB0DIV |APB0 Clock Divider 00557 * | | |APB0 clock can be divided from HCLK 00558 * | | |000: PCLK0 = HCLK. 00559 * | | |001: PCLK0 = 1/2 HCLK. 00560 * | | |010: PCLK0 = 1/4 HCLK. 00561 * | | |011: PCLK0 = 1/8 HCLK. 00562 * | | |100: PCLK0 = 1/16 HCLK. 00563 * | | |Others: Reserved. 00564 * |[6:4] |APB1DIV |APB1 Clock Divider 00565 * | | |APB1 clock can be divided from HCLK 00566 * | | |000: PCLK1 = HCLK. 00567 * | | |001: PCLK1 = 1/2 HCLK. 00568 * | | |010: PCLK1 = 1/4 HCLK. 00569 * | | |011: PCLK1 = 1/8 HCLK. 00570 * | | |100: PCLK1 = 1/16 HCLK. 00571 * | | |Others: Reserved. 00572 * @var CLK_T::PLLCTL 00573 * Offset: 0x40 PLL Control Register 00574 * --------------------------------------------------------------------------------------------------- 00575 * |Bits |Field |Descriptions 00576 * | :----: | :----: | :---- | 00577 * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) 00578 * | | |Refer to the formulas below the table. 00579 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00580 * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) 00581 * | | |Refer to the formulas below the table. 00582 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00583 * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) 00584 * | | |Refer to the formulas below the table. 00585 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00586 * |[16] |PD |Power-down Mode (Write Protect) 00587 * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. 00588 * | | |0 = PLL is in normal mode. 00589 * | | |1 = PLL is in Power-down mode (default). 00590 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00591 * |[17] |BP |PLL Bypass Control (Write Protect) 00592 * | | |0 = PLL is in normal mode (default). 00593 * | | |1 = PLL clock output is same as PLL input clock FIN. 00594 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00595 * |[18] |OE |PLL OE (FOUT Enable) Pin Control (Write Protect) 00596 * | | |0 = PLL FOUT Enabled. 00597 * | | |1 = PLL FOUT is fixed low. 00598 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00599 * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect) 00600 * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT). 00601 * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). 00602 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00603 * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect) 00604 * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz). 00605 * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz). 00606 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00607 * |[28] |BANDSEL |PLL Stable Counter Selection (Write Protect) 00608 * | | |0 = PLL low band frequency select. (FVCO range is 200MHz ~ 400MHZ) 00609 * | | |1 = PLL high band frequency select. (FVCO range is 400MHz ~ 500MHZ) 00610 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00611 * @var CLK_T::STATUS 00612 * Offset: 0x50 Clock Status Monitor Register 00613 * --------------------------------------------------------------------------------------------------- 00614 * |Bits |Field |Descriptions 00615 * | :----: | :----: | :---- | 00616 * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) 00617 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. 00618 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. 00619 * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) 00620 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. 00621 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. 00622 * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) 00623 * | | |0 = Internal PLL clock is not stable or disabled. 00624 * | | |1 = Internal PLL clock is stable and enabled. 00625 * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) 00626 * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. 00627 * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. 00628 * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) 00629 * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. 00630 * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. 00631 * | | |Note: This bit is read only. 00632 * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only) 00633 * | | |This bit is updated when software switches system clock source 00634 * | | |If switch target clock is stable, this bit will be set to 0 00635 * | | |If switch target clock is not stable, this bit will be set to 1. 00636 * | | |0 = Clock switching success. 00637 * | | |1 = Clock switching failure. 00638 * | | |Note: Write 1 to clear the bit to 0. 00639 * @var CLK_T::CLKOCTL 00640 * Offset: 0x60 Clock Output Control Register 00641 * --------------------------------------------------------------------------------------------------- 00642 * |Bits |Field |Descriptions 00643 * | :----: | :----: | :---- | 00644 * |[3:0] |FREQSEL |Clock Output Frequency Selection 00645 * | | |The formula of output frequency is 00646 * | | |Fout = Fin/2(N+1). 00647 * | | |Fin is the input clock frequency. 00648 * | | |Fout is the frequency of divider output clock. 00649 * | | |N is the 4-bit value of FREQSEL[3:0]. 00650 * |[4] |CLKOEN |Clock Output Enable Bit 00651 * | | |0 = Clock Output function Disabled. 00652 * | | |1 = Clock Output function Enabled. 00653 * |[5] |DIV1EN |Clock Output Divide One Enable Bit 00654 * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. 00655 * | | |1 = Clock Output will output clock with source frequency. 00656 * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit 00657 * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. 00658 * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled. 00659 * @var CLK_T::CLKDCTL 00660 * Offset: 0x70 Clock Fail Detector Control Register 00661 * --------------------------------------------------------------------------------------------------- 00662 * |Bits |Field |Descriptions 00663 * | :----: | :----: | :---- | 00664 * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit 00665 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. 00666 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. 00667 * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit 00668 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. 00669 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. 00670 * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit 00671 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. 00672 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. 00673 * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit 00674 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. 00675 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. 00676 * |[16] |HXTFQDEN |HXT Clock Frequency Range Detector Enable Bit 00677 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled. 00678 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled. 00679 * |[17] |HXTFQIEN |HXT Clock Frequency Range Detector Interrupt Enable Bit 00680 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled. 00681 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled. 00682 * @var CLK_T::CLKDSTS 00683 * Offset: 0x74 Clock Fail Detector Status Register 00684 * --------------------------------------------------------------------------------------------------- 00685 * |Bits |Field |Descriptions 00686 * | :----: | :----: | :---- | 00687 * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag 00688 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. 00689 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops. 00690 * | | |Note: Write 1 to clear the bit to 0. 00691 * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag 00692 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. 00693 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. 00694 * | | |Note: Write 1 to clear the bit to 0. 00695 * |[8] |HXTFQIF |HXT Clock Frequency Range Detector Interrupt Flag 00696 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is normal. 00697 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. 00698 * | | |Note: Write 1 to clear the bit to 0. 00699 * @var CLK_T::CDUPB 00700 * Offset: 0x78 Clock Frequency Range Detector Upper Boundary Register 00701 * --------------------------------------------------------------------------------------------------- 00702 * |Bits |Field |Descriptions 00703 * | :----: | :----: | :---- | 00704 * |[9:0] |UPERBD |HXT Clock Frequency Range Detector Upper Boundary Value 00705 * | | |The bits define the maximum value of frequency range detector window. 00706 * | | |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. 00707 * @var CLK_T::CDLOWB 00708 * Offset: 0x7C Clock Frequency Range Detector Lower Boundary Register 00709 * --------------------------------------------------------------------------------------------------- 00710 * |Bits |Field |Descriptions 00711 * | :----: | :----: | :---- | 00712 * |[9:0] |LOWERBD |HXT Clock Frequency Range Detector Lower Boundary Value 00713 * | | |The bits define the minimum value of frequency range detector window. 00714 * | | |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. 00715 * @var CLK_T::PMUCTL 00716 * Offset: 0x90 Power Manager Control Register 00717 * --------------------------------------------------------------------------------------------------- 00718 * |Bits |Field |Descriptions 00719 * | :----: | :----: | :---- | 00720 * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect) 00721 * | | |This is a protected register. Please refer to open lock sequence to program it. 00722 * | | |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction. 00723 * | | |000 = Power-down mode is selected. (PD) 00724 * | | |001 = Low leakage Power-down mode is selected (LLPD). 00725 * | | |010 =Fast wake-up Power-down mode is selected (FWPD). 00726 * | | |011 = Reserved. 00727 * | | |100 = Standby Power-down mode 0 is selected (SPD0) (SRAM retention). 00728 * | | |101 = Standby Power-down mode 1 is selected (SPD1). 00729 * | | |110 = Deep Power-down mode is selected (DPD). 00730 * | | |111 = Reserved. 00731 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00732 * |[8] |WKTMREN |Wake-up Timer Enable (Write Protect) 00733 * | | |This is a protected register. Please refer to open lock sequence to program it. 00734 * | | |0 = Wake-up timer disable at DPD/SPD mode. 00735 * | | |1 = Wake-up timer enabled at DPD/SPD mode. 00736 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00737 * |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) 00738 * | | |This is a protected register. Please refer to open lock sequence to program it. 00739 * | | |These bits control wake-up timer time-out interval when chip at DPD/SPD mode. 00740 * | | |000 = Time-out interval is 128 OSC10K clocks (12.8 ms). 00741 * | | |001 = Time-out interval is 256 OSC10K clocks (25.6 ms). 00742 * | | |010 = Time-out interval is 512 OSC10K clocks (51.2 ms). 00743 * | | |011 = Time-out interval is 1024 OSC10K clocks (102.4ms). 00744 * | | |100 = Time-out interval is 4096 OSC10K clocks (409.6ms). 00745 * | | |101 = Time-out interval is 8192 OSC10K clocks (819.2ms). 00746 * | | |110 = Time-out interval is 16384 OSC10K clocks (1638.4ms). 00747 * | | |111 = Time-out interval is 65536 OSC10K clocks (6553.6ms). 00748 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00749 * |[17:16] |WKPINEN |Wake-up Pin Enable (Write Protect) 00750 * | | |This is a protected register. Please refer to open lock sequence to program it. 00751 * | | |00 = Wake-up pin disable at Deep Power-down mode. 00752 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 00753 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 00754 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 00755 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00756 * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect) 00757 * | | |This is a protected register. Please refer to open lock sequence to program it. 00758 * | | |0 = ACMP wake-up disable at Standby Power-down mode. 00759 * | | |1 = ACMP wake-up enabled at Standby Power-down mode. 00760 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00761 * |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect) 00762 * | | |This is a protected register. Please refer to open lock sequence to program it. 00763 * | | |0 = RTC wake-up disable at Deep Power-down mode or Standby Power-down mode. 00764 * | | |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode. 00765 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 00766 * @var CLK_T::PMUSTS 00767 * Offset: 0x94 Power Manager Status Register 00768 * --------------------------------------------------------------------------------------------------- 00769 * |Bits |Field |Descriptions 00770 * | :----: | :----: | :---- | 00771 * |[0] |PINWK |Pin Wake-up Flag (Read Only) 00772 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0) 00773 * | | |This flag is cleared when DPD mode is entered. 00774 * |[1] |TMRWK |Timer Wake-up Flag (Read Only) 00775 * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out 00776 * | | |This flag is cleared when DPD or SPD mode is entered. 00777 * |[2] |RTCWK |RTC Wake-up Flag (Read Only) 00778 * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened 00779 * | | |This flag is cleared when DPD or SPD mode is entered. 00780 * |[8] |GPAWK |GPA Wake-up Flag (Read Only) 00781 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins 00782 * | | |This flag is cleared when SPD mode is entered. 00783 * |[9] |GPBWK |GPB Wake-up Flag (Read Only) 00784 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins 00785 * | | |This flag is cleared when SPD mode is entered. 00786 * |[10] |GPCWK |GPC Wake-up Flag (Read Only) 00787 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins 00788 * | | |This flag is cleared when SPD mode is entered. 00789 * |[11] |GPDWK |GPD Wake-up Flag (Read Only) 00790 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins 00791 * | | |This flag is cleared when SPD mode is entered. 00792 * |[12] |LVRWK |LVR Wake-up Flag (Read Only) 00793 * | | |This flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened 00794 * | | |This flag is cleared when SPD mode is entered. 00795 * |[13] |BODWK |BOD Wake-up Flag (Read Only) 00796 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened 00797 * | | |This flag is cleared when SPD mode is entered. 00798 * |[14] |ACMPWK |ACMP Wake-up Flag (Read Only) 00799 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition 00800 * | | |This flag is cleared when SPD mode is entered. 00801 * |[31] |CLRWK |Clear Wake-up Flag 00802 * | | |0 = No clear. 00803 * | | |1 = Clear all wake-up flag. 00804 * @var CLK_T::LDOCTL 00805 * Offset: 0x98 LDO Control Register 00806 * --------------------------------------------------------------------------------------------------- 00807 * |Bits |Field |Descriptions 00808 * | :----: | :----: | :---- | 00809 * |[18] |PDBIASEN |Power-down Bias Enable Bit 00810 * | | |0 = Reserved. 00811 * | | |1 = Power-down bias enabled. 00812 * | | |Note: This bit should set to 1 before chip enter power-down mode. 00813 * @var CLK_T::SWKDBCTL 00814 * Offset: 0x9C Standby Power-down Wake-up De-bounce Control Register 00815 * --------------------------------------------------------------------------------------------------- 00816 * |Bits |Field |Descriptions 00817 * | :----: | :----: | :---- | 00818 * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection 00819 * | | |0000 = Sample wake-up input once per 1 clocks. 00820 * | | |0001 = Sample wake-up input once per 2 clocks. 00821 * | | |0010 = Sample wake-up input once per 4 clocks. 00822 * | | |0011 = Sample wake-up input once per 8 clocks. 00823 * | | |0100 = Sample wake-up input once per 16 clocks. 00824 * | | |0101 = Sample wake-up input once per 32 clocks. 00825 * | | |0110 = Sample wake-up input once per 64 clocks. 00826 * | | |0111 = Sample wake-up input once per 128 clocks. 00827 * | | |1000 = Sample wake-up input once per 256 clocks. 00828 * | | |1001 = Sample wake-up input once per 2*256 clocks. 00829 * | | |1010 = Sample wake-up input once per 4*256 clocks. 00830 * | | |1011 = Sample wake-up input once per 8*256 clocks. 00831 * | | |1100 = Sample wake-up input once per 16*256 clocks. 00832 * | | |1101 = Sample wake-up input once per 32*256 clocks. 00833 * | | |1110 = Sample wake-up input once per 64*256 clocks. 00834 * | | |1111 = Sample wake-up input once per 128*256 clocks. 00835 * | | |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). 00836 * @var CLK_T::PASWKCTL 00837 * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register 00838 * --------------------------------------------------------------------------------------------------- 00839 * |Bits |Field |Descriptions 00840 * | :----: | :----: | :---- | 00841 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 00842 * | | |0 = GPA group pin wake-up function disabled. 00843 * | | |1 = GPA group pin wake-up function enabled. 00844 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 00845 * | | |0 = GPA group pin rising edge wake-up function disabled. 00846 * | | |1 = GPA group pin rising edge wake-up function enabled. 00847 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 00848 * | | |0 = GPA group pin falling edge wake-up function disabled. 00849 * | | |1 = GPA group pin falling edge wake-up function enabled. 00850 * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select 00851 * | | |0000 = GPA.0 wake-up function enabled. 00852 * | | |0001 = GPA.1 wake-up function enabled. 00853 * | | |0010 = GPA.2 wake-up function enabled. 00854 * | | |0011 = GPA.3 wake-up function enabled. 00855 * | | |0100 = GPA.4 wake-up function enabled. 00856 * | | |0101 = GPA.5 wake-up function enabled. 00857 * | | |0110 = GPA.6 wake-up function enabled. 00858 * | | |0111 = GPA.7 wake-up function enabled. 00859 * | | |1000 = GPA.8 wake-up function enabled. 00860 * | | |1001 = GPA.9 wake-up function enabled. 00861 * | | |1010 = GPA.10 wake-up function enabled. 00862 * | | |1011 = GPA.11 wake-up function enabled. 00863 * | | |1100 = GPA.12 wake-up function enabled. 00864 * | | |1101 = GPA.13 wake-up function enabled. 00865 * | | |1110 = GPA.14 wake-up function enabled. 00866 * | | |1111 = GPA.15 wake-up function enabled. 00867 * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit 00868 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO 00869 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 00870 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. 00871 * | | |0 = Standby power-down wake-up pin De-bounce function disable. 00872 * | | |1 = Standby power-down wake-up pin De-bounce function enable. 00873 * | | |The de-bounce function is valid only for edge triggered. 00874 * @var CLK_T::PBSWKCTL 00875 * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register 00876 * --------------------------------------------------------------------------------------------------- 00877 * |Bits |Field |Descriptions 00878 * | :----: | :----: | :---- | 00879 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 00880 * | | |0 = GPB group pin wake-up function disabled. 00881 * | | |1 = GPB group pin wake-up function enabled. 00882 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 00883 * | | |0 = GPB group pin rising edge wake-up function disabled. 00884 * | | |1 = GPB group pin rising edge wake-up function enabled. 00885 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 00886 * | | |0 = GPB group pin falling edge wake-up function disabled. 00887 * | | |1 = GPB group pin falling edge wake-up function enabled. 00888 * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select 00889 * | | |0000 = GPB.0 wake-up function enabled. 00890 * | | |0001 = GPB.1 wake-up function enabled. 00891 * | | |0010 = GPB.2 wake-up function enabled. 00892 * | | |0011 = GPB.3 wake-up function enabled. 00893 * | | |0100 = GPB.4 wake-up function enabled. 00894 * | | |0101 = GPB.5 wake-up function enabled. 00895 * | | |0110 = GPB.6 wake-up function enabled. 00896 * | | |0111 = GPB.7 wake-up function enabled. 00897 * | | |1000 = GPB.8 wake-up function enabled. 00898 * | | |1001 = GPB.9 wake-up function enabled. 00899 * | | |1010 = GPB.10 wake-up function enabled. 00900 * | | |1011 = GPB.11 wake-up function enabled. 00901 * | | |1100 = GPB.12 wake-up function enabled. 00902 * | | |1101 = GPB.13 wake-up function enabled. 00903 * | | |1110 = GPB.14 wake-up function enabled. 00904 * | | |1111 = GPB.15 wake-up function enabled. 00905 * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit 00906 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO 00907 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 00908 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. 00909 * | | |0 = Standby power-down wake-up pin De-bounce function disable. 00910 * | | |1 = Standby power-down wake-up pin De-bounce function enable. 00911 * | | |The de-bounce function is valid only for edge triggered. 00912 * @var CLK_T::PCSWKCTL 00913 * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register 00914 * --------------------------------------------------------------------------------------------------- 00915 * |Bits |Field |Descriptions 00916 * | :----: | :----: | :---- | 00917 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 00918 * | | |0 = GPC group pin wake-up function disabled. 00919 * | | |1 = GPC group pin wake-up function enabled. 00920 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 00921 * | | |0 = GPC group pin rising edge wake-up function disabled. 00922 * | | |1 = GPC group pin rising edge wake-up function enabled. 00923 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 00924 * | | |0 = GPC group pin falling edge wake-up function disabled. 00925 * | | |1 = GPC group pin falling edge wake-up function enabled. 00926 * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select 00927 * | | |0000 = GPC.0 wake-up function enabled. 00928 * | | |0001 = GPC.1 wake-up function enabled. 00929 * | | |0010 = GPC.2 wake-up function enabled. 00930 * | | |0011 = GPC.3 wake-up function enabled. 00931 * | | |0100 = GPC.4 wake-up function enabled. 00932 * | | |0101 = GPC.5 wake-up function enabled. 00933 * | | |0110 = GPC.6 wake-up function enabled. 00934 * | | |0111 = GPC.7 wake-up function enabled. 00935 * | | |1000 = GPC.8 wake-up function enabled. 00936 * | | |1001 = GPC.9 wake-up function enabled. 00937 * | | |1010 = GPC.10 wake-up function enabled. 00938 * | | |1011 = GPC.11 wake-up function enabled. 00939 * | | |1100 = GPC.12 wake-up function enabled. 00940 * | | |1101 = GPC.13 wake-up function enabled. 00941 * | | |1110 = GPC.14 wake-up function enabled. 00942 * | | |1111 = GPC.15 wake-up function enabled. 00943 * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit 00944 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO 00945 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 00946 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. 00947 * | | |0 = Standby power-down wake-up pin De-bounce function disable. 00948 * | | |1 = Standby power-down wake-up pin De-bounce function enable. 00949 * | | |The de-bounce function is valid only for edge triggered. 00950 * @var CLK_T::PDSWKCTL 00951 * Offset: 0xAC GPD Standby Power-down Wake-up Control Register 00952 * --------------------------------------------------------------------------------------------------- 00953 * |Bits |Field |Descriptions 00954 * | :----: | :----: | :---- | 00955 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 00956 * | | |0 = GPD group pin wake-up function disabled. 00957 * | | |1 = GPD group pin wake-up function enabled. 00958 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 00959 * | | |0 = GPD group pin rising edge wake-up function disabled. 00960 * | | |1 = GPD group pin rising edge wake-up function enabled. 00961 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 00962 * | | |0 = GPD group pin falling edge wake-up function disabled. 00963 * | | |1 = GPD group pin falling edge wake-up function enabled. 00964 * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select 00965 * | | |0000 = GPD.0 wake-up function enabled. 00966 * | | |0001 = GPD.1 wake-up function enabled. 00967 * | | |0010 = GPD.2 wake-up function enabled. 00968 * | | |0011 = GPD.3 wake-up function enabled. 00969 * | | |0100 = GPD.4 wake-up function enabled. 00970 * | | |0101 = GPD.5 wake-up function enabled. 00971 * | | |0110 = GPD.6 wake-up function enabled. 00972 * | | |0111 = GPD.7 wake-up function enabled. 00973 * | | |1000 = GPD.8 wake-up function enabled. 00974 * | | |1001 = GPD.9 wake-up function enabled. 00975 * | | |1010 = GPD.10 wake-up function enabled. 00976 * | | |1011 = GPD.11 wake-up function enabled. 00977 * | | |1100 = GPD.12 wake-up function enabled. 00978 * | | |1101 = GPD.13 wake-up function enabled. 00979 * | | |1110 = GPD.14 wake-up function enabled. 00980 * | | |1111 = GPD.15 wake-up function enabled. 00981 * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit 00982 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO 00983 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up 00984 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. 00985 * | | |0 = Standby power-down wake-up pin De-bounce function disable. 00986 * | | |1 = Standby power-down wake-up pin De-bounce function enable. 00987 * | | |The de-bounce function is valid only for edge triggered. 00988 * @var CLK_T::IOPDCTL 00989 * Offset: 0xB0 GPIO Standby Power-down Control Register 00990 * --------------------------------------------------------------------------------------------------- 00991 * |Bits |Field |Descriptions 00992 * | :----: | :----: | :---- | 00993 * |[0] |IOHR |GPIO Hold Release 00994 * | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status 00995 * | | |After chip was waked up from standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status. 00996 * | | |This bit is auto cleared by hardware. 00997 */ 00998 __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ 00999 __IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */ 01000 __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */ 01001 __IO uint32_t APBCLK1; /*!< [0x000c] APB Devices Clock Enable Control Register 1 */ 01002 __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */ 01003 __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */ 01004 __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */ 01005 __IO uint32_t CLKSEL3; /*!< [0x001c] Clock Source Select Control Register 3 */ 01006 __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */ 01007 __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */ 01008 /** @cond HIDDEN_SYMBOLS */ 01009 __I uint32_t RESERVE0[1]; 01010 /** @endcond */ 01011 __IO uint32_t CLKDIV3; /*!< [0x002c] Clock Divider Number Register 3 */ 01012 __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */ 01013 __IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */ 01014 /** @cond HIDDEN_SYMBOLS */ 01015 __I uint32_t RESERVE1[2]; 01016 /** @endcond */ 01017 __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */ 01018 /** @cond HIDDEN_SYMBOLS */ 01019 __I uint32_t RESERVE2[3]; 01020 /** @endcond */ 01021 __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ 01022 /** @cond HIDDEN_SYMBOLS */ 01023 __I uint32_t RESERVE3[3]; 01024 /** @endcond */ 01025 __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */ 01026 /** @cond HIDDEN_SYMBOLS */ 01027 __I uint32_t RESERVE4[3]; 01028 /** @endcond */ 01029 __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */ 01030 __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */ 01031 __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register */ 01032 __IO uint32_t CDLOWB; /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register */ 01033 /** @cond HIDDEN_SYMBOLS */ 01034 __I uint32_t RESERVE5[4]; 01035 /** @endcond */ 01036 __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */ 01037 __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */ 01038 __IO uint32_t LDOCTL; /*!< [0x0098] LDO Control Register */ 01039 __IO uint32_t SWKDBCTL; /*!< [0x009c] Standby Power-down Wake-up De-bounce Control Register */ 01040 __IO uint32_t PASWKCTL; /*!< [0x00a0] GPA Standby Power-down Wake-up Control Register */ 01041 __IO uint32_t PBSWKCTL; /*!< [0x00a4] GPB Standby Power-down Wake-up Control Register */ 01042 __IO uint32_t PCSWKCTL; /*!< [0x00a8] GPC Standby Power-down Wake-up Control Register */ 01043 __IO uint32_t PDSWKCTL; /*!< [0x00ac] GPD Standby Power-down Wake-up Control Register */ 01044 __IO uint32_t IOPDCTL; /*!< [0x00b0] GPIO Standby Power-down Control Register */ 01045 01046 } CLK_T; 01047 01048 /** 01049 @addtogroup CLK_CONST CLK Bit Field Definition 01050 Constant Definitions for CLK Controller 01051 @{ */ 01052 01053 #define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ 01054 #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ 01055 01056 #define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ 01057 #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ 01058 01059 #define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ 01060 #define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ 01061 01062 #define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ 01063 #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ 01064 01065 #define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */ 01066 #define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */ 01067 01068 #define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */ 01069 #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */ 01070 01071 #define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */ 01072 #define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */ 01073 01074 #define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */ 01075 #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */ 01076 01077 #define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */ 01078 #define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */ 01079 01080 #define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */ 01081 #define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */ 01082 01083 #define CLK_PWRCTL_HXTTBEN_Pos (13) /*!< CLK_T::PWRCTL: HXTTBEN Position */ 01084 #define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) /*!< CLK_T::PWRCTL: HXTTBEN Mask */ 01085 01086 #define CLK_PWRCTL_HIRCSTBS_Pos (16) /*!< CLK_T::PWRCTL: HIRCSTBS Position */ 01087 #define CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos) /*!< CLK_T::PWRCTL: HIRCSTBS Mask */ 01088 01089 #define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMACKEN Position */ 01090 #define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK_T::AHBCLK: PDMACKEN Mask */ 01091 01092 #define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */ 01093 #define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */ 01094 01095 #define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */ 01096 #define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */ 01097 01098 #define CLK_AHBCLK_EMACCKEN_Pos (5) /*!< CLK_T::AHBCLK: EMACCKEN Position */ 01099 #define CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos) /*!< CLK_T::AHBCLK: EMACCKEN Mask */ 01100 01101 #define CLK_AHBCLK_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK: SDH0CKEN Position */ 01102 #define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK: SDH0CKEN Mask */ 01103 01104 #define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */ 01105 #define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */ 01106 01107 #define CLK_AHBCLK_HSUSBDCKEN_Pos (10) /*!< CLK_T::AHBCLK: HSUSBDCKEN Position */ 01108 #define CLK_AHBCLK_HSUSBDCKEN_Msk (0x1ul << CLK_AHBCLK_HSUSBDCKEN_Pos) /*!< CLK_T::AHBCLK: HSUSBDCKEN Mask */ 01109 01110 #define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK: CRPTCKEN Position */ 01111 #define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK: CRPTCKEN Mask */ 01112 01113 #define CLK_AHBCLK_SPIMCKEN_Pos (14) /*!< CLK_T::AHBCLK: SPIMCKEN Position */ 01114 #define CLK_AHBCLK_SPIMCKEN_Msk (0x1ul << CLK_AHBCLK_SPIMCKEN_Pos) /*!< CLK_T::AHBCLK: SPIMCKEN Mask */ 01115 01116 #define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */ 01117 #define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */ 01118 01119 #define CLK_AHBCLK_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK: USBHCKEN Position */ 01120 #define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */ 01121 01122 #define CLK_AHBCLK_SDH1CKEN_Pos (17) /*!< CLK_T::AHBCLK: SDH1CKEN Position */ 01123 #define CLK_AHBCLK_SDH1CKEN_Msk (0x1ul << CLK_AHBCLK_SDH1CKEN_Pos) /*!< CLK_T::AHBCLK: SDH1CKEN Mask */ 01124 01125 #define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */ 01126 #define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */ 01127 01128 #define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */ 01129 #define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ 01130 01131 #define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ 01132 #define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ 01133 01134 #define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ 01135 #define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ 01136 01137 #define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ 01138 #define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ 01139 01140 #define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ 01141 #define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ 01142 01143 #define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */ 01144 #define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */ 01145 01146 #define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */ 01147 #define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */ 01148 01149 #define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */ 01150 #define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */ 01151 01152 #define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */ 01153 #define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */ 01154 01155 #define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */ 01156 #define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */ 01157 01158 #define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */ 01159 #define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */ 01160 01161 #define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */ 01162 #define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */ 01163 01164 #define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */ 01165 #define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */ 01166 01167 #define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */ 01168 #define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */ 01169 01170 #define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */ 01171 #define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ 01172 01173 #define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */ 01174 #define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ 01175 01176 #define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */ 01177 #define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ 01178 01179 #define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */ 01180 #define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */ 01181 01182 #define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */ 01183 #define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */ 01184 01185 #define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */ 01186 #define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ 01187 01188 #define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */ 01189 #define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */ 01190 01191 #define CLK_APBCLK0_CAN1CKEN_Pos (25) /*!< CLK_T::APBCLK0: CAN1CKEN Position */ 01192 #define CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos) /*!< CLK_T::APBCLK0: CAN1CKEN Mask */ 01193 01194 #define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */ 01195 #define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */ 01196 01197 #define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ 01198 #define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ 01199 01200 #define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */ 01201 #define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */ 01202 01203 #define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */ 01204 #define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */ 01205 01206 #define CLK_APBCLK0_HSOTGCKEN_Pos (30) /*!< CLK_T::APBCLK0: HSOTGCKEN Position */ 01207 #define CLK_APBCLK0_HSOTGCKEN_Msk (0x1ul << CLK_APBCLK0_HSOTGCKEN_Pos) /*!< CLK_T::APBCLK0: HSOTGCKEN Mask */ 01208 01209 #define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */ 01210 #define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */ 01211 01212 #define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */ 01213 #define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */ 01214 01215 #define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */ 01216 #define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */ 01217 01218 #define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */ 01219 #define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */ 01220 01221 #define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ 01222 #define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ 01223 01224 #define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */ 01225 #define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */ 01226 01227 #define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */ 01228 #define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */ 01229 01230 #define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */ 01231 #define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */ 01232 01233 #define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */ 01234 #define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */ 01235 01236 #define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */ 01237 #define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */ 01238 01239 #define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */ 01240 #define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */ 01241 01242 #define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: QEI0CKEN Position */ 01243 #define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK_T::APBCLK1: QEI0CKEN Mask */ 01244 01245 #define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: QEI1CKEN Position */ 01246 #define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK_T::APBCLK1: QEI1CKEN Mask */ 01247 01248 #define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */ 01249 #define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */ 01250 01251 #define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */ 01252 #define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */ 01253 01254 #define CLK_APBCLK1_OPACKEN_Pos (30) /*!< CLK_T::APBCLK1: OPACKEN Position */ 01255 #define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos) /*!< CLK_T::APBCLK1: OPACKEN Mask */ 01256 01257 #define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */ 01258 #define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */ 01259 01260 #define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */ 01261 #define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */ 01262 01263 #define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */ 01264 #define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */ 01265 01266 #define CLK_CLKSEL0_SDH1SEL_Pos (22) /*!< CLK_T::CLKSEL0: SDH1SEL Position */ 01267 #define CLK_CLKSEL0_SDH1SEL_Msk (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos) /*!< CLK_T::CLKSEL0: SDH1SEL Mask */ 01268 01269 #define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */ 01270 #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */ 01271 01272 #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ 01273 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ 01274 01275 #define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ 01276 #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ 01277 01278 #define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ 01279 #define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ 01280 01281 #define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ 01282 #define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ 01283 01284 #define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */ 01285 #define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */ 01286 01287 #define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK_T::CLKSEL1: UART1SEL Position */ 01288 #define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */ 01289 01290 #define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */ 01291 #define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */ 01292 01293 #define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */ 01294 #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */ 01295 01296 #define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */ 01297 #define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */ 01298 01299 #define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */ 01300 #define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */ 01301 01302 #define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */ 01303 #define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */ 01304 01305 #define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */ 01306 #define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */ 01307 01308 #define CLK_CLKSEL2_SPI1SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI1SEL Position */ 01309 #define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */ 01310 01311 #define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */ 01312 #define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */ 01313 01314 #define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */ 01315 #define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */ 01316 01317 #define CLK_CLKSEL2_SPI2SEL_Pos (10) /*!< CLK_T::CLKSEL2: SPI2SEL Position */ 01318 #define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */ 01319 01320 #define CLK_CLKSEL2_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI3SEL Position */ 01321 #define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */ 01322 01323 #define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */ 01324 #define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */ 01325 01326 #define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */ 01327 #define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */ 01328 01329 #define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */ 01330 #define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */ 01331 01332 #define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */ 01333 #define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */ 01334 01335 #define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */ 01336 #define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */ 01337 01338 #define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */ 01339 #define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */ 01340 01341 #define CLK_CLKSEL3_UART3SEL_Pos (26) /*!< CLK_T::CLKSEL3: UART3SEL Position */ 01342 #define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos) /*!< CLK_T::CLKSEL3: UART3SEL Mask */ 01343 01344 #define CLK_CLKSEL3_UART4SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART4SEL Position */ 01345 #define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */ 01346 01347 #define CLK_CLKSEL3_UART5SEL_Pos (30) /*!< CLK_T::CLKSEL3: UART5SEL Position */ 01348 #define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */ 01349 01350 #define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */ 01351 #define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */ 01352 01353 #define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */ 01354 #define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */ 01355 01356 #define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */ 01357 #define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */ 01358 01359 #define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */ 01360 #define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */ 01361 01362 #define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */ 01363 #define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */ 01364 01365 #define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */ 01366 #define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */ 01367 01368 #define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */ 01369 #define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */ 01370 01371 #define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */ 01372 #define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */ 01373 01374 #define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */ 01375 #define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */ 01376 01377 #define CLK_CLKDIV3_EMACDIV_Pos (16) /*!< CLK_T::CLKDIV3: EMACDIV Position */ 01378 #define CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLK_T::CLKDIV3: EMACDIV Mask */ 01379 01380 #define CLK_CLKDIV3_SDH1DIV_Pos (24) /*!< CLK_T::CLKDIV3: SDH1DIV Position */ 01381 #define CLK_CLKDIV3_SDH1DIV_Msk (0xfful << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLK_T::CLKDIV3: SDH1DIV Mask */ 01382 01383 #define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ 01384 #define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ 01385 01386 #define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */ 01387 #define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */ 01388 01389 #define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */ 01390 #define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */ 01391 01392 #define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */ 01393 #define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */ 01394 01395 #define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */ 01396 #define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */ 01397 01398 #define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */ 01399 #define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */ 01400 01401 #define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */ 01402 #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */ 01403 01404 #define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */ 01405 #define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */ 01406 01407 #define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */ 01408 #define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */ 01409 01410 #define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */ 01411 #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */ 01412 01413 #define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */ 01414 #define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */ 01415 01416 #define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */ 01417 #define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */ 01418 01419 #define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */ 01420 #define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */ 01421 01422 #define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */ 01423 #define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */ 01424 01425 #define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ 01426 #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ 01427 01428 #define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ 01429 #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ 01430 01431 #define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */ 01432 #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */ 01433 01434 #define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ 01435 #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ 01436 01437 #define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ 01438 #define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ 01439 01440 #define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */ 01441 #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */ 01442 01443 #define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ 01444 #define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ 01445 01446 #define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ 01447 #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ 01448 01449 #define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ 01450 #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ 01451 01452 #define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */ 01453 #define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */ 01454 01455 #define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ 01456 #define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ 01457 01458 #define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ 01459 #define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ 01460 01461 #define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ 01462 #define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ 01463 01464 #define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ 01465 #define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ 01466 01467 #define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ 01468 #define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ 01469 01470 #define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ 01471 #define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ 01472 01473 #define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ 01474 #define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ 01475 01476 #define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ 01477 #define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ 01478 01479 #define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ 01480 #define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ 01481 01482 #define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ 01483 #define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ 01484 01485 #define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ 01486 #define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ 01487 01488 #define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */ 01489 #define CLK_PMUCTL_PDMSEL_Msk (0x7ul << CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */ 01490 01491 #define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */ 01492 #define CLK_PMUCTL_WKTMREN_Msk (0x1ul << CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */ 01493 01494 #define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */ 01495 #define CLK_PMUCTL_WKTMRIS_Msk (0x7ul << CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */ 01496 01497 #define CLK_PMUCTL_WKPINEN_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN Position */ 01498 #define CLK_PMUCTL_WKPINEN_Msk (0x3ul << CLK_PMUCTL_WKPINEN_Pos) /*!< CLK_T::PMUCTL: WKPINEN Mask */ 01499 01500 #define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */ 01501 #define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */ 01502 01503 #define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */ 01504 #define CLK_PMUCTL_RTCWKEN_Msk (0x1ul << CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */ 01505 01506 #define CLK_PMUSTS_PINWK_Pos (0) /*!< CLK_T::PMUSTS: PINWK Position */ 01507 #define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos) /*!< CLK_T::PMUSTS: PINWK Mask */ 01508 01509 #define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */ 01510 #define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */ 01511 01512 #define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */ 01513 #define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */ 01514 01515 #define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */ 01516 #define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */ 01517 01518 #define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */ 01519 #define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */ 01520 01521 #define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */ 01522 #define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */ 01523 01524 #define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */ 01525 #define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */ 01526 01527 #define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */ 01528 #define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */ 01529 01530 #define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */ 01531 #define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */ 01532 01533 #define CLK_PMUSTS_ACMPWK_Pos (14) /*!< CLK_T::PMUSTS: ACMPWK Position */ 01534 #define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos) /*!< CLK_T::PMUSTS: ACMPWK Mask */ 01535 01536 #define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */ 01537 #define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */ 01538 01539 #define CLK_LDOCTL_PDBIASEN_Pos (18) /*!< CLK_T::LDOCTL: PDBIASEN Position */ 01540 #define CLK_LDOCTL_PDBIASEN_Msk (0x1ul << CLK_LDOCTL_PDBIASEN_Pos) /*!< CLK_T::LDOCTL: PDBIASEN Mask */ 01541 01542 #define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */ 01543 #define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */ 01544 01545 #define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */ 01546 #define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */ 01547 01548 #define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */ 01549 #define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */ 01550 01551 #define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */ 01552 #define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */ 01553 01554 #define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */ 01555 #define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */ 01556 01557 #define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */ 01558 #define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */ 01559 01560 #define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */ 01561 #define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */ 01562 01563 #define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */ 01564 #define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */ 01565 01566 #define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */ 01567 #define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */ 01568 01569 #define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */ 01570 #define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */ 01571 01572 #define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */ 01573 #define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */ 01574 01575 #define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */ 01576 #define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */ 01577 01578 #define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */ 01579 #define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */ 01580 01581 #define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */ 01582 #define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */ 01583 01584 #define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */ 01585 #define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */ 01586 01587 #define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */ 01588 #define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */ 01589 01590 #define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */ 01591 #define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */ 01592 01593 #define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */ 01594 #define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */ 01595 01596 #define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */ 01597 #define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */ 01598 01599 #define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */ 01600 #define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */ 01601 01602 #define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */ 01603 #define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */ 01604 01605 #define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */ 01606 #define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */ 01607 01608 /**@}*/ /* CLK_CONST */ 01609 /**@}*/ /* end of CLK register group */ 01610 /**@}*/ /* end of REGISTER group */ 01611 01612 #if defined ( __CC_ARM ) 01613 #pragma no_anon_unions 01614 #endif 01615 01616 #endif /* __CLK_REG_H__ */
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