lpc43xx_scu.h

00001 /**
00002  * @file    lpc43xx_scu.h
00003  * @brief   
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 /* Peripheral group ----------------------------------------------------------- */
00023 /** @defgroup SCU   SCU (System Control Unit)
00024  * @ingroup LPC4300CMSIS_FwLib_Drivers
00025  * @{
00026  */
00027 
00028 #ifndef __SCU_H
00029 #define __SCU_H
00030 
00031 #ifdef __cplusplus
00032 extern "C"
00033 {
00034 #endif
00035 
00036 /* Private macros ------------------------------------------------------------- */
00037 /** @defgroup SCT_Private_Macros SCT Private Macros
00038  * @{
00039  */
00040 
00041 /** Port offset definition */
00042 #define PORT_OFFSET     0x80
00043 /** Pin offset definition */
00044 #define PIN_OFFSET      0x04
00045 
00046 /* Pin mode defines, following partly a definition from older chip architectures */
00047 #define MD_PUP  (0x0 << 3)
00048 #define MD_BUK  (0x1 << 3)
00049 #define MD_PLN  (0x2 << 3)
00050 #define MD_PDN  (0x3 << 3)
00051 #define MD_EHS  (0x1 << 5)
00052 #define MD_EZI  (0x1 << 6)
00053 #define MD_ZI   (0x1 << 7)
00054 #define MD_EHD0 (0x1 << 8)
00055 #define MD_EHD1 (0x1 << 9)
00056 #define MD_EHD2 (0x3 << 8)
00057 #define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
00058 
00059 
00060 /* Pin mode defines, more in line with the definitions in the LPC1800/4300 user manual */
00061 /* Defines for SFSPx_y pin configuration registers                                     */
00062 #define PDN_ENABLE        (1 << 3)  // Pull-down enable
00063 #define PDN_DISABLE       (0 << 3)      // Pull-down disable
00064 #define PUP_ENABLE        (0 << 4)      // Pull-up enable
00065 #define PUP_DISABLE       (1 << 4)  // Pull-up disable
00066 #define SLEWRATE_SLOW     (0 << 5)  // Slew rate for low noise with medium speed
00067 #define SLEWRATE_FAST     (1 << 5)  // Slew rate for medium noise with fast speed
00068 #define INBUF_ENABLE      (1 << 6)  // Input buffer
00069 #define INBUF_DISABLE     (0 << 6)  // Input buffer
00070 #define FILTER_ENABLE     (0 << 7)  // Glitch filter (for signals below 30MHz)
00071 #define FILTER_DISABLE    (1 << 7)  // No glitch filter (for signals above 30MHz)
00072 #define DRIVE_8MA         (1 << 8)  // Drive strength of 8mA
00073 #define DRIVE_14MA        (1 << 9)  // Drive strength of 14mA
00074 #define DRIVE_20MA        (3 << 8)  // Drive strength of 20mA
00075 
00076 
00077 /* Configuration examples for various I/O pins */
00078 #define EMC_IO          (PUP_ENABLE  | PDN_ENABLE  | SLEWRATE_FAST | INBUF_ENABLE  | FILTER_DISABLE)
00079 #define LCD_PINCONFIG   (PUP_DISABLE | PDN_DISABLE | SLEWRATE_FAST | INBUF_ENABLE  | FILTER_DISABLE)
00080 #define CLK_IN          (PUP_ENABLE  | PDN_ENABLE  | SLEWRATE_FAST | INBUF_ENABLE  | FILTER_DISABLE)
00081 #define CLK_OUT         (PUP_ENABLE  | PDN_ENABLE  | SLEWRATE_FAST | INBUF_ENABLE  | FILTER_DISABLE)
00082 #define GPIO_PUP    (PUP_ENABLE  | PDN_DISABLE | SLEWRATE_SLOW | INBUF_ENABLE  | FILTER_ENABLE )
00083 #define GPIO_PDN    (PUP_DISABLE | PDN_ENABLE  | SLEWRATE_SLOW | INBUF_ENABLE  | FILTER_ENABLE )
00084 #define GPIO_NOPULL (PUP_DISABLE | PDN_DISABLE | SLEWRATE_SLOW | INBUF_ENABLE  | FILTER_ENABLE )
00085 #define UART_RX_TX  (PUP_DISABLE | PDN_ENABLE  | SLEWRATE_SLOW | INBUF_ENABLE  | FILTER_ENABLE )
00086 #define SSP_IO          (PUP_ENABLE  | PDN_ENABLE  | SLEWRATE_FAST | INBUF_ENABLE  | FILTER_DISABLE)
00087 
00088 
00089 /* Pin function */
00090 #define FUNC0           0x0             /** Function 0  */
00091 #define FUNC1           0x1             /** Function 1  */
00092 #define FUNC2           0x2             /** Function 2  */
00093 #define FUNC3           0x3             /** Function 3  */
00094 #define FUNC4           0x4
00095 #define FUNC5           0x5
00096 #define FUNC6           0x6
00097 #define FUNC7           0x7
00098 /**
00099  * @}
00100  */
00101 
00102 #define LPC_SCU_PIN(po, pi)   (*(volatile int         *) (LPC_SCU_BASE + ((po) * 0x80) + ((pi) * 0x4))    )
00103 #define LPC_SCU_CLK(c)        (*(volatile int         *) (LPC_SCU_BASE + 0xC00 + ((c) * 0x4))    )
00104 
00105 /* Public Functions ----------------------------------------------------------- */
00106 /** @defgroup SCU_Public_Functions SCU Public Functions
00107  * @{
00108  */
00109 
00110 void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
00111 
00112 /**
00113  * @}
00114  */
00115 
00116 #ifdef __cplusplus
00117 }
00118 #endif
00119 
00120 #endif /* end __SCU_H */
00121 
00122 /**
00123  * @}
00124  */
00125