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udphs.h
00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) %copyright_year%, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 #ifndef _SAM3U_UDPHS_INSTANCE_ 00031 #define _SAM3U_UDPHS_INSTANCE_ 00032 00033 /* ========== Register definition for UDPHS peripheral ========== */ 00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 00035 #define REG_UDPHS_CTRL (0x400A4000U) /**< \brief (UDPHS) UDPHS Control Register */ 00036 #define REG_UDPHS_FNUM (0x400A4004U) /**< \brief (UDPHS) UDPHS Frame Number Register */ 00037 #define REG_UDPHS_IEN (0x400A4010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */ 00038 #define REG_UDPHS_INTSTA (0x400A4014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */ 00039 #define REG_UDPHS_CLRINT (0x400A4018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */ 00040 #define REG_UDPHS_EPTRST (0x400A401CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */ 00041 #define REG_UDPHS_TST (0x400A40E0U) /**< \brief (UDPHS) UDPHS Test Register */ 00042 #define REG_UDPHS_EPTCFG0 (0x400A4100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */ 00043 #define REG_UDPHS_EPTCTLENB0 (0x400A4104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */ 00044 #define REG_UDPHS_EPTCTLDIS0 (0x400A4108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */ 00045 #define REG_UDPHS_EPTCTL0 (0x400A410CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */ 00046 #define REG_UDPHS_EPTSETSTA0 (0x400A4114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */ 00047 #define REG_UDPHS_EPTCLRSTA0 (0x400A4118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */ 00048 #define REG_UDPHS_EPTSTA0 (0x400A411CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */ 00049 #define REG_UDPHS_EPTCFG1 (0x400A4120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */ 00050 #define REG_UDPHS_EPTCTLENB1 (0x400A4124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */ 00051 #define REG_UDPHS_EPTCTLDIS1 (0x400A4128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */ 00052 #define REG_UDPHS_EPTCTL1 (0x400A412CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */ 00053 #define REG_UDPHS_EPTSETSTA1 (0x400A4134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */ 00054 #define REG_UDPHS_EPTCLRSTA1 (0x400A4138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */ 00055 #define REG_UDPHS_EPTSTA1 (0x400A413CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */ 00056 #define REG_UDPHS_EPTCFG2 (0x400A4140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */ 00057 #define REG_UDPHS_EPTCTLENB2 (0x400A4144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */ 00058 #define REG_UDPHS_EPTCTLDIS2 (0x400A4148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */ 00059 #define REG_UDPHS_EPTCTL2 (0x400A414CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */ 00060 #define REG_UDPHS_EPTSETSTA2 (0x400A4154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */ 00061 #define REG_UDPHS_EPTCLRSTA2 (0x400A4158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */ 00062 #define REG_UDPHS_EPTSTA2 (0x400A415CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */ 00063 #define REG_UDPHS_EPTCFG3 (0x400A4160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */ 00064 #define REG_UDPHS_EPTCTLENB3 (0x400A4164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */ 00065 #define REG_UDPHS_EPTCTLDIS3 (0x400A4168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */ 00066 #define REG_UDPHS_EPTCTL3 (0x400A416CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */ 00067 #define REG_UDPHS_EPTSETSTA3 (0x400A4174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */ 00068 #define REG_UDPHS_EPTCLRSTA3 (0x400A4178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */ 00069 #define REG_UDPHS_EPTSTA3 (0x400A417CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */ 00070 #define REG_UDPHS_EPTCFG4 (0x400A4180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */ 00071 #define REG_UDPHS_EPTCTLENB4 (0x400A4184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */ 00072 #define REG_UDPHS_EPTCTLDIS4 (0x400A4188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */ 00073 #define REG_UDPHS_EPTCTL4 (0x400A418CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */ 00074 #define REG_UDPHS_EPTSETSTA4 (0x400A4194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */ 00075 #define REG_UDPHS_EPTCLRSTA4 (0x400A4198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */ 00076 #define REG_UDPHS_EPTSTA4 (0x400A419CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */ 00077 #define REG_UDPHS_EPTCFG5 (0x400A41A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */ 00078 #define REG_UDPHS_EPTCTLENB5 (0x400A41A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */ 00079 #define REG_UDPHS_EPTCTLDIS5 (0x400A41A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */ 00080 #define REG_UDPHS_EPTCTL5 (0x400A41ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */ 00081 #define REG_UDPHS_EPTSETSTA5 (0x400A41B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */ 00082 #define REG_UDPHS_EPTCLRSTA5 (0x400A41B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */ 00083 #define REG_UDPHS_EPTSTA5 (0x400A41BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */ 00084 #define REG_UDPHS_EPTCFG6 (0x400A41C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */ 00085 #define REG_UDPHS_EPTCTLENB6 (0x400A41C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */ 00086 #define REG_UDPHS_EPTCTLDIS6 (0x400A41C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */ 00087 #define REG_UDPHS_EPTCTL6 (0x400A41CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */ 00088 #define REG_UDPHS_EPTSETSTA6 (0x400A41D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */ 00089 #define REG_UDPHS_EPTCLRSTA6 (0x400A41D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */ 00090 #define REG_UDPHS_EPTSTA6 (0x400A41DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */ 00091 #define REG_UDPHS_DMANXTDSC0 (0x400A4300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */ 00092 #define REG_UDPHS_DMAADDRESS0 (0x400A4304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */ 00093 #define REG_UDPHS_DMACONTROL0 (0x400A4308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */ 00094 #define REG_UDPHS_DMASTATUS0 (0x400A430CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */ 00095 #define REG_UDPHS_DMANXTDSC1 (0x400A4310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */ 00096 #define REG_UDPHS_DMAADDRESS1 (0x400A4314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */ 00097 #define REG_UDPHS_DMACONTROL1 (0x400A4318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */ 00098 #define REG_UDPHS_DMASTATUS1 (0x400A431CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */ 00099 #define REG_UDPHS_DMANXTDSC2 (0x400A4320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */ 00100 #define REG_UDPHS_DMAADDRESS2 (0x400A4324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */ 00101 #define REG_UDPHS_DMACONTROL2 (0x400A4328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */ 00102 #define REG_UDPHS_DMASTATUS2 (0x400A432CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */ 00103 #define REG_UDPHS_DMANXTDSC3 (0x400A4330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */ 00104 #define REG_UDPHS_DMAADDRESS3 (0x400A4334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */ 00105 #define REG_UDPHS_DMACONTROL3 (0x400A4338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */ 00106 #define REG_UDPHS_DMASTATUS3 (0x400A433CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */ 00107 #define REG_UDPHS_DMANXTDSC4 (0x400A4340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */ 00108 #define REG_UDPHS_DMAADDRESS4 (0x400A4344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */ 00109 #define REG_UDPHS_DMACONTROL4 (0x400A4348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */ 00110 #define REG_UDPHS_DMASTATUS4 (0x400A434CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */ 00111 #define REG_UDPHS_DMANXTDSC5 (0x400A4350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */ 00112 #define REG_UDPHS_DMAADDRESS5 (0x400A4354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */ 00113 #define REG_UDPHS_DMACONTROL5 (0x400A4358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */ 00114 #define REG_UDPHS_DMASTATUS5 (0x400A435CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */ 00115 #else 00116 #define REG_UDPHS_CTRL (*(RwReg*)0x400A4000U) /**< \brief (UDPHS) UDPHS Control Register */ 00117 #define REG_UDPHS_FNUM (*(RoReg*)0x400A4004U) /**< \brief (UDPHS) UDPHS Frame Number Register */ 00118 #define REG_UDPHS_IEN (*(RwReg*)0x400A4010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */ 00119 #define REG_UDPHS_INTSTA (*(RoReg*)0x400A4014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */ 00120 #define REG_UDPHS_CLRINT (*(WoReg*)0x400A4018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */ 00121 #define REG_UDPHS_EPTRST (*(WoReg*)0x400A401CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */ 00122 #define REG_UDPHS_TST (*(RwReg*)0x400A40E0U) /**< \brief (UDPHS) UDPHS Test Register */ 00123 #define REG_UDPHS_EPTCFG0 (*(RwReg*)0x400A4100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */ 00124 #define REG_UDPHS_EPTCTLENB0 (*(WoReg*)0x400A4104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */ 00125 #define REG_UDPHS_EPTCTLDIS0 (*(WoReg*)0x400A4108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */ 00126 #define REG_UDPHS_EPTCTL0 (*(RoReg*)0x400A410CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */ 00127 #define REG_UDPHS_EPTSETSTA0 (*(WoReg*)0x400A4114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */ 00128 #define REG_UDPHS_EPTCLRSTA0 (*(WoReg*)0x400A4118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */ 00129 #define REG_UDPHS_EPTSTA0 (*(RoReg*)0x400A411CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */ 00130 #define REG_UDPHS_EPTCFG1 (*(RwReg*)0x400A4120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */ 00131 #define REG_UDPHS_EPTCTLENB1 (*(WoReg*)0x400A4124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */ 00132 #define REG_UDPHS_EPTCTLDIS1 (*(WoReg*)0x400A4128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */ 00133 #define REG_UDPHS_EPTCTL1 (*(RoReg*)0x400A412CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */ 00134 #define REG_UDPHS_EPTSETSTA1 (*(WoReg*)0x400A4134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */ 00135 #define REG_UDPHS_EPTCLRSTA1 (*(WoReg*)0x400A4138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */ 00136 #define REG_UDPHS_EPTSTA1 (*(RoReg*)0x400A413CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */ 00137 #define REG_UDPHS_EPTCFG2 (*(RwReg*)0x400A4140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */ 00138 #define REG_UDPHS_EPTCTLENB2 (*(WoReg*)0x400A4144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */ 00139 #define REG_UDPHS_EPTCTLDIS2 (*(WoReg*)0x400A4148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */ 00140 #define REG_UDPHS_EPTCTL2 (*(RoReg*)0x400A414CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */ 00141 #define REG_UDPHS_EPTSETSTA2 (*(WoReg*)0x400A4154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */ 00142 #define REG_UDPHS_EPTCLRSTA2 (*(WoReg*)0x400A4158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */ 00143 #define REG_UDPHS_EPTSTA2 (*(RoReg*)0x400A415CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */ 00144 #define REG_UDPHS_EPTCFG3 (*(RwReg*)0x400A4160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */ 00145 #define REG_UDPHS_EPTCTLENB3 (*(WoReg*)0x400A4164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */ 00146 #define REG_UDPHS_EPTCTLDIS3 (*(WoReg*)0x400A4168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */ 00147 #define REG_UDPHS_EPTCTL3 (*(RoReg*)0x400A416CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */ 00148 #define REG_UDPHS_EPTSETSTA3 (*(WoReg*)0x400A4174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */ 00149 #define REG_UDPHS_EPTCLRSTA3 (*(WoReg*)0x400A4178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */ 00150 #define REG_UDPHS_EPTSTA3 (*(RoReg*)0x400A417CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */ 00151 #define REG_UDPHS_EPTCFG4 (*(RwReg*)0x400A4180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */ 00152 #define REG_UDPHS_EPTCTLENB4 (*(WoReg*)0x400A4184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */ 00153 #define REG_UDPHS_EPTCTLDIS4 (*(WoReg*)0x400A4188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */ 00154 #define REG_UDPHS_EPTCTL4 (*(RoReg*)0x400A418CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */ 00155 #define REG_UDPHS_EPTSETSTA4 (*(WoReg*)0x400A4194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */ 00156 #define REG_UDPHS_EPTCLRSTA4 (*(WoReg*)0x400A4198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */ 00157 #define REG_UDPHS_EPTSTA4 (*(RoReg*)0x400A419CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */ 00158 #define REG_UDPHS_EPTCFG5 (*(RwReg*)0x400A41A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */ 00159 #define REG_UDPHS_EPTCTLENB5 (*(WoReg*)0x400A41A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */ 00160 #define REG_UDPHS_EPTCTLDIS5 (*(WoReg*)0x400A41A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */ 00161 #define REG_UDPHS_EPTCTL5 (*(RoReg*)0x400A41ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */ 00162 #define REG_UDPHS_EPTSETSTA5 (*(WoReg*)0x400A41B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */ 00163 #define REG_UDPHS_EPTCLRSTA5 (*(WoReg*)0x400A41B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */ 00164 #define REG_UDPHS_EPTSTA5 (*(RoReg*)0x400A41BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */ 00165 #define REG_UDPHS_EPTCFG6 (*(RwReg*)0x400A41C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */ 00166 #define REG_UDPHS_EPTCTLENB6 (*(WoReg*)0x400A41C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */ 00167 #define REG_UDPHS_EPTCTLDIS6 (*(WoReg*)0x400A41C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */ 00168 #define REG_UDPHS_EPTCTL6 (*(RoReg*)0x400A41CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */ 00169 #define REG_UDPHS_EPTSETSTA6 (*(WoReg*)0x400A41D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */ 00170 #define REG_UDPHS_EPTCLRSTA6 (*(WoReg*)0x400A41D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */ 00171 #define REG_UDPHS_EPTSTA6 (*(RoReg*)0x400A41DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */ 00172 #define REG_UDPHS_DMANXTDSC0 (*(RwReg*)0x400A4300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */ 00173 #define REG_UDPHS_DMAADDRESS0 (*(RwReg*)0x400A4304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */ 00174 #define REG_UDPHS_DMACONTROL0 (*(RwReg*)0x400A4308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */ 00175 #define REG_UDPHS_DMASTATUS0 (*(RwReg*)0x400A430CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */ 00176 #define REG_UDPHS_DMANXTDSC1 (*(RwReg*)0x400A4310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */ 00177 #define REG_UDPHS_DMAADDRESS1 (*(RwReg*)0x400A4314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */ 00178 #define REG_UDPHS_DMACONTROL1 (*(RwReg*)0x400A4318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */ 00179 #define REG_UDPHS_DMASTATUS1 (*(RwReg*)0x400A431CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */ 00180 #define REG_UDPHS_DMANXTDSC2 (*(RwReg*)0x400A4320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */ 00181 #define REG_UDPHS_DMAADDRESS2 (*(RwReg*)0x400A4324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */ 00182 #define REG_UDPHS_DMACONTROL2 (*(RwReg*)0x400A4328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */ 00183 #define REG_UDPHS_DMASTATUS2 (*(RwReg*)0x400A432CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */ 00184 #define REG_UDPHS_DMANXTDSC3 (*(RwReg*)0x400A4330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */ 00185 #define REG_UDPHS_DMAADDRESS3 (*(RwReg*)0x400A4334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */ 00186 #define REG_UDPHS_DMACONTROL3 (*(RwReg*)0x400A4338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */ 00187 #define REG_UDPHS_DMASTATUS3 (*(RwReg*)0x400A433CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */ 00188 #define REG_UDPHS_DMANXTDSC4 (*(RwReg*)0x400A4340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */ 00189 #define REG_UDPHS_DMAADDRESS4 (*(RwReg*)0x400A4344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */ 00190 #define REG_UDPHS_DMACONTROL4 (*(RwReg*)0x400A4348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */ 00191 #define REG_UDPHS_DMASTATUS4 (*(RwReg*)0x400A434CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */ 00192 #define REG_UDPHS_DMANXTDSC5 (*(RwReg*)0x400A4350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */ 00193 #define REG_UDPHS_DMAADDRESS5 (*(RwReg*)0x400A4354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */ 00194 #define REG_UDPHS_DMACONTROL5 (*(RwReg*)0x400A4358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */ 00195 #define REG_UDPHS_DMASTATUS5 (*(RwReg*)0x400A435CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */ 00196 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 00197 00198 #endif /* _SAM3U_UDPHS_INSTANCE_ */
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