ssc.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) %copyright_year%, Atmel Corporation                                        */
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00010 /* modification, are permitted provided that the following condition is met:    */
00011 /*                                                                              */
00012 /* - Redistributions of source code must retain the above copyright notice,     */
00013 /* this list of conditions and the disclaimer below.                            */
00014 /*                                                                              */
00015 /* Atmel's name may not be used to endorse or promote products derived from     */
00016 /* this software without specific prior written permission.                     */
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00029 
00030 #ifndef _SAM3U_SSC_INSTANCE_
00031 #define _SAM3U_SSC_INSTANCE_
00032 
00033 /* ========== Register definition for SSC peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035 #define REG_SSC_CR            (0x40004000U) /**< \brief (SSC) Control Register */
00036 #define REG_SSC_CMR           (0x40004004U) /**< \brief (SSC) Clock Mode Register */
00037 #define REG_SSC_RCMR          (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
00038 #define REG_SSC_RFMR          (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
00039 #define REG_SSC_TCMR          (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
00040 #define REG_SSC_TFMR          (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
00041 #define REG_SSC_RHR           (0x40004020U) /**< \brief (SSC) Receive Holding Register */
00042 #define REG_SSC_THR           (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
00043 #define REG_SSC_RSHR          (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
00044 #define REG_SSC_TSHR          (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
00045 #define REG_SSC_RC0R          (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
00046 #define REG_SSC_RC1R          (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
00047 #define REG_SSC_SR            (0x40004040U) /**< \brief (SSC) Status Register */
00048 #define REG_SSC_IER           (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
00049 #define REG_SSC_IDR           (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
00050 #define REG_SSC_IMR           (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
00051 #define REG_SSC_WPMR          (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
00052 #define REG_SSC_WPSR          (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
00053 #else
00054 #define REG_SSC_CR   (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */
00055 #define REG_SSC_CMR  (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
00056 #define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
00057 #define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
00058 #define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
00059 #define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
00060 #define REG_SSC_RHR  (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
00061 #define REG_SSC_THR  (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
00062 #define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
00063 #define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
00064 #define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
00065 #define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
00066 #define REG_SSC_SR   (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */
00067 #define REG_SSC_IER  (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
00068 #define REG_SSC_IDR  (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
00069 #define REG_SSC_IMR  (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
00070 #define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
00071 #define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
00072 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00073 
00074 #endif /* _SAM3U_SSC_INSTANCE_ */