spi.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) %copyright_year%, Atmel Corporation                                        */
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00010 /* modification, are permitted provided that the following condition is met:    */
00011 /*                                                                              */
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00013 /* this list of conditions and the disclaimer below.                            */
00014 /*                                                                              */
00015 /* Atmel's name may not be used to endorse or promote products derived from     */
00016 /* this software without specific prior written permission.                     */
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00029 
00030 #ifndef _SAM3U_SPI_INSTANCE_
00031 #define _SAM3U_SPI_INSTANCE_
00032 
00033 /* ========== Register definition for SPI peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035 #define REG_SPI_CR              (0x40008000U) /**< \brief (SPI) Control Register */
00036 #define REG_SPI_MR              (0x40008004U) /**< \brief (SPI) Mode Register */
00037 #define REG_SPI_RDR             (0x40008008U) /**< \brief (SPI) Receive Data Register */
00038 #define REG_SPI_TDR             (0x4000800CU) /**< \brief (SPI) Transmit Data Register */
00039 #define REG_SPI_SR              (0x40008010U) /**< \brief (SPI) Status Register */
00040 #define REG_SPI_IER             (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
00041 #define REG_SPI_IDR             (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
00042 #define REG_SPI_IMR             (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
00043 #define REG_SPI_CSR             (0x40008030U) /**< \brief (SPI) Chip Select Register */
00044 #define REG_SPI_WPMR            (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
00045 #define REG_SPI_WPSR            (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
00046 #else
00047 #define REG_SPI_CR     (*(WoReg*)0x40008000U) /**< \brief (SPI) Control Register */
00048 #define REG_SPI_MR     (*(RwReg*)0x40008004U) /**< \brief (SPI) Mode Register */
00049 #define REG_SPI_RDR    (*(RoReg*)0x40008008U) /**< \brief (SPI) Receive Data Register */
00050 #define REG_SPI_TDR    (*(WoReg*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */
00051 #define REG_SPI_SR     (*(RoReg*)0x40008010U) /**< \brief (SPI) Status Register */
00052 #define REG_SPI_IER    (*(WoReg*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
00053 #define REG_SPI_IDR    (*(WoReg*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
00054 #define REG_SPI_IMR    (*(RoReg*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
00055 #define REG_SPI_CSR    (*(RwReg*)0x40008030U) /**< \brief (SPI) Chip Select Register */
00056 #define REG_SPI_WPMR   (*(RwReg*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
00057 #define REG_SPI_WPSR   (*(RoReg*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
00058 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00059 
00060 #endif /* _SAM3U_SPI_INSTANCE_ */