smc.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) %copyright_year%, Atmel Corporation                                        */
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00011 /*                                                                              */
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00013 /* this list of conditions and the disclaimer below.                            */
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00029 
00030 #ifndef _SAM3U_SMC_INSTANCE_
00031 #define _SAM3U_SMC_INSTANCE_
00032 
00033 /* ========== Register definition for SMC peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035 #define REG_SMC_CFG               (0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
00036 #define REG_SMC_CTRL              (0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
00037 #define REG_SMC_SR                (0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
00038 #define REG_SMC_IER               (0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
00039 #define REG_SMC_IDR               (0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
00040 #define REG_SMC_IMR               (0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
00041 #define REG_SMC_ADDR              (0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
00042 #define REG_SMC_BANK              (0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
00043 #define REG_SMC_ECC_CTRL          (0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
00044 #define REG_SMC_ECC_MD            (0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
00045 #define REG_SMC_ECC_SR1           (0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
00046 #define REG_SMC_ECC_PR0           (0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
00047 #define REG_SMC_ECC_PR1           (0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
00048 #define REG_SMC_ECC_SR2           (0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
00049 #define REG_SMC_ECC_PR2           (0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
00050 #define REG_SMC_ECC_PR3           (0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
00051 #define REG_SMC_ECC_PR4           (0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
00052 #define REG_SMC_ECC_PR5           (0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
00053 #define REG_SMC_ECC_PR6           (0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
00054 #define REG_SMC_ECC_PR7           (0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
00055 #define REG_SMC_ECC_PR8           (0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
00056 #define REG_SMC_ECC_PR9           (0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
00057 #define REG_SMC_ECC_PR10          (0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
00058 #define REG_SMC_ECC_PR11          (0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
00059 #define REG_SMC_ECC_PR12          (0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
00060 #define REG_SMC_ECC_PR13          (0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
00061 #define REG_SMC_ECC_PR14          (0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
00062 #define REG_SMC_ECC_PR15          (0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
00063 #define REG_SMC_SETUP0            (0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
00064 #define REG_SMC_PULSE0            (0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
00065 #define REG_SMC_CYCLE0            (0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
00066 #define REG_SMC_TIMINGS0          (0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
00067 #define REG_SMC_MODE0             (0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
00068 #define REG_SMC_SETUP1            (0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
00069 #define REG_SMC_PULSE1            (0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
00070 #define REG_SMC_CYCLE1            (0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
00071 #define REG_SMC_TIMINGS1          (0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
00072 #define REG_SMC_MODE1             (0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
00073 #define REG_SMC_SETUP2            (0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
00074 #define REG_SMC_PULSE2            (0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
00075 #define REG_SMC_CYCLE2            (0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
00076 #define REG_SMC_TIMINGS2          (0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
00077 #define REG_SMC_MODE2             (0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
00078 #define REG_SMC_SETUP3            (0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
00079 #define REG_SMC_PULSE3            (0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
00080 #define REG_SMC_CYCLE3            (0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
00081 #define REG_SMC_TIMINGS3          (0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
00082 #define REG_SMC_MODE3             (0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
00083 #define REG_SMC_OCMS              (0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
00084 #define REG_SMC_KEY1              (0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
00085 #define REG_SMC_KEY2              (0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
00086 #define REG_SMC_WPCR              (0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
00087 #define REG_SMC_WPSR              (0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
00088 #else
00089 #define REG_SMC_CFG      (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
00090 #define REG_SMC_CTRL     (*(WoReg*)0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
00091 #define REG_SMC_SR       (*(RoReg*)0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
00092 #define REG_SMC_IER      (*(WoReg*)0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
00093 #define REG_SMC_IDR      (*(WoReg*)0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
00094 #define REG_SMC_IMR      (*(RoReg*)0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
00095 #define REG_SMC_ADDR     (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
00096 #define REG_SMC_BANK     (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
00097 #define REG_SMC_ECC_CTRL (*(WoReg*)0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
00098 #define REG_SMC_ECC_MD   (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
00099 #define REG_SMC_ECC_SR1  (*(RoReg*)0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
00100 #define REG_SMC_ECC_PR0  (*(RoReg*)0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
00101 #define REG_SMC_ECC_PR1  (*(RoReg*)0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
00102 #define REG_SMC_ECC_SR2  (*(RoReg*)0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
00103 #define REG_SMC_ECC_PR2  (*(RoReg*)0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
00104 #define REG_SMC_ECC_PR3  (*(RoReg*)0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
00105 #define REG_SMC_ECC_PR4  (*(RoReg*)0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
00106 #define REG_SMC_ECC_PR5  (*(RoReg*)0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
00107 #define REG_SMC_ECC_PR6  (*(RoReg*)0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
00108 #define REG_SMC_ECC_PR7  (*(RoReg*)0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
00109 #define REG_SMC_ECC_PR8  (*(RoReg*)0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
00110 #define REG_SMC_ECC_PR9  (*(RoReg*)0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
00111 #define REG_SMC_ECC_PR10 (*(RoReg*)0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
00112 #define REG_SMC_ECC_PR11 (*(RoReg*)0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
00113 #define REG_SMC_ECC_PR12 (*(RoReg*)0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
00114 #define REG_SMC_ECC_PR13 (*(RoReg*)0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
00115 #define REG_SMC_ECC_PR14 (*(RoReg*)0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
00116 #define REG_SMC_ECC_PR15 (*(RoReg*)0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
00117 #define REG_SMC_SETUP0   (*(RwReg*)0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
00118 #define REG_SMC_PULSE0   (*(RwReg*)0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
00119 #define REG_SMC_CYCLE0   (*(RwReg*)0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
00120 #define REG_SMC_TIMINGS0 (*(RwReg*)0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
00121 #define REG_SMC_MODE0    (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
00122 #define REG_SMC_SETUP1   (*(RwReg*)0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
00123 #define REG_SMC_PULSE1   (*(RwReg*)0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
00124 #define REG_SMC_CYCLE1   (*(RwReg*)0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
00125 #define REG_SMC_TIMINGS1 (*(RwReg*)0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
00126 #define REG_SMC_MODE1    (*(RwReg*)0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
00127 #define REG_SMC_SETUP2   (*(RwReg*)0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
00128 #define REG_SMC_PULSE2   (*(RwReg*)0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
00129 #define REG_SMC_CYCLE2   (*(RwReg*)0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
00130 #define REG_SMC_TIMINGS2 (*(RwReg*)0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
00131 #define REG_SMC_MODE2    (*(RwReg*)0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
00132 #define REG_SMC_SETUP3   (*(RwReg*)0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
00133 #define REG_SMC_PULSE3   (*(RwReg*)0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
00134 #define REG_SMC_CYCLE3   (*(RwReg*)0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
00135 #define REG_SMC_TIMINGS3 (*(RwReg*)0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
00136 #define REG_SMC_MODE3    (*(RwReg*)0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
00137 #define REG_SMC_OCMS     (*(RwReg*)0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
00138 #define REG_SMC_KEY1     (*(WoReg*)0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
00139 #define REG_SMC_KEY2     (*(WoReg*)0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
00140 #define REG_SMC_WPCR     (*(WoReg*)0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
00141 #define REG_SMC_WPSR     (*(RoReg*)0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
00142 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00143 
00144 #endif /* _SAM3U_SMC_INSTANCE_ */