pmc.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) %copyright_year%, Atmel Corporation                                        */
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00011 /*                                                                              */
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00016 /* this software without specific prior written permission.                     */
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00029 
00030 #ifndef _SAM3U_PMC_INSTANCE_
00031 #define _SAM3U_PMC_INSTANCE_
00032 
00033 /* ========== Register definition for PMC peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035 #define REG_PMC_SCER            (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
00036 #define REG_PMC_SCDR            (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
00037 #define REG_PMC_SCSR            (0x400E0408U) /**< \brief (PMC) System Clock Status Register */
00038 #define REG_PMC_PCER0           (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
00039 #define REG_PMC_PCDR0           (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
00040 #define REG_PMC_PCSR0           (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
00041 #define REG_CKGR_UCKR           (0x400E041CU) /**< \brief (PMC) UTMI Clock Register */
00042 #define REG_CKGR_MOR            (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
00043 #define REG_CKGR_MCFR           (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
00044 #define REG_CKGR_PLLAR          (0x400E0428U) /**< \brief (PMC) PLLA Register */
00045 #define REG_PMC_MCKR            (0x400E0430U) /**< \brief (PMC) Master Clock Register */
00046 #define REG_PMC_PCK             (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
00047 #define REG_PMC_IER             (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
00048 #define REG_PMC_IDR             (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
00049 #define REG_PMC_SR              (0x400E0468U) /**< \brief (PMC) Status Register */
00050 #define REG_PMC_IMR             (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
00051 #define REG_PMC_FSMR            (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
00052 #define REG_PMC_FSPR            (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
00053 #define REG_PMC_FOCR            (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
00054 #define REG_PMC_WPMR            (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
00055 #define REG_PMC_WPSR            (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
00056 #else
00057 #define REG_PMC_SCER   (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
00058 #define REG_PMC_SCDR   (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
00059 #define REG_PMC_SCSR   (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */
00060 #define REG_PMC_PCER0  (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
00061 #define REG_PMC_PCDR0  (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
00062 #define REG_PMC_PCSR0  (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
00063 #define REG_CKGR_UCKR  (*(RwReg*)0x400E041CU) /**< \brief (PMC) UTMI Clock Register */
00064 #define REG_CKGR_MOR   (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
00065 #define REG_CKGR_MCFR  (*(RoReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
00066 #define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */
00067 #define REG_PMC_MCKR   (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */
00068 #define REG_PMC_PCK    (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
00069 #define REG_PMC_IER    (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
00070 #define REG_PMC_IDR    (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
00071 #define REG_PMC_SR     (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */
00072 #define REG_PMC_IMR    (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
00073 #define REG_PMC_FSMR   (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
00074 #define REG_PMC_FSPR   (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
00075 #define REG_PMC_FOCR   (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
00076 #define REG_PMC_WPMR   (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
00077 #define REG_PMC_WPSR   (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
00078 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00079 
00080 #endif /* _SAM3U_PMC_INSTANCE_ */