adc.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) %copyright_year%, Atmel Corporation                                        */
00006 /*                                                                              */
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00010 /* modification, are permitted provided that the following condition is met:    */
00011 /*                                                                              */
00012 /* - Redistributions of source code must retain the above copyright notice,     */
00013 /* this list of conditions and the disclaimer below.                            */
00014 /*                                                                              */
00015 /* Atmel's name may not be used to endorse or promote products derived from     */
00016 /* this software without specific prior written permission.                     */
00017 /*                                                                              */
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00028 /* ---------------------------------------------------------------------------- */
00029 
00030 #ifndef _SAM3U_ADC_INSTANCE_
00031 #define _SAM3U_ADC_INSTANCE_
00032 
00033 /* ========== Register definition for ADC peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035 #define REG_ADC_CR              (0x400AC000U) /**< \brief (ADC) Control Register */
00036 #define REG_ADC_MR              (0x400AC004U) /**< \brief (ADC) Mode Register */
00037 #define REG_ADC_CHER            (0x400AC010U) /**< \brief (ADC) Channel Enable Register */
00038 #define REG_ADC_CHDR            (0x400AC014U) /**< \brief (ADC) Channel Disable Register */
00039 #define REG_ADC_CHSR            (0x400AC018U) /**< \brief (ADC) Channel Status Register */
00040 #define REG_ADC_SR              (0x400AC01CU) /**< \brief (ADC) Status Register */
00041 #define REG_ADC_LCDR            (0x400AC020U) /**< \brief (ADC) Last Converted Data Register */
00042 #define REG_ADC_IER             (0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */
00043 #define REG_ADC_IDR             (0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */
00044 #define REG_ADC_IMR             (0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */
00045 #define REG_ADC_CDR             (0x400AC030U) /**< \brief (ADC) Channel Data Register */
00046 #define REG_ADC_RPR             (0x400AC100U) /**< \brief (ADC) Receive Pointer Register */
00047 #define REG_ADC_RCR             (0x400AC104U) /**< \brief (ADC) Receive Counter Register */
00048 #define REG_ADC_RNPR            (0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */
00049 #define REG_ADC_RNCR            (0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */
00050 #define REG_ADC_PTCR            (0x400AC120U) /**< \brief (ADC) Transfer Control Register */
00051 #define REG_ADC_PTSR            (0x400AC124U) /**< \brief (ADC) Transfer Status Register */
00052 #else
00053 #define REG_ADC_CR     (*(WoReg*)0x400AC000U) /**< \brief (ADC) Control Register */
00054 #define REG_ADC_MR     (*(RwReg*)0x400AC004U) /**< \brief (ADC) Mode Register */
00055 #define REG_ADC_CHER   (*(WoReg*)0x400AC010U) /**< \brief (ADC) Channel Enable Register */
00056 #define REG_ADC_CHDR   (*(WoReg*)0x400AC014U) /**< \brief (ADC) Channel Disable Register */
00057 #define REG_ADC_CHSR   (*(RoReg*)0x400AC018U) /**< \brief (ADC) Channel Status Register */
00058 #define REG_ADC_SR     (*(RoReg*)0x400AC01CU) /**< \brief (ADC) Status Register */
00059 #define REG_ADC_LCDR   (*(RoReg*)0x400AC020U) /**< \brief (ADC) Last Converted Data Register */
00060 #define REG_ADC_IER    (*(WoReg*)0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */
00061 #define REG_ADC_IDR    (*(WoReg*)0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */
00062 #define REG_ADC_IMR    (*(RoReg*)0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */
00063 #define REG_ADC_CDR    (*(RoReg*)0x400AC030U) /**< \brief (ADC) Channel Data Register */
00064 #define REG_ADC_RPR    (*(RwReg*)0x400AC100U) /**< \brief (ADC) Receive Pointer Register */
00065 #define REG_ADC_RCR    (*(RwReg*)0x400AC104U) /**< \brief (ADC) Receive Counter Register */
00066 #define REG_ADC_RNPR   (*(RwReg*)0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */
00067 #define REG_ADC_RNCR   (*(RwReg*)0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */
00068 #define REG_ADC_PTCR   (*(WoReg*)0x400AC120U) /**< \brief (ADC) Transfer Control Register */
00069 #define REG_ADC_PTSR   (*(RoReg*)0x400AC124U) /**< \brief (ADC) Transfer Status Register */
00070 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00071 
00072 #endif /* _SAM3U_ADC_INSTANCE_ */