DAP_config.h

00001 /**
00002  * @file    DAP_config.h
00003  * @brief
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 
00023 #ifndef __DAP_CONFIG_H__
00024 #define __DAP_CONFIG_H__
00025 
00026 #include "IO_Config.h"
00027 
00028 //**************************************************************************************************
00029 /**
00030 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
00031 \ingroup DAP_ConfigIO_gr
00032 @{
00033 Provides definitions about:
00034  - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
00035  - Debug Unit communication packet size.
00036  - Debug Access Port communication mode (JTAG or SWD).
00037  - Optional information about a connected Target Device (for Evaluation Boards).
00038 */
00039 
00040 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
00041 /// This value is used to calculate the SWD/JTAG clock speed.
00042 #define CPU_CLOCK               SystemCoreClock        ///< Specifies the CPU Clock in Hz
00043 
00044 /// Number of processor cycles for I/O Port write operations.
00045 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
00046 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
00047 /// requrie 2 processor cycles for a I/O Port Write operation.  If the Debug Unit uses
00048 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
00049 /// requrired.
00050 #define IO_PORT_WRITE_CYCLES    1               ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
00051 
00052 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
00053 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00054 #define DAP_SWD                 1               ///< SWD Mode:  1 = available, 0 = not available
00055 
00056 /// Indicate that JTAG communication mode is available at the Debug Port.
00057 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00058 #define DAP_JTAG                0               ///< JTAG Mode: 1 = available, 0 = not available.
00059 
00060 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
00061 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
00062 #define DAP_JTAG_DEV_CNT        0               ///< Maximum number of JTAG devices on scan chain
00063 
00064 /// Default communication mode on the Debug Access Port.
00065 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
00066 #define DAP_DEFAULT_PORT        1               ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
00067 
00068 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
00069 /// Used to initialize the default SWD/JTAG clock frequency.
00070 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
00071 #define DAP_DEFAULT_SWJ_CLOCK   5000000         ///< Default SWD/JTAG clock frequency in Hz.
00072 
00073 /// Maximum Package Size for Command and Response data.
00074 /// This configuration settings is used to optimized the communication performance with the
00075 /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
00076 #define DAP_PACKET_SIZE         64              ///< USB: 64 = Full-Speed, 1024 = High-Speed.
00077 
00078 /// Maximum Package Buffers for Command and Response data.
00079 /// This configuration settings is used to optimized the communication performance with the
00080 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
00081 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
00082 #define DAP_PACKET_COUNT        5              ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
00083 
00084 /// Indicate that UART Serial Wire Output (SWO) trace is available.
00085 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00086 #define SWO_UART                0               ///< SWO UART:  1 = available, 0 = not available
00087 
00088 /// Maximum SWO UART Baudrate
00089 #define SWO_UART_MAX_BAUDRATE   10000000U       ///< SWO UART Maximum Baudrate in Hz
00090 
00091 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
00092 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00093 #define SWO_MANCHESTER          0               ///< SWO Manchester:  1 = available, 0 = not available
00094 
00095 /// SWO Trace Buffer Size.
00096 #define SWO_BUFFER_SIZE         4096U           ///< SWO Trace Buffer Size in bytes (must be 2^n)
00097 
00098 /// SWO Streaming Trace.
00099 #define SWO_STREAM              0               ///< SWO Streaming Trace: 1 = available, 0 = not available.
00100 
00101 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
00102 #define TIMESTAMP_CLOCK         0U      ///< Timestamp clock in Hz (0 = timestamps not supported).
00103 
00104 
00105 /// Debug Unit is connected to fixed Target Device.
00106 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
00107 /// known device.  In this case a Device Vendor and Device Name string is stored which
00108 /// may be used by the debugger or IDE to configure device parameters.
00109 #define TARGET_DEVICE_FIXED     0               ///< Target Device: 1 = known, 0 = unknown;
00110 
00111 #if TARGET_DEVICE_FIXED
00112 #define TARGET_DEVICE_VENDOR    ""              ///< String indicating the Silicon Vendor
00113 #define TARGET_DEVICE_NAME      ""              ///< String indicating the Target Device
00114 #endif
00115 
00116 ///@}
00117 
00118 //**************************************************************************************************
00119 /**
00120 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
00121 \ingroup DAP_ConfigIO_gr
00122 @{
00123 
00124 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
00125 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
00126 interface of a device. The following I/O Pins are provided:
00127 
00128 JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mode
00129 ---------------------------- | -------------------- | ---------------------------------------------
00130 TCK: Test Clock              | SWCLK: Clock         | Output Push/Pull
00131 TMS: Test Mode Select        | SWDIO: Data I/O      | Output Push/Pull; Input (for receiving data)
00132 TDI: Test Data Input         |                      | Output Push/Pull
00133 TDO: Test Data Output        |                      | Input
00134 nTRST: Test Reset (optional) |                      | Output Open Drain with pull-up resistor
00135 nRESET: Device Reset         | nRESET: Device Reset | Output Open Drain with pull-up resistor
00136 
00137 
00138 DAP Hardware I/O Pin Access Functions
00139 -------------------------------------
00140 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
00141 these I/O Pins.
00142 
00143 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
00144 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
00145 peripherals that can independently write/read a single I/O pin without affecting any other pins
00146 of the same I/O port. The following SWDIO I/O Pin functions are provided:
00147  - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
00148  - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
00149  - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
00150  - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
00151 */
00152 
00153 
00154 // Configure DAP I/O pins ------------------------------
00155 
00156 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
00157 Configures the DAP Hardware I/O pins for JTAG mode:
00158  - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
00159  - TDO to input mode.
00160 */
00161 __STATIC_INLINE void PORT_JTAG_SETUP(void) {}
00162 
00163 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
00164 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
00165  - SWCLK, SWDIO, nRESET to output mode and set to default high level.
00166  - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
00167 */
00168 __STATIC_INLINE void PORT_SWD_SETUP(void)
00169 {
00170     PIN_SWCLK_GPIO->PSOR = PIN_SWCLK;
00171     PIN_SWDIO_GPIO->PSOR = PIN_SWDIO;
00172     PIN_nRESET_GPIO->PSOR = PIN_nRESET;
00173     PIN_SWCLK_GPIO->PDDR |= (PIN_SWCLK);
00174     PIN_SWDIO_GPIO->PDDR |= (PIN_SWDIO);
00175     PIN_nRESET_GPIO->PDDR |= (PIN_nRESET);
00176 }
00177 
00178 /** Disable JTAG/SWD I/O Pins.
00179 Disables the DAP Hardware I/O pins which configures:
00180  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
00181 */
00182 __STATIC_INLINE void PORT_OFF(void)
00183 {
00184     PIN_SWCLK_GPIO->PDDR &= ~(PIN_SWCLK);
00185     PIN_SWDIO_GPIO->PDDR &= ~(PIN_SWDIO);
00186     PIN_nRESET_GPIO->PDDR &= ~(PIN_nRESET);
00187 }
00188 
00189 
00190 // SWCLK/TCK I/O pin -------------------------------------
00191 
00192 /** SWCLK/TCK I/O pin: Get Input.
00193 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
00194 */
00195 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
00196 {
00197     return (PIN_SWCLK_GPIO->PDIR & PIN_SWCLK) ? 1 : 0;
00198 }
00199 
00200 /** SWCLK/TCK I/O pin: Set Output to High.
00201 Set the SWCLK/TCK DAP hardware I/O pin to high level.
00202 */
00203 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_SET(void)
00204 {
00205     PIN_SWCLK_GPIO->PSOR = PIN_SWCLK;
00206 }
00207 
00208 /** SWCLK/TCK I/O pin: Set Output to Low.
00209 Set the SWCLK/TCK DAP hardware I/O pin to low level.
00210 */
00211 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR(void)
00212 {
00213     PIN_SWCLK_GPIO->PCOR = PIN_SWCLK;
00214 }
00215 
00216 
00217 // SWDIO/TMS Pin I/O --------------------------------------
00218 
00219 /** SWDIO/TMS I/O pin: Get Input.
00220 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
00221 */
00222 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
00223 {
00224     return (PIN_SWDIO_GPIO->PDIR & PIN_SWDIO) ? 1 : 0;
00225 }
00226 
00227 /** SWDIO/TMS I/O pin: Set Output to High.
00228 Set the SWDIO/TMS DAP hardware I/O pin to high level.
00229 */
00230 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_SET(void)
00231 {
00232     PIN_SWDIO_GPIO->PSOR = PIN_SWDIO;
00233 }
00234 
00235 /** SWDIO/TMS I/O pin: Set Output to Low.
00236 Set the SWDIO/TMS DAP hardware I/O pin to low level.
00237 */
00238 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_CLR(void)
00239 {
00240     PIN_SWDIO_GPIO->PCOR = PIN_SWDIO;
00241 }
00242 
00243 /** SWDIO I/O pin: Get Input (used in SWD mode only).
00244 \return Current status of the SWDIO DAP hardware I/O pin.
00245 */
00246 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
00247 {
00248     return (PIN_SWDIO_GPIO->PDIR & PIN_SWDIO) ? 1 : 0;
00249 }
00250 
00251 /** SWDIO I/O pin: Set Output (used in SWD mode only).
00252 \param bit Output value for the SWDIO DAP hardware I/O pin.
00253 */
00254 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT(uint32_t bit)
00255 {
00256     if (bit & 0x1) {
00257         PIN_SWDIO_GPIO->PSOR = PIN_SWDIO;
00258     } else {
00259         PIN_SWDIO_GPIO->PCOR = PIN_SWDIO;
00260     }
00261 }
00262 
00263 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
00264 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
00265 called prior \ref PIN_SWDIO_OUT function calls.
00266 */
00267 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_ENABLE(void)
00268 {
00269     PIN_SWDIO_GPIO->PDDR |= PIN_SWDIO;
00270 }
00271 
00272 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
00273 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
00274 called prior \ref PIN_SWDIO_IN function calls.
00275 */
00276 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE(void)
00277 {
00278     PIN_SWDIO_GPIO->PDDR &= ~(PIN_SWDIO);
00279 }
00280 
00281 
00282 // TDI Pin I/O ---------------------------------------------
00283 
00284 /** TDI I/O pin: Get Input.
00285 \return Current status of the TDI DAP hardware I/O pin.
00286 */
00287 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
00288 {
00289     return (0);   // Not available
00290 }
00291 
00292 /** TDI I/O pin: Set Output.
00293 \param bit Output value for the TDI DAP hardware I/O pin.
00294 */
00295 __STATIC_FORCEINLINE void     PIN_TDI_OUT(uint32_t bit)
00296 {
00297     ;             // Not available
00298 }
00299 
00300 
00301 // TDO Pin I/O ---------------------------------------------
00302 
00303 /** TDO I/O pin: Get Input.
00304 \return Current status of the TDO DAP hardware I/O pin.
00305 */
00306 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
00307 {
00308     return (0);   // Not available
00309 }
00310 
00311 
00312 // nTRST Pin I/O -------------------------------------------
00313 
00314 /** nTRST I/O pin: Get Input.
00315 \return Current status of the nTRST DAP hardware I/O pin.
00316 */
00317 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
00318 {
00319     return (0);   // Not available
00320 }
00321 
00322 /** nTRST I/O pin: Set Output.
00323 \param bit JTAG TRST Test Reset pin status:
00324            - 0: issue a JTAG TRST Test Reset.
00325            - 1: release JTAG TRST Test Reset.
00326 */
00327 __STATIC_FORCEINLINE void     PIN_nTRST_OUT(uint32_t bit)
00328 {
00329     ;             // Not available
00330 }
00331 
00332 // nRESET Pin I/O------------------------------------------
00333 
00334 /** nRESET I/O pin: Get Input.
00335 \return Current status of the nRESET DAP hardware I/O pin.
00336 */
00337 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
00338 {
00339     return (PIN_nRESET_GPIO->PDIR & PIN_nRESET) ? 1 : 0;
00340 }
00341 
00342 /** nRESET I/O pin: Set Output.
00343 \param bit target device hardware reset pin status:
00344            - 0: issue a device hardware reset.
00345            - 1: release device hardware reset.
00346 */
00347 __STATIC_FORCEINLINE void     PIN_nRESET_OUT(uint32_t bit)
00348 {
00349     if (bit & 0x1) {
00350         PIN_nRESET_GPIO->PSOR = PIN_nRESET;
00351     } else {
00352         PIN_nRESET_GPIO->PCOR = PIN_nRESET;
00353     }
00354 }
00355 
00356 ///@}
00357 
00358 
00359 //**************************************************************************************************
00360 /**
00361 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
00362 \ingroup DAP_ConfigIO_gr
00363 @{
00364 
00365 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
00366 
00367 It is recommended to provide the following LEDs for status indication:
00368  - Connect LED: is active when the DAP hardware is connected to a debugger.
00369  - Running LED: is active when the debugger has put the target device into running state.
00370 */
00371 
00372 /** Debug Unit: Set status of Connected LED.
00373 \param bit status of the Connect LED.
00374            - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
00375            - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
00376 */
00377 __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
00378 {
00379     ;             // Not available
00380 }
00381 
00382 /** Debug Unit: Set status Target Running LED.
00383 \param bit status of the Target Running LED.
00384            - 1: Target Running LED ON: program execution in target started.
00385            - 0: Target Running LED OFF: program execution in target stopped.
00386 */
00387 __STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit)
00388 {
00389     ;             // Not available
00390 }
00391 
00392 ///@}
00393 
00394 
00395 //**************************************************************************************************
00396 /**
00397 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
00398 \ingroup DAP_ConfigIO_gr
00399 @{
00400 Access function for Test Domain Timer.
00401 
00402 The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
00403 default, the DWT timer is used.  The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
00404 
00405 */
00406 
00407 /** Get timestamp of Test Domain Timer.
00408 \return Current timestamp value.
00409 */
00410 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
00411   return 0;
00412 }
00413 
00414 ///@}
00415 
00416 
00417 //**************************************************************************************************
00418 /**
00419 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
00420 \ingroup DAP_ConfigIO_gr
00421 @{
00422 
00423 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
00424 */
00425 
00426 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
00427 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
00428 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
00429  - I/O clock system enabled.
00430  - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
00431  - for nTRST, nRESET a weak pull-up (if available) is enabled.
00432  - LED output pins are enabled and LEDs are turned off.
00433 */
00434 __STATIC_INLINE void DAP_SETUP(void)
00435 {
00436     SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK |  /* Enable Port A Clock */
00437                   SIM_SCGC5_PORTB_MASK |  /* Enable Port B Clock */
00438                   SIM_SCGC5_PORTC_MASK |  /* Enable Port C Clock */
00439                   SIM_SCGC5_PORTD_MASK |  /* Enable Port D Clock */
00440                   SIM_SCGC5_PORTE_MASK;   /* Enable Port E Clock */
00441     /* Configure I/O pin SWCLK */
00442     PIN_SWCLK_PORT->PCR[PIN_SWCLK_BIT] = PORT_PCR_MUX(1)  | /* GPIO */
00443                                          PORT_PCR_PE_MASK;  /* Pull (Down) enable */
00444     PIN_SWCLK_GPIO->PSOR  = PIN_SWCLK;                      /* High level */
00445     PIN_SWCLK_GPIO->PDDR |= PIN_SWCLK;                      /* Output */
00446     /* Configure I/O pin SWDIO */
00447     PIN_SWDIO_PORT->PCR[PIN_SWDIO_BIT] = PORT_PCR_MUX(1)  |  /* GPIO */
00448                                          PORT_PCR_PE_MASK |  /* Pull enable */
00449                                          PORT_PCR_PS_MASK;   /* Pull-up */
00450     PIN_SWDIO_GPIO->PSOR  = PIN_SWDIO;                       /* High level */
00451     PIN_SWDIO_GPIO->PDDR &= ~(PIN_SWDIO);                    /* Input */
00452     /* Configure I/O pin nRESET */
00453     PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_MUX(1)  |  /* GPIO */
00454                                            PORT_PCR_PE_MASK |  /* Pull enable */
00455                                            PORT_PCR_PS_MASK;   /* Pull-up */
00456     PIN_nRESET_GPIO->PSOR  = PIN_nRESET;                       /* High level */
00457     PIN_nRESET_GPIO->PDDR |= PIN_nRESET;                       /* Output */
00458 }
00459 
00460 /** Reset Target Device with custom specific I/O pin or command sequence.
00461 This function allows the optional implementation of a device specific reset sequence.
00462 It is called when the command \ref DAP_ResetTarget and is for example required
00463 when a device needs a time-critical unlock sequence that enables the debug port.
00464 \return 0 = no device specific reset sequence is implemented.\n
00465         1 = a device specific reset sequence is implemented.
00466 */
00467 __STATIC_INLINE uint32_t RESET_TARGET(void)
00468 {
00469     return (0);              // change to '1' when a device reset sequence is implemented
00470 }
00471 
00472 ///@}
00473 
00474 
00475 #endif /* __DAP_CONFIG_H__ */