DAP_config.h

00001 /**
00002  * @file    DAP_config.h
00003  * @brief
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 #ifndef __DAP_CONFIG_H__
00023 #define __DAP_CONFIG_H__
00024 
00025 #include "IO_Config.h"
00026 
00027 //**************************************************************************************************
00028 /**
00029 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
00030 \ingroup DAP_ConfigIO_gr
00031 @{
00032 Provides definitions about the hardware and configuration of the Debug Unit.
00033 
00034 This information includes:
00035  - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
00036  - Debug Unit communication packet size.
00037  - Debug Access Port communication mode (JTAG or SWD).
00038  - Optional information about a connected Target Device (for Evaluation Boards).
00039 */
00040 
00041 #include "fsl_device_registers.h"                             // Debug Unit Cortex-M Processor Header File
00042 
00043 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
00044 /// This value is used to calculate the SWD/JTAG clock speed.
00045 #define CPU_CLOCK               SystemCoreClock        ///< Specifies the CPU Clock in Hz
00046 
00047 /// Number of processor cycles for I/O Port write operations.
00048 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
00049 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
00050 /// require 2 processor cycles for a I/O Port Write operation.  If the Debug Unit uses
00051 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
00052 /// required.
00053 #define IO_PORT_WRITE_CYCLES    2U              ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
00054 
00055 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
00056 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00057 #define DAP_SWD                 1               ///< SWD Mode:  1 = available, 0 = not available
00058 
00059 /// Indicate that JTAG communication mode is available at the Debug Port.
00060 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00061 #define DAP_JTAG                0               ///< JTAG Mode: 1 = available, 0 = not available.
00062 
00063 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
00064 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
00065 #define DAP_JTAG_DEV_CNT        0               ///< Maximum number of JTAG devices on scan chain
00066 
00067 /// Default communication mode on the Debug Access Port.
00068 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
00069 #define DAP_DEFAULT_PORT        1               ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
00070 
00071 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
00072 /// Used to initialize the default SWD/JTAG clock frequency.
00073 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
00074 #define DAP_DEFAULT_SWJ_CLOCK   4000000         ///< Default SWD/JTAG clock frequency in Hz.
00075 
00076 /// Maximum Package Size for Command and Response data.
00077 /// This configuration settings is used to optimized the communication performance with the
00078 /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
00079 #ifndef HID_ENDPOINT            //HID end points currently set limits to 64
00080 #define DAP_PACKET_SIZE         512              ///< USB: 64 = Full-Speed, 512 = High-Speed.
00081 #else
00082 #define DAP_PACKET_SIZE         64              ///< USB: 64 = Full-Speed, 512 = High-Speed.
00083 #endif
00084 
00085 /// Maximum Package Buffers for Command and Response data.
00086 /// This configuration settings is used to optimized the communication performance with the
00087 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
00088 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
00089 #define DAP_PACKET_COUNT        64U             ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
00090 
00091 /// Indicate that UART Serial Wire Output (SWO) trace is available.
00092 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00093 #define SWO_UART                1               ///< SWO UART:  1 = available, 0 = not available
00094 
00095 /// Maximum SWO UART Baudrate
00096 #define SWO_UART_MAX_BAUDRATE   10000000U       ///< SWO UART Maximum Baudrate in Hz
00097 
00098 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
00099 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00100 #define SWO_MANCHESTER          0               ///< SWO Manchester:  1 = available, 0 = not available
00101 
00102 /// SWO Trace Buffer Size.
00103 #define SWO_BUFFER_SIZE         4096U           ///< SWO Trace Buffer Size in bytes (must be 2^n)
00104 
00105 #define SWO_USART_PORT 1 ///< UART1 is used for the SWO UART.
00106 
00107 /// SWO Streaming Trace.
00108 #define SWO_STREAM              0               ///< SWO Streaming Trace: 1 = available, 0 = not available.
00109 
00110 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
00111 #define TIMESTAMP_CLOCK         1000000U      ///< Timestamp clock in Hz (0 = timestamps not supported).
00112 
00113 /// Debug Unit is connected to fixed Target Device.
00114 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
00115 /// known device.  In this case a Device Vendor and Device Name string is stored which
00116 /// may be used by the debugger or IDE to configure device parameters.
00117 #define TARGET_DEVICE_FIXED     0               ///< Target Device: 1 = known, 0 = unknown;
00118 
00119 #if TARGET_DEVICE_FIXED
00120 #define TARGET_DEVICE_VENDOR    ""              ///< String indicating the Silicon Vendor
00121 #define TARGET_DEVICE_NAME      ""              ///< String indicating the Target Device
00122 #endif
00123 
00124 ///@}
00125 
00126 //**************************************************************************************************
00127 /**
00128 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
00129 \ingroup DAP_ConfigIO_gr
00130 @{
00131 
00132 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
00133 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
00134 interface of a device. The following I/O Pins are provided:
00135 
00136 JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mode
00137 ---------------------------- | -------------------- | ---------------------------------------------
00138 TCK: Test Clock              | SWCLK: Clock         | Output Push/Pull
00139 TMS: Test Mode Select        | SWDIO: Data I/O      | Output Push/Pull; Input (for receiving data)
00140 TDI: Test Data Input         |                      | Output Push/Pull
00141 TDO: Test Data Output        |                      | Input
00142 nTRST: Test Reset (optional) |                      | Output Open Drain with pull-up resistor
00143 nRESET: Device Reset         | nRESET: Device Reset | Output Open Drain with pull-up resistor
00144 
00145 
00146 DAP Hardware I/O Pin Access Functions
00147 -------------------------------------
00148 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
00149 these I/O Pins.
00150 
00151 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
00152 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
00153 peripherals that can independently write/read a single I/O pin without affecting any other pins
00154 of the same I/O port. The following SWDIO I/O Pin functions are provided:
00155  - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
00156  - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
00157  - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
00158  - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
00159 */
00160 
00161 
00162 // Configure DAP I/O pins ------------------------------
00163 
00164 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
00165 Configures the DAP Hardware I/O pins for JTAG mode:
00166  - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
00167  - TDO to input mode.
00168 */
00169 static inline void PORT_JTAG_SETUP(void) {}
00170 
00171 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
00172 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
00173  - SWCLK, SWDIO, nRESET to output mode and set to default high level.
00174  - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
00175 */
00176 static inline void PORT_SWD_SETUP(void)
00177 {
00178     PIN_SWCLK_GPIO->PSOR     = 1 << PIN_SWCLK_BIT;
00179     PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT;
00180     PIN_SWDIO_OE_GPIO->PSOR = 1 << PIN_SWDIO_OE_BIT;
00181     PIN_SWD_OE_GPIO->PSOR   = 1 << PIN_SWD_OE_BIT;
00182     PIN_nRESET_GPIO->PSOR    = 1 << PIN_nRESET_BIT;
00183     PIN_SWD_OE_GPIO->PDDR = PIN_SWD_OE_GPIO->PDDR | (1 << PIN_SWD_OE_BIT);
00184     PIN_nRESET_GPIO->PSOR = PIN_nRESET;
00185     PIN_nRESET_GPIO->PDDR |= PIN_nRESET; //output
00186     PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_MUX(1);
00187 }
00188 
00189 /** Disable JTAG/SWD I/O Pins.
00190 Disables the DAP Hardware I/O pins which configures:
00191  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
00192 */
00193 static inline void PORT_OFF(void)
00194 {
00195     PIN_SWDIO_OE_GPIO->PCOR = 1 << PIN_SWDIO_OE_BIT;
00196     PIN_SWD_OE_GPIO->PCOR   = 1 << PIN_SWD_OE_BIT;
00197     PIN_nRESET_GPIO->PSOR    = 1 << PIN_nRESET_BIT;
00198     PIN_nRESET_GPIO->PDDR &= ~PIN_nRESET; //input
00199     PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] |= PORT_PCR_ISF_MASK;
00200     PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_MUX(1);
00201 }
00202 
00203 
00204 // SWCLK/TCK I/O pin -------------------------------------
00205 
00206 /** SWCLK/TCK I/O pin: Get Input.
00207 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
00208 */
00209 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void)
00210 {
00211     return (0);   // Not available
00212 }
00213 
00214 /** SWCLK/TCK I/O pin: Set Output to High.
00215 Set the SWCLK/TCK DAP hardware I/O pin to high level.
00216 */
00217 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_SET(void)
00218 {
00219     PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT;
00220 }
00221 
00222 /** SWCLK/TCK I/O pin: Set Output to Low.
00223 Set the SWCLK/TCK DAP hardware I/O pin to low level.
00224 */
00225 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR(void)
00226 {
00227     PIN_SWCLK_GPIO->PCOR = 1 << PIN_SWCLK_BIT;
00228 }
00229 
00230 
00231 // SWDIO/TMS Pin I/O --------------------------------------
00232 
00233 /** SWDIO/TMS I/O pin: Get Input.
00234 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
00235 */
00236 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
00237 {
00238     return ((PIN_SWDIO_IN_GPIO->PDIR >> PIN_SWDIO_IN_BIT) & 1);
00239 }
00240 
00241 /** SWDIO/TMS I/O pin: Set Output to High.
00242 Set the SWDIO/TMS DAP hardware I/O pin to high level.
00243 */
00244 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_SET(void)
00245 {
00246     PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT;
00247 }
00248 
00249 /** SWDIO/TMS I/O pin: Set Output to Low.
00250 Set the SWDIO/TMS DAP hardware I/O pin to low level.
00251 */
00252 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_CLR(void)
00253 {
00254     PIN_SWDIO_OUT_GPIO->PCOR = 1 << PIN_SWDIO_OUT_BIT;
00255 }
00256 
00257 /** SWDIO I/O pin: Get Input (used in SWD mode only).
00258 \return Current status of the SWDIO DAP hardware I/O pin.
00259 */
00260 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
00261 {
00262     return (BITBAND_REG(PIN_SWDIO_IN_GPIO->PDIR, PIN_SWDIO_IN_BIT));
00263 }
00264 
00265 /** SWDIO I/O pin: Set Output (used in SWD mode only).
00266 \param bit Output value for the SWDIO DAP hardware I/O pin.
00267 */
00268 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT(uint32_t bit)
00269 {
00270     BITBAND_REG(PIN_SWDIO_OUT_GPIO->PDOR, PIN_SWDIO_OUT_BIT) = bit;
00271 }
00272 
00273 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
00274 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
00275 called prior \ref PIN_SWDIO_OUT function calls.
00276 */
00277 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_ENABLE(void)
00278 {
00279     PIN_SWDIO_OE_GPIO->PSOR = 1 << PIN_SWDIO_OE_BIT;
00280 }
00281 
00282 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
00283 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
00284 called prior \ref PIN_SWDIO_IN function calls.
00285 */
00286 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE(void)
00287 {
00288     PIN_SWDIO_OE_GPIO->PCOR = 1 << PIN_SWDIO_OE_BIT;
00289 }
00290 
00291 
00292 // TDI Pin I/O ---------------------------------------------
00293 
00294 /** TDI I/O pin: Get Input.
00295 \return Current status of the TDI DAP hardware I/O pin.
00296 */
00297 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void)
00298 {
00299     return (0);   // Not available
00300 }
00301 
00302 /** TDI I/O pin: Set Output.
00303 \param bit Output value for the TDI DAP hardware I/O pin.
00304 */
00305 __STATIC_FORCEINLINE void     PIN_TDI_OUT(uint32_t bit)
00306 {
00307     ;             // Not available
00308 }
00309 
00310 
00311 // TDO Pin I/O ---------------------------------------------
00312 
00313 /** TDO I/O pin: Get Input.
00314 \return Current status of the TDO DAP hardware I/O pin.
00315 */
00316 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void)
00317 {
00318     return (0);   // Not available
00319 }
00320 
00321 
00322 // nTRST Pin I/O -------------------------------------------
00323 
00324 /** nTRST I/O pin: Get Input.
00325 \return Current status of the nTRST DAP hardware I/O pin.
00326 */
00327 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void)
00328 {
00329     return (0);   // Not available
00330 }
00331 
00332 /** nTRST I/O pin: Set Output.
00333 \param bit JTAG TRST Test Reset pin status:
00334            - 0: issue a JTAG TRST Test Reset.
00335            - 1: release JTAG TRST Test Reset.
00336 */
00337 __STATIC_FORCEINLINE void     PIN_nTRST_OUT(uint32_t bit)
00338 {
00339     ;             // Not available
00340 }
00341 
00342 // nRESET Pin I/O------------------------------------------
00343 
00344 /** nRESET I/O pin: Get Input.
00345 \return Current status of the nRESET DAP hardware I/O pin.
00346 */
00347 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
00348 {
00349     return ((PIN_nRESET_GPIO->PDIR >> PIN_nRESET_BIT) & 1);
00350 }
00351 
00352 /** nRESET I/O pin: Set Output.
00353 \param bit target device hardware reset pin status:
00354            - 0: issue a device hardware reset.
00355            - 1: release device hardware reset.
00356 */
00357 __STATIC_FORCEINLINE void     PIN_nRESET_OUT(uint32_t bit)
00358 {
00359     BITBAND_REG(PIN_nRESET_GPIO->PDOR, PIN_nRESET_BIT) = bit;
00360 }
00361 
00362 ///@}
00363 
00364 
00365 //**************************************************************************************************
00366 /**
00367 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
00368 \ingroup DAP_ConfigIO_gr
00369 @{
00370 
00371 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
00372 
00373 It is recommended to provide the following LEDs for status indication:
00374  - Connect LED: is active when the DAP hardware is connected to a debugger.
00375  - Running LED: is active when the debugger has put the target device into running state.
00376 */
00377 
00378 /** Debug Unit: Set status of Connected LED.
00379 \param bit status of the Connect LED.
00380            - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
00381            - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
00382 */
00383 static inline void LED_CONNECTED_OUT(uint32_t bit)
00384 {
00385     BITBAND_REG(LED_CONNECTED_GPIO->PDOR, LED_CONNECTED_BIT) = ~bit;
00386 }
00387 
00388 /** Debug Unit: Set status Target Running LED.
00389 \param bit status of the Target Running LED.
00390            - 1: Target Running LED ON: program execution in target started.
00391            - 0: Target Running LED OFF: program execution in target stopped.
00392 */
00393 static inline void LED_RUNNING_OUT(uint32_t bit)
00394 {
00395     ;             // Not available
00396 }
00397 
00398 ///@}
00399 
00400 
00401 //**************************************************************************************************
00402 /**
00403 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
00404 \ingroup DAP_ConfigIO_gr
00405 @{
00406 Access function for Test Domain Timer.
00407 
00408 The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
00409 default, the DWT timer is used.  The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
00410 
00411 */
00412 
00413 /** Get timestamp of Test Domain Timer.
00414 \return Current timestamp value.
00415 */
00416 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
00417   return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
00418 }
00419 
00420 ///@}
00421 
00422 
00423 //**************************************************************************************************
00424 /**
00425 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
00426 \ingroup DAP_ConfigIO_gr
00427 @{
00428 
00429 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
00430 */
00431 
00432 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
00433 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
00434 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
00435  - I/O clock system enabled.
00436  - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
00437  - for nTRST, nRESET a weak pull-up (if available) is enabled.
00438  - LED output pins are enabled and LEDs are turned off.
00439 */
00440 static inline void DAP_SETUP(void)
00441 {
00442     SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK |  /* Enable Port A Clock */
00443                   SIM_SCGC5_PORTB_MASK |  /* Enable Port B Clock */
00444                   SIM_SCGC5_PORTC_MASK |  /* Enable Port C Clock */
00445                   SIM_SCGC5_PORTD_MASK;   /* Enable Port D Clock */
00446     /* Configure I/O pin SWCLK */
00447     PIN_SWCLK_PORT->PCR[PIN_SWCLK_BIT]         = PORT_PCR_MUX(1) |   /* GPIO */
00448              PORT_PCR_DSE_MASK; /* High drive strength */
00449     PIN_SWCLK_GPIO->PSOR  = 1 << PIN_SWCLK_BIT;                      /* High level */
00450     PIN_SWCLK_GPIO->PDDR |= 1 << PIN_SWCLK_BIT;                      /* Output */
00451     /* Configure I/O pin SWDIO_OUT */
00452     PIN_SWDIO_OUT_PORT->PCR[PIN_SWDIO_OUT_BIT] = PORT_PCR_MUX(1) |   /* GPIO */
00453              PORT_PCR_DSE_MASK; /* High drive strength */
00454     PIN_SWDIO_OUT_GPIO->PSOR  = 1 << PIN_SWDIO_OUT_BIT;              /* High level */
00455     PIN_SWDIO_OUT_GPIO->PDDR |= 1 << PIN_SWDIO_OUT_BIT;              /* Output */
00456     /* Configure I/O pin SWDIO_IN */
00457     PIN_SWDIO_IN_PORT->PCR[PIN_SWDIO_IN_BIT]   = PORT_PCR_MUX(1)  |  /* GPIO */
00458             PORT_PCR_PE_MASK |  /* Pull enable */
00459             PORT_PCR_PS_MASK;   /* Pull-up */
00460     PIN_SWDIO_IN_GPIO->PDDR &= ~(1 << PIN_SWDIO_IN_BIT);             /* Input */
00461     /* Configure I/O pin SWDIO_OE */
00462     PIN_SWDIO_OE_PORT->PCR[PIN_SWDIO_OE_BIT] = PORT_PCR_MUX(1) |     /* GPIO */
00463              PORT_PCR_DSE_MASK; /* High drive strength */
00464     PIN_SWDIO_OE_GPIO->PCOR  = 1 << PIN_SWDIO_OE_BIT;                /* Low level */
00465     PIN_SWDIO_OE_GPIO->PDDR |= 1 << PIN_SWDIO_OE_BIT;                /* Output */
00466     /* Configure I/O pin SWD_OE */
00467     PIN_SWD_OE_PORT->PCR[PIN_SWD_OE_BIT]     = PORT_PCR_MUX(1) |     /* GPIO */
00468              PORT_PCR_DSE_MASK; /* High drive strength */
00469     PIN_SWD_OE_GPIO->PCOR  = 1 << PIN_SWD_OE_BIT;                    /* Low level */
00470     PIN_SWD_OE_GPIO->PDDR |= 1 << PIN_SWD_OE_BIT;                    /* Output */
00471     /* Configure I/O pin nRESET */
00472     PIN_nRESET_PORT->PCR[PIN_nRESET_BIT]       = PORT_PCR_MUX(1)  |  /* GPIO */
00473             PORT_PCR_PE_MASK |  /* Pull enable */
00474             PORT_PCR_PS_MASK |  /* Pull-up */
00475             PORT_PCR_ODE_MASK;  /* Open-drain */
00476     PIN_nRESET_GPIO->PSOR  = 1 << PIN_nRESET_BIT;                    /* High level */
00477     PIN_nRESET_GPIO->PDDR &= ~(1 << PIN_nRESET_BIT);                    /* Input */
00478     // Configure I/O pin LVLRST_EN
00479     // The nRESET level translator is enabled by default. The translator is auto-
00480     // direction sensing. So as long as we don't drive nRESET from our side, we won't
00481     // interfere with another debug probe connected to the target SWD header.
00482     PIN_nRESET_EN_PORT->PCR[PIN_nRESET_EN_BIT]       = PORT_PCR_MUX(1)  |  /* GPIO */
00483             PORT_PCR_ODE_MASK;  /* Open-drain */
00484     PIN_nRESET_EN_GPIO->PSOR  = PIN_nRESET_EN;                    /* High level */
00485     PIN_nRESET_EN_GPIO->PDDR |= PIN_nRESET_EN;                    /* Output */
00486     /* Configure LED */
00487     LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1)  |  /* GPIO */
00488             PORT_PCR_ODE_MASK;  /* Open-drain */
00489     LED_CONNECTED_GPIO->PCOR  = 1 << LED_CONNECTED_BIT;              /* Turned on */
00490     LED_CONNECTED_GPIO->PDDR |= 1 << LED_CONNECTED_BIT;              /* Output */
00491 }
00492 
00493 /** Reset Target Device with custom specific I/O pin or command sequence.
00494 This function allows the optional implementation of a device specific reset sequence.
00495 It is called when the command \ref DAP_ResetTarget and is for example required
00496 when a device needs a time-critical unlock sequence that enables the debug port.
00497 \return 0 = no device specific reset sequence is implemented.\n
00498         1 = a device specific reset sequence is implemented.
00499 */
00500 static inline uint32_t RESET_TARGET(void)
00501 {
00502     return (0);              // change to '1' when a device reset sequence is implemented
00503 }
00504 
00505 ///@}
00506 
00507 
00508 #endif /* __DAP_CONFIG_H__ */