DAP_config.h

00001 /*
00002  * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
00003  *
00004  * SPDX-License-Identifier: Apache-2.0
00005  *
00006  * Licensed under the Apache License, Version 2.0 (the License); you may
00007  * not use this file except in compliance with the License.
00008  * You may obtain a copy of the License at
00009  *
00010  * www.apache.org/licenses/LICENSE-2.0
00011  *
00012  * Unless required by applicable law or agreed to in writing, software
00013  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00014  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00015  * See the License for the specific language governing permissions and
00016  * limitations under the License.
00017  *
00018  * ----------------------------------------------------------------------
00019  *
00020  * $Date:        1. December 2017
00021  * $Revision:    V2.0.0
00022  *
00023  * Project:      CMSIS-DAP Configuration
00024  * Title:        DAP_config.h CMSIS-DAP Configuration File (Template)
00025  *
00026  *---------------------------------------------------------------------------*/
00027 
00028 #ifndef __DAP_CONFIG_H__
00029 #define __DAP_CONFIG_H__
00030 
00031 #include "IO_Config.h"
00032 
00033 //**************************************************************************************************
00034 /**
00035 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
00036 \ingroup DAP_ConfigIO_gr
00037 @{
00038 Provides definitions about the hardware and configuration of the Debug Unit.
00039 
00040 This information includes:
00041  - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
00042  - Debug Unit Identification strings (Vendor, Product, Serial Number).
00043  - Debug Unit communication packet size.
00044  - Debug Access Port supported modes and settings (JTAG/SWD and SWO).
00045  - Optional information about a connected Target Device (for Evaluation Boards).
00046 */
00047 
00048 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
00049 /// This value is used to calculate the SWD/JTAG clock speed.
00050 #define CPU_CLOCK               SystemCoreClock        ///< Specifies the CPU Clock in Hz.
00051 
00052 /// Number of processor cycles for I/O Port write operations.
00053 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
00054 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
00055 /// require 2 processor cycles for a I/O Port Write operation.  If the Debug Unit uses
00056 /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
00057 /// required.
00058 #define IO_PORT_WRITE_CYCLES    2U              ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0.
00059 
00060 /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
00061 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00062 #define DAP_SWD                 1               ///< SWD Mode:  1 = available, 0 = not available.
00063 
00064 /// Indicate that JTAG communication mode is available at the Debug Port.
00065 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00066 #define DAP_JTAG                0               ///< JTAG Mode: 1 = available, 0 = not available.
00067 
00068 /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
00069 /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
00070 #define DAP_JTAG_DEV_CNT        0               ///< Maximum number of JTAG devices on scan chain.
00071 
00072 /// Default communication mode on the Debug Access Port.
00073 /// Used for the command \ref DAP_Connect when Port Default mode is selected.
00074 #define DAP_DEFAULT_PORT        1U              ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
00075 
00076 /// Default communication speed on the Debug Access Port for SWD and JTAG mode.
00077 /// Used to initialize the default SWD/JTAG clock frequency.
00078 /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
00079 #define DAP_DEFAULT_SWJ_CLOCK   1000000U        ///< Default SWD/JTAG clock frequency in Hz.
00080 
00081 /// Maximum Package Size for Command and Response data.
00082 /// This configuration settings is used to optimize the communication performance with the
00083 /// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB,
00084 /// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB.
00085 #define DAP_PACKET_SIZE         64U            ///< Specifies Packet Size in bytes.
00086 
00087 /// Maximum Package Buffers for Command and Response data.
00088 /// This configuration settings is used to optimize the communication performance with the
00089 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
00090 /// setting can be reduced (valid range is 1 .. 255).
00091 #define DAP_PACKET_COUNT        5U              ///< Specifies number of packets buffered.
00092 
00093 /// Indicate that UART Serial Wire Output (SWO) trace is available.
00094 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00095 #define SWO_UART                0               ///< SWO UART:  1 = available, 0 = not available.
00096 
00097 /// Maximum SWO UART Baudrate.
00098 #define SWO_UART_MAX_BAUDRATE   10000000U       ///< SWO UART Maximum Baudrate in Hz.
00099 
00100 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
00101 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
00102 #define SWO_MANCHESTER          0               ///< SWO Manchester:  1 = available, 0 = not available.
00103 
00104 /// SWO Trace Buffer Size.
00105 #define SWO_BUFFER_SIZE         4096U           ///< SWO Trace Buffer Size in bytes (must be 2^n).
00106 
00107 /// SWO Streaming Trace.
00108 #define SWO_STREAM              0               ///< SWO Streaming Trace: 1 = available, 0 = not available.
00109 
00110 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
00111 #define TIMESTAMP_CLOCK         1000000U      ///< Timestamp clock in Hz (0 = timestamps not supported).
00112 
00113 /// Debug Unit is connected to fixed Target Device.
00114 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
00115 /// known device.  In this case a Device Vendor and Device Name string is stored which
00116 /// may be used by the debugger or IDE to configure device parameters.
00117 #define TARGET_DEVICE_FIXED     0               ///< Target Device: 1 = known, 0 = unknown;
00118 
00119 #if TARGET_DEVICE_FIXED
00120 #define TARGET_DEVICE_VENDOR    ""              ///< String indicating the Silicon Vendor
00121 #define TARGET_DEVICE_NAME      ""              ///< String indicating the Target Device
00122 #endif
00123 
00124 ///@}
00125 
00126 
00127 //**************************************************************************************************
00128 /**
00129 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
00130 \ingroup DAP_ConfigIO_gr
00131 @{
00132 
00133 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
00134 and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
00135 interface of a device. The following I/O Pins are provided:
00136 
00137 JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mode
00138 ---------------------------- | -------------------- | ---------------------------------------------
00139 TCK: Test Clock              | SWCLK: Clock         | Output Push/Pull
00140 TMS: Test Mode Select        | SWDIO: Data I/O      | Output Push/Pull; Input (for receiving data)
00141 TDI: Test Data Input         |                      | Output Push/Pull
00142 TDO: Test Data Output        |                      | Input
00143 nTRST: Test Reset (optional) |                      | Output Open Drain with pull-up resistor
00144 nRESET: Device Reset         | nRESET: Device Reset | Output Open Drain with pull-up resistor
00145 
00146 
00147 DAP Hardware I/O Pin Access Functions
00148 -------------------------------------
00149 The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
00150 these I/O Pins.
00151 
00152 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
00153 This functions are provided to achieve faster I/O that is possible with some advanced GPIO
00154 peripherals that can independently write/read a single I/O pin without affecting any other pins
00155 of the same I/O port. The following SWDIO I/O Pin functions are provided:
00156  - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
00157  - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
00158  - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
00159  - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
00160 */
00161 
00162 
00163 // Configure DAP I/O pins ------------------------------
00164 
00165 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
00166 Configures the DAP Hardware I/O pins for JTAG mode:
00167  - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
00168  - TDO to input mode.
00169 */
00170 __STATIC_INLINE void PORT_JTAG_SETUP (void) {
00171   ;
00172 }
00173 
00174 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
00175 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
00176  - SWCLK, SWDIO, nRESET to output mode and set to default high level.
00177  - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode).
00178 */
00179 __STATIC_INLINE void PORT_SWD_SETUP(void)
00180 {
00181     PIN_SWCLK_GPIO->PSOR     = 1 << PIN_SWCLK_BIT;
00182     PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT;
00183     PIN_SWDIO_NOE_GPIO->PCOR = 1 << PIN_SWDIO_NOE_BIT;
00184     PIN_SWD_NOE_GPIO->PCOR   = 1 << PIN_SWD_NOE_BIT;
00185     PIN_nRESET_GPIO->PSOR    = 1 << PIN_nRESET_BIT;
00186     PIN_SWD_NOE_GPIO->PDDR = PIN_SWD_NOE_GPIO->PDDR | (1 << PIN_SWD_NOE_BIT);
00187     PIN_SWD_NOE_GPIO->PCOR = 1 << PIN_SWD_NOE_BIT;
00188     PIN_SWDIO_NOE_GPIO->PCOR = 1 << PIN_SWDIO_NOE_BIT;
00189     PIN_nRESET_GPIO->PSOR = PIN_nRESET;
00190     PIN_nRESET_GPIO->PDDR |= PIN_nRESET; //output
00191     PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_MUX(1);
00192 }
00193 
00194 /** Disable JTAG/SWD I/O Pins.
00195 Disables the DAP Hardware I/O pins which configures:
00196  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
00197 */
00198 __STATIC_INLINE void PORT_OFF(void)
00199 {
00200     PIN_SWDIO_NOE_GPIO->PSOR = 1 << PIN_SWDIO_NOE_BIT;
00201     PIN_SWD_NOE_GPIO->PSOR   = 1 << PIN_SWD_NOE_BIT;
00202     PIN_nRESET_GPIO->PSOR    = 1 << PIN_nRESET_BIT;
00203     PIN_nRESET_GPIO->PDDR &= ~PIN_nRESET; //input
00204     PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] |= PORT_PCR_ISF_MASK;
00205     PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_MUX(1);
00206 }
00207 
00208 
00209 // SWCLK/TCK I/O pin -------------------------------------
00210 
00211 /** SWCLK/TCK I/O pin: Get Input.
00212 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
00213 */
00214 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN  (void) {
00215   return (0U);
00216 }
00217 
00218 /** SWCLK/TCK I/O pin: Set Output to High.
00219 Set the SWCLK/TCK DAP hardware I/O pin to high level.
00220 */
00221 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_SET(void)
00222 {
00223     PIN_SWCLK_GPIO->PSOR = 1 << PIN_SWCLK_BIT;
00224 }
00225 
00226 /** SWCLK/TCK I/O pin: Set Output to Low.
00227 Set the SWCLK/TCK DAP hardware I/O pin to low level.
00228 */
00229 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR(void)
00230 {
00231     PIN_SWCLK_GPIO->PCOR = 1 << PIN_SWCLK_BIT;
00232 }
00233 
00234 
00235 // SWDIO/TMS Pin I/O --------------------------------------
00236 
00237 /** SWDIO/TMS I/O pin: Get Input.
00238 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
00239 */
00240 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void)
00241 {
00242     return ((PIN_SWDIO_IN_GPIO->PDIR >> PIN_SWDIO_IN_BIT) & 1);
00243 }
00244 
00245 /** SWDIO/TMS I/O pin: Set Output to High.
00246 Set the SWDIO/TMS DAP hardware I/O pin to high level.
00247 */
00248 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_SET(void)
00249 {
00250     PIN_SWDIO_OUT_GPIO->PSOR = 1 << PIN_SWDIO_OUT_BIT;
00251 }
00252 
00253 /** SWDIO/TMS I/O pin: Set Output to Low.
00254 Set the SWDIO/TMS DAP hardware I/O pin to low level.
00255 */
00256 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_CLR(void)
00257 {
00258     PIN_SWDIO_OUT_GPIO->PCOR = 1 << PIN_SWDIO_OUT_BIT;
00259 }
00260 
00261 /** SWDIO I/O pin: Get Input (used in SWD mode only).
00262 \return Current status of the SWDIO DAP hardware I/O pin.
00263 */
00264 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void)
00265 {
00266     return (BITBAND_REG(PIN_SWDIO_IN_GPIO->PDIR, PIN_SWDIO_IN_BIT));
00267 }
00268 
00269 /** SWDIO I/O pin: Set Output (used in SWD mode only).
00270 \param bit Output value for the SWDIO DAP hardware I/O pin.
00271 */
00272 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT(uint32_t bit)
00273 {
00274     BITBAND_REG(PIN_SWDIO_OUT_GPIO->PDOR, PIN_SWDIO_OUT_BIT) = bit;
00275 }
00276 
00277 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
00278 Configure the SWDIO DAP hardware I/O pin to output mode. This function is
00279 called prior \ref PIN_SWDIO_OUT function calls.
00280 */
00281 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_ENABLE(void)
00282 {
00283     PIN_SWDIO_NOE_GPIO->PCOR = 1 << PIN_SWDIO_NOE_BIT;
00284 }
00285 
00286 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
00287 Configure the SWDIO DAP hardware I/O pin to input mode. This function is
00288 called prior \ref PIN_SWDIO_IN function calls.
00289 */
00290 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE(void)
00291 {
00292     PIN_SWDIO_NOE_GPIO->PSOR = 1 << PIN_SWDIO_NOE_BIT;
00293 }
00294 
00295 
00296 // TDI Pin I/O ---------------------------------------------
00297 
00298 /** TDI I/O pin: Get Input.
00299 \return Current status of the TDI DAP hardware I/O pin.
00300 */
00301 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN  (void) {
00302   return (0U);
00303 }
00304 
00305 /** TDI I/O pin: Set Output.
00306 \param bit Output value for the TDI DAP hardware I/O pin.
00307 */
00308 __STATIC_FORCEINLINE void     PIN_TDI_OUT (uint32_t bit) {
00309   ;
00310 }
00311 
00312 
00313 // TDO Pin I/O ---------------------------------------------
00314 
00315 /** TDO I/O pin: Get Input.
00316 \return Current status of the TDO DAP hardware I/O pin.
00317 */
00318 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN  (void) {
00319   return (0U);
00320 }
00321 
00322 
00323 // nTRST Pin I/O -------------------------------------------
00324 
00325 /** nTRST I/O pin: Get Input.
00326 \return Current status of the nTRST DAP hardware I/O pin.
00327 */
00328 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN   (void) {
00329   return (0U);
00330 }
00331 
00332 /** nTRST I/O pin: Set Output.
00333 \param bit JTAG TRST Test Reset pin status:
00334            - 0: issue a JTAG TRST Test Reset.
00335            - 1: release JTAG TRST Test Reset.
00336 */
00337 __STATIC_FORCEINLINE void     PIN_nTRST_OUT  (uint32_t bit) {
00338   ;
00339 }
00340 
00341 // nRESET Pin I/O------------------------------------------
00342 
00343 /** nRESET I/O pin: Get Input.
00344 \return Current status of the nRESET DAP hardware I/O pin.
00345 */
00346 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void)
00347 {
00348     return ((PIN_nRESET_GPIO->PDIR >> PIN_nRESET_BIT) & 1);
00349 }
00350 
00351 /** nRESET I/O pin: Set Output.
00352 \param bit target device hardware reset pin status:
00353            - 0: issue a device hardware reset.
00354            - 1: release device hardware reset.
00355 */
00356 __STATIC_FORCEINLINE void     PIN_nRESET_OUT(uint32_t bit)
00357 {
00358     BITBAND_REG(PIN_nRESET_GPIO->PDOR, PIN_nRESET_BIT) = bit;
00359 }
00360 
00361 ///@}
00362 
00363 
00364 //**************************************************************************************************
00365 /**
00366 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
00367 \ingroup DAP_ConfigIO_gr
00368 @{
00369 
00370 CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
00371 
00372 It is recommended to provide the following LEDs for status indication:
00373  - Connect LED: is active when the DAP hardware is connected to a debugger.
00374  - Running LED: is active when the debugger has put the target device into running state.
00375 */
00376 
00377 /** Debug Unit: Set status of Connected LED.
00378 \param bit status of the Connect LED.
00379            - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
00380            - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
00381 */
00382 __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
00383 {
00384     BITBAND_REG(LED_CONNECTED_GPIO->PDOR, LED_CONNECTED_BIT) = ~bit;
00385 }
00386 
00387 /** Debug Unit: Set status Target Running LED.
00388 \param bit status of the Target Running LED.
00389            - 1: Target Running LED ON: program execution in target started.
00390            - 0: Target Running LED OFF: program execution in target stopped.
00391 */
00392 __STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {}
00393 
00394 ///@}
00395 
00396 
00397 //**************************************************************************************************
00398 /**
00399 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
00400 \ingroup DAP_ConfigIO_gr
00401 @{
00402 Access function for Test Domain Timer.
00403 
00404 The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
00405 default, the DWT timer is used.  The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
00406 
00407 */
00408 
00409 /** Get timestamp of Test Domain Timer.
00410 \return Current timestamp value.
00411 */
00412 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
00413   return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK);
00414 }
00415 
00416 ///@}
00417 
00418 
00419 //**************************************************************************************************
00420 /**
00421 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
00422 \ingroup DAP_ConfigIO_gr
00423 @{
00424 
00425 CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
00426 */
00427 
00428 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
00429 This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
00430 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
00431  - I/O clock system enabled.
00432  - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
00433  - for nTRST, nRESET a weak pull-up (if available) is enabled.
00434  - LED output pins are enabled and LEDs are turned off.
00435 */
00436 __STATIC_INLINE void DAP_SETUP(void)
00437 {
00438     SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK |  /* Enable Port A Clock */
00439                   SIM_SCGC5_PORTB_MASK |  /* Enable Port B Clock */
00440                   SIM_SCGC5_PORTC_MASK |  /* Enable Port C Clock */
00441                   SIM_SCGC5_PORTD_MASK;   /* Enable Port D Clock */
00442     /* Configure I/O pin SWCLK */
00443     PIN_SWCLK_PORT->PCR[PIN_SWCLK_BIT]         = PORT_PCR_MUX(1) |   /* GPIO */
00444              PORT_PCR_DSE_MASK; /* High drive strength */
00445     PIN_SWCLK_GPIO->PSOR  = 1 << PIN_SWCLK_BIT;                      /* High level */
00446     PIN_SWCLK_GPIO->PDDR |= 1 << PIN_SWCLK_BIT;                      /* Output */
00447     /* Configure I/O pin SWDIO_OUT */
00448     PIN_SWDIO_OUT_PORT->PCR[PIN_SWDIO_OUT_BIT] = PORT_PCR_MUX(1) |   /* GPIO */
00449              PORT_PCR_DSE_MASK; /* High drive strength */
00450     PIN_SWDIO_OUT_GPIO->PSOR  = 1 << PIN_SWDIO_OUT_BIT;              /* High level */
00451     PIN_SWDIO_OUT_GPIO->PDDR |= 1 << PIN_SWDIO_OUT_BIT;              /* Output */
00452     /* Configure I/O pin SWDIO_IN */
00453     PIN_SWDIO_IN_PORT->PCR[PIN_SWDIO_IN_BIT]   = PORT_PCR_MUX(1)  |  /* GPIO */
00454             PORT_PCR_PE_MASK |  /* Pull enable */
00455             PORT_PCR_PS_MASK;   /* Pull-up */
00456     PIN_SWDIO_IN_GPIO->PDDR &= ~(1 << PIN_SWDIO_IN_BIT);             /* Input */
00457     /* Configure I/O pin SWDIO_NOE */
00458     PIN_SWDIO_NOE_PORT->PCR[PIN_SWDIO_NOE_BIT] = PORT_PCR_MUX(1) |   /* GPIO */
00459              PORT_PCR_DSE_MASK; /* High drive strength */
00460     PIN_SWDIO_NOE_GPIO->PSOR  = 1 << PIN_SWDIO_NOE_BIT;              /* High level */
00461     PIN_SWDIO_NOE_GPIO->PDDR |= 1 << PIN_SWDIO_NOE_BIT;              /* Output */
00462     /* Configure I/O pin SWD_NOE */
00463     PIN_SWD_NOE_PORT->PCR[PIN_SWD_NOE_BIT]     = PORT_PCR_MUX(1) |   /* GPIO */
00464              PORT_PCR_DSE_MASK; /* High drive strength */
00465     PIN_SWD_NOE_GPIO->PSOR  = 1 << PIN_SWD_NOE_BIT;                  /* High level */
00466     PIN_SWD_NOE_GPIO->PDDR |= 1 << PIN_SWD_NOE_BIT;                  /* Output */
00467     /* Configure I/O pin nRESET */
00468     PIN_nRESET_PORT->PCR[PIN_nRESET_BIT]       = PORT_PCR_MUX(1)  |  /* GPIO */
00469             PORT_PCR_PE_MASK |  /* Pull enable */
00470             PORT_PCR_PS_MASK |  /* Pull-up */
00471             PORT_PCR_ODE_MASK;  /* Open-drain */
00472     PIN_nRESET_GPIO->PSOR  = 1 << PIN_nRESET_BIT;                    /* High level */
00473     PIN_nRESET_GPIO->PDDR &= ~(1 << PIN_nRESET_BIT);                    /* Input */
00474     /* Configure LED */
00475     LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1)  |  /* GPIO */
00476             PORT_PCR_ODE_MASK;  /* Open-drain */
00477     LED_CONNECTED_GPIO->PCOR  = 1 << LED_CONNECTED_BIT;              /* Turned on */
00478     LED_CONNECTED_GPIO->PDDR |= 1 << LED_CONNECTED_BIT;              /* Output */
00479 }
00480 
00481 /** Reset Target Device with custom specific I/O pin or command sequence.
00482 This function allows the optional implementation of a device specific reset sequence.
00483 It is called when the command \ref DAP_ResetTarget and is for example required
00484 when a device needs a time-critical unlock sequence that enables the debug port.
00485 \return 0 = no device specific reset sequence is implemented.\n
00486         1 = a device specific reset sequence is implemented.
00487 */
00488 __STATIC_INLINE uint8_t RESET_TARGET (void) {
00489   return (0U);             // change to '1' when a device reset sequence is implemented
00490 }
00491 
00492 ///@}
00493 
00494 
00495 #endif /* __DAP_CONFIG_H__ */