fpu_enable.c

00001 /***********************************************************************
00002  * $Id: fpu_enable.c
00003  *
00004  * Project: LPC43xx
00005  *
00006  * Description: fpu initialization routine
00007  *
00008  * Copyright(C) 2011, NXP Semiconductor
00009  * All rights reserved.
00010  *
00011  ***********************************************************************
00012  * Software that is described herein is for illustrative purposes only
00013  * which provides customers with programming information regarding the
00014  * products. This software is supplied "AS IS" without any warranties.
00015  * NXP Semiconductors assumes no responsibility or liability for the
00016  * use of the software, conveys no license or title under any patent,
00017  * copyright, or mask work right to the product. NXP Semiconductors
00018  * reserves the right to make changes in the software without
00019  * notification. NXP Semiconductors also make no representation or
00020  * warranty that such application will be suitable for the specified
00021  * use without further testing or modification.
00022  **********************************************************************/
00023 
00024 #define LPC_CPACR           0xE000ED88
00025 
00026 #define SCB_MVFR0           0xE000EF40
00027 #define SCB_MVFR0_RESET     0x10110021
00028 
00029 #define SCB_MVFR1           0xE000EF44
00030 #define SCB_MVFR1_RESET     0x11000011
00031 
00032 #include "stdint.h"
00033 
00034 void fpuEnable(void)
00035 {
00036     /* from arm trm manual, howto enable the FPU :
00037         ; CPACR is located at address 0xE000ED88
00038         LDR.W R0, =0xE000ED88
00039         ; Read CPACR
00040         LDR R1, [R0]
00041         ; Set bits 20-23 to enable CP10 and CP11 coprocessors
00042         ORR R1, R1, #(0xF << 20)
00043         ; Write back the modified value to the CPACR
00044         STR R1, [R0]
00045     */
00046     volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
00047     volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
00048     volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
00049     volatile uint32_t Cpacr;
00050     volatile uint32_t Mvfr0;
00051     volatile uint32_t Mvfr1;
00052     char vfpPresent = 0;
00053     Mvfr0 = *regMvfr0;
00054     Mvfr1 = *regMvfr1;
00055     vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
00056 
00057     /* enable the FPU if present on target */
00058     if (vfpPresent) {
00059         Cpacr = *regCpacr;
00060         Cpacr |= (0xF << 20);
00061         *regCpacr = Cpacr;   // enable CP10 and CP11 for full access
00062     }
00063 }
00064 
00065