debug_cm.h

00001 /**
00002  * @file    debug_cm.h
00003  * @brief   Access to ARM DAP (Cortex-M) using CMSIS-DAP protocol
00004  *
00005  * DAPLink Interface Firmware
00006  * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
00007  * SPDX-License-Identifier: Apache-2.0
00008  *
00009  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00010  * not use this file except in compliance with the License.
00011  * You may obtain a copy of the License at
00012  *
00013  * http://www.apache.org/licenses/LICENSE-2.0
00014  *
00015  * Unless required by applicable law or agreed to in writing, software
00016  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00017  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00018  * See the License for the specific language governing permissions and
00019  * limitations under the License.
00020  */
00021 
00022 #ifndef DEBUG_CM_H
00023 #define DEBUG_CM_H
00024 
00025 #include "DAP.h"
00026 
00027 // SWD register access
00028 #define SWD_REG_AP        (1)
00029 #define SWD_REG_DP        (0)
00030 #define SWD_REG_R         (1<<1)
00031 #define SWD_REG_W         (0<<1)
00032 #define SWD_REG_ADR(a)    (a & 0x0c)
00033 
00034 // Abort Register definitions
00035 #define DAPABORT       0x00000001  // DAP Abort
00036 #define STKCMPCLR      0x00000002  // Clear STICKYCMP Flag (SW Only)
00037 #define STKERRCLR      0x00000004  // Clear STICKYERR Flag (SW Only)
00038 #define WDERRCLR       0x00000008  // Clear WDATAERR Flag (SW Only)
00039 #define ORUNERRCLR     0x00000010  // Clear STICKYORUN Flag (SW Only)
00040 
00041 // Debug Control and Status definitions
00042 #define ORUNDETECT     0x00000001  // Overrun Detect
00043 #define STICKYORUN     0x00000002  // Sticky Overrun
00044 #define TRNMODE        0x0000000C  // Transfer Mode Mask
00045 #define TRNNORMAL      0x00000000  // Transfer Mode: Normal
00046 #define TRNVERIFY      0x00000004  // Transfer Mode: Pushed Verify
00047 #define TRNCOMPARE     0x00000008  // Transfer Mode: Pushed Compare
00048 #define STICKYCMP      0x00000010  // Sticky Compare
00049 #define STICKYERR      0x00000020  // Sticky Error
00050 #define READOK         0x00000040  // Read OK (SW Only)
00051 #define WDATAERR       0x00000080  // Write Data Error (SW Only)
00052 #define MASKLANE       0x00000F00  // Mask Lane Mask
00053 #define MASKLANE0      0x00000100  // Mask Lane 0
00054 #define MASKLANE1      0x00000200  // Mask Lane 1
00055 #define MASKLANE2      0x00000400  // Mask Lane 2
00056 #define MASKLANE3      0x00000800  // Mask Lane 3
00057 #define TRNCNT         0x001FF000  // Transaction Counter Mask
00058 #define CDBGRSTREQ     0x04000000  // Debug Reset Request
00059 #define CDBGRSTACK     0x08000000  // Debug Reset Acknowledge
00060 #define CDBGPWRUPREQ   0x10000000  // Debug Power-up Request
00061 #define CDBGPWRUPACK   0x20000000  // Debug Power-up Acknowledge
00062 #define CSYSPWRUPREQ   0x40000000  // System Power-up Request
00063 #define CSYSPWRUPACK   0x80000000  // System Power-up Acknowledge
00064 
00065 // Debug Select Register definitions
00066 #define CTRLSEL        0x00000001  // CTRLSEL (SW Only)
00067 #define APBANKSEL      0x000000F0  // APBANKSEL Mask
00068 #define APSEL          0xFF000000  // APSEL Mask
00069 
00070 // Access Port Register Addresses
00071 #define AP_CSW         0x00        // Control and Status Word
00072 #define AP_TAR         0x04        // Transfer Address
00073 #define AP_DRW         0x0C        // Data Read/Write
00074 #define AP_BD0         0x10        // Banked Data 0
00075 #define AP_BD1         0x14        // Banked Data 1
00076 #define AP_BD2         0x18        // Banked Data 2
00077 #define AP_BD3         0x1C        // Banked Data 3
00078 #define AP_ROM         0xF8        // Debug ROM Address
00079 #define AP_IDR         0xFC        // Identification Register
00080 
00081 // AP Control and Status Word definitions
00082 #define CSW_SIZE       0x00000007  // Access Size: Selection Mask
00083 #define CSW_SIZE8      0x00000000  // Access Size: 8-bit
00084 #define CSW_SIZE16     0x00000001  // Access Size: 16-bit
00085 #define CSW_SIZE32     0x00000002  // Access Size: 32-bit
00086 #define CSW_ADDRINC    0x00000030  // Auto Address Increment Mask
00087 #define CSW_NADDRINC   0x00000000  // No Address Increment
00088 #define CSW_SADDRINC   0x00000010  // Single Address Increment
00089 #define CSW_PADDRINC   0x00000020  // Packed Address Increment
00090 #define CSW_DBGSTAT    0x00000040  // Debug Status
00091 #define CSW_TINPROG    0x00000080  // Transfer in progress
00092 #define CSW_HPROT      0x02000000  // User/Privilege Control
00093 #define CSW_MSTRTYPE   0x20000000  // Master Type Mask
00094 #define CSW_MSTRCORE   0x00000000  // Master Type: Core
00095 #define CSW_MSTRDBG    0x20000000  // Master Type: Debug
00096 #define CSW_RESERVED   0x01000000  // Reserved Value
00097 
00098 // Core Debug Register Address Offsets
00099 #define DBG_OFS        0x0DF0      // Debug Register Offset inside NVIC
00100 #define DBG_HCSR_OFS   0x00        // Debug Halting Control & Status Register
00101 #define DBG_CRSR_OFS   0x04        // Debug Core Register Selector Register
00102 #define DBG_CRDR_OFS   0x08        // Debug Core Register Data Register
00103 #define DBG_EMCR_OFS   0x0C        // Debug Exception & Monitor Control Register
00104 
00105 // Core Debug Register Addresses
00106 #define DBG_HCSR       (DBG_Addr + DBG_HCSR_OFS)
00107 #define DBG_CRSR       (DBG_Addr + DBG_CRSR_OFS)
00108 #define DBG_CRDR       (DBG_Addr + DBG_CRDR_OFS)
00109 #define DBG_EMCR       (DBG_Addr + DBG_EMCR_OFS)
00110 
00111 // Debug Halting Control and Status Register definitions
00112 #define C_DEBUGEN      0x00000001  // Debug Enable
00113 #define C_HALT         0x00000002  // Halt
00114 #define C_STEP         0x00000004  // Step
00115 #define C_MASKINTS     0x00000008  // Mask Interrupts
00116 #define C_SNAPSTALL    0x00000020  // Snap Stall
00117 #define S_REGRDY       0x00010000  // Register R/W Ready Flag
00118 #define S_HALT         0x00020000  // Halt Flag
00119 #define S_SLEEP        0x00040000  // Sleep Flag
00120 #define S_LOCKUP       0x00080000  // Lockup Flag
00121 #define S_RETIRE_ST    0x01000000  // Sticky Retire Flag
00122 #define S_RESET_ST     0x02000000  // Sticky Reset Flag
00123 #define DBGKEY         0xA05F0000  // Debug Key
00124 
00125 // Debug Exception and Monitor Control Register definitions
00126 #define VC_CORERESET   0x00000001  // Reset Vector Catch
00127 #define VC_MMERR       0x00000010  // Debug Trap on MMU Fault
00128 #define VC_NOCPERR     0x00000020  // Debug Trap on No Coprocessor Fault
00129 #define VC_CHKERR      0x00000040  // Debug Trap on Checking Error Fault
00130 #define VC_STATERR     0x00000080  // Debug Trap on State Error Fault
00131 #define VC_BUSERR      0x00000100  // Debug Trap on Bus Error Fault
00132 #define VC_INTERR      0x00000200  // Debug Trap on Interrupt Error Fault
00133 #define VC_HARDERR     0x00000400  // Debug Trap on Hard Fault
00134 #define MON_EN         0x00010000  // Monitor Enable
00135 #define MON_PEND       0x00020000  // Monitor Pend
00136 #define MON_STEP       0x00040000  // Monitor Step
00137 #define MON_REQ        0x00080000  // Monitor Request
00138 #define TRCENA         0x01000000  // Trace Enable (DWT, ITM, ETM, TPIU)
00139 
00140 // NVIC: Interrupt Controller Type Register
00141 #define NVIC_ICT       (NVIC_Addr + 0x0004)
00142 #define INTLINESNUM    0x0000001F  // Interrupt Line Numbers
00143 
00144 // NVIC: CPUID Base Register
00145 #define NVIC_CPUID     (NVIC_Addr + 0x0D00)
00146 #define CPUID_PARTNO   0x0000FFF0  // Part Number Mask
00147 #define CPUID_REVISION 0x0000000F  // Revision Mask
00148 #define CPUID_VARIANT  0x00F00000  // Variant Mask
00149 
00150 // NVIC: Application Interrupt/Reset Control Register
00151 #define NVIC_AIRCR     (NVIC_Addr + 0x0D0C)
00152 #define VECTRESET      0x00000001  // Reset Cortex-M (except Debug)
00153 #define VECTCLRACTIVE  0x00000002  // Clear Active Vector Bit
00154 #define SYSRESETREQ    0x00000004  // Reset System (except Debug)
00155 #define VECTKEY        0x05FA0000  // Write Key
00156 
00157 // NVIC: Debug Fault Status Register
00158 #define NVIC_DFSR      (NVIC_Addr + 0x0D30)
00159 #define HALTED         0x00000001  // Halt Flag
00160 #define BKPT           0x00000002  // BKPT Flag
00161 #define DWTTRAP        0x00000004  // DWT Match
00162 #define VCATCH         0x00000008  // Vector Catch Flag
00163 #define EXTERNAL       0x00000010  // External Debug Request
00164 
00165 // Data Watchpoint and Trace unit
00166 #define DWT_PCSR       0xe000101c  // DWT PC Sampling Register
00167 
00168 #endif