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core_cm7.h
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00001 /**************************************************************************//** 00002 * @file core_cm7.h 00003 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File 00004 * @version V5.1.2 00005 * @date 19. August 2019 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__clang__) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_CM7_H_GENERIC 00032 #define __CORE_CM7_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup Cortex_M7 00060 @{ 00061 */ 00062 00063 #include "cmsis_version.h" 00064 00065 /* CMSIS CM7 definitions */ 00066 #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 00067 #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 00068 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ 00069 __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 00070 00071 #define __CORTEX_M (7U) /*!< Cortex-M Core */ 00072 00073 /** __FPU_USED indicates whether an FPU is used or not. 00074 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 00075 */ 00076 #if defined ( __CC_ARM ) 00077 #if defined __TARGET_FPU_VFP 00078 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00079 #define __FPU_USED 1U 00080 #else 00081 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00082 #define __FPU_USED 0U 00083 #endif 00084 #else 00085 #define __FPU_USED 0U 00086 #endif 00087 00088 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00089 #if defined __ARM_FP 00090 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00091 #define __FPU_USED 1U 00092 #else 00093 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00094 #define __FPU_USED 0U 00095 #endif 00096 #else 00097 #define __FPU_USED 0U 00098 #endif 00099 00100 #elif defined ( __GNUC__ ) 00101 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00103 #define __FPU_USED 1U 00104 #else 00105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00106 #define __FPU_USED 0U 00107 #endif 00108 #else 00109 #define __FPU_USED 0U 00110 #endif 00111 00112 #elif defined ( __ICCARM__ ) 00113 #if defined __ARMVFP__ 00114 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00115 #define __FPU_USED 1U 00116 #else 00117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00118 #define __FPU_USED 0U 00119 #endif 00120 #else 00121 #define __FPU_USED 0U 00122 #endif 00123 00124 #elif defined ( __TI_ARM__ ) 00125 #if defined __TI_VFP_SUPPORT__ 00126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00127 #define __FPU_USED 1U 00128 #else 00129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00130 #define __FPU_USED 0U 00131 #endif 00132 #else 00133 #define __FPU_USED 0U 00134 #endif 00135 00136 #elif defined ( __TASKING__ ) 00137 #if defined __FPU_VFP__ 00138 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00139 #define __FPU_USED 1U 00140 #else 00141 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00142 #define __FPU_USED 0U 00143 #endif 00144 #else 00145 #define __FPU_USED 0U 00146 #endif 00147 00148 #elif defined ( __CSMC__ ) 00149 #if ( __CSMC__ & 0x400U) 00150 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00151 #define __FPU_USED 1U 00152 #else 00153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00154 #define __FPU_USED 0U 00155 #endif 00156 #else 00157 #define __FPU_USED 0U 00158 #endif 00159 00160 #endif 00161 00162 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00163 00164 00165 #ifdef __cplusplus 00166 } 00167 #endif 00168 00169 #endif /* __CORE_CM7_H_GENERIC */ 00170 00171 #ifndef __CMSIS_GENERIC 00172 00173 #ifndef __CORE_CM7_H_DEPENDANT 00174 #define __CORE_CM7_H_DEPENDANT 00175 00176 #ifdef __cplusplus 00177 extern "C" { 00178 #endif 00179 00180 /* check device defines and use defaults */ 00181 #if defined __CHECK_DEVICE_DEFINES 00182 #ifndef __CM7_REV 00183 #define __CM7_REV 0x0000U 00184 #warning "__CM7_REV not defined in device header file; using default!" 00185 #endif 00186 00187 #ifndef __FPU_PRESENT 00188 #define __FPU_PRESENT 0U 00189 #warning "__FPU_PRESENT not defined in device header file; using default!" 00190 #endif 00191 00192 #ifndef __MPU_PRESENT 00193 #define __MPU_PRESENT 0U 00194 #warning "__MPU_PRESENT not defined in device header file; using default!" 00195 #endif 00196 00197 #ifndef __ICACHE_PRESENT 00198 #define __ICACHE_PRESENT 0U 00199 #warning "__ICACHE_PRESENT not defined in device header file; using default!" 00200 #endif 00201 00202 #ifndef __DCACHE_PRESENT 00203 #define __DCACHE_PRESENT 0U 00204 #warning "__DCACHE_PRESENT not defined in device header file; using default!" 00205 #endif 00206 00207 #ifndef __DTCM_PRESENT 00208 #define __DTCM_PRESENT 0U 00209 #warning "__DTCM_PRESENT not defined in device header file; using default!" 00210 #endif 00211 00212 #ifndef __NVIC_PRIO_BITS 00213 #define __NVIC_PRIO_BITS 3U 00214 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00215 #endif 00216 00217 #ifndef __Vendor_SysTickConfig 00218 #define __Vendor_SysTickConfig 0U 00219 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00220 #endif 00221 #endif 00222 00223 /* IO definitions (access restrictions to peripheral registers) */ 00224 /** 00225 \defgroup CMSIS_glob_defs CMSIS Global Defines 00226 00227 <strong>IO Type Qualifiers</strong> are used 00228 \li to specify the access to peripheral variables. 00229 \li for automatic generation of peripheral register debug information. 00230 */ 00231 #ifdef __cplusplus 00232 #define __I volatile /*!< Defines 'read only' permissions */ 00233 #else 00234 #define __I volatile const /*!< Defines 'read only' permissions */ 00235 #endif 00236 #define __O volatile /*!< Defines 'write only' permissions */ 00237 #define __IO volatile /*!< Defines 'read / write' permissions */ 00238 00239 /* following defines should be used for structure members */ 00240 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00241 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00242 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00243 00244 /*@} end of group Cortex_M7 */ 00245 00246 00247 00248 /******************************************************************************* 00249 * Register Abstraction 00250 Core Register contain: 00251 - Core Register 00252 - Core NVIC Register 00253 - Core SCB Register 00254 - Core SysTick Register 00255 - Core Debug Register 00256 - Core MPU Register 00257 - Core FPU Register 00258 ******************************************************************************/ 00259 /** 00260 \defgroup CMSIS_core_register Defines and Type Definitions 00261 \brief Type definitions and defines for Cortex-M processor based devices. 00262 */ 00263 00264 /** 00265 \ingroup CMSIS_core_register 00266 \defgroup CMSIS_CORE Status and Control Registers 00267 \brief Core Register type definitions. 00268 @{ 00269 */ 00270 00271 /** 00272 \brief Union type to access the Application Program Status Register (APSR). 00273 */ 00274 typedef union 00275 { 00276 struct 00277 { 00278 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00279 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00280 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00281 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00282 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00283 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00284 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00285 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00286 } b; /*!< Structure used for bit access */ 00287 uint32_t w; /*!< Type used for word access */ 00288 } APSR_Type; 00289 00290 /* APSR Register Definitions */ 00291 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00292 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00293 00294 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00295 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00296 00297 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00298 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00299 00300 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00301 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00302 00303 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 00304 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 00305 00306 #define APSR_GE_Pos 16U /*!< APSR: GE Position */ 00307 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ 00308 00309 00310 /** 00311 \brief Union type to access the Interrupt Program Status Register (IPSR). 00312 */ 00313 typedef union 00314 { 00315 struct 00316 { 00317 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00318 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00319 } b; /*!< Structure used for bit access */ 00320 uint32_t w; /*!< Type used for word access */ 00321 } IPSR_Type; 00322 00323 /* IPSR Register Definitions */ 00324 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00325 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00326 00327 00328 /** 00329 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00330 */ 00331 typedef union 00332 { 00333 struct 00334 { 00335 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00336 uint32_t _reserved0:1; /*!< bit: 9 Reserved */ 00337 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ 00338 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00339 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00340 uint32_t T:1; /*!< bit: 24 Thumb bit */ 00341 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ 00342 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00343 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00344 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00345 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00346 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00347 } b; /*!< Structure used for bit access */ 00348 uint32_t w; /*!< Type used for word access */ 00349 } xPSR_Type; 00350 00351 /* xPSR Register Definitions */ 00352 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00353 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00354 00355 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00356 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00357 00358 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00359 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00360 00361 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00362 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00363 00364 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 00365 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 00366 00367 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ 00368 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ 00369 00370 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00371 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00372 00373 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ 00374 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ 00375 00376 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ 00377 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ 00378 00379 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00380 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00381 00382 00383 /** 00384 \brief Union type to access the Control Registers (CONTROL). 00385 */ 00386 typedef union 00387 { 00388 struct 00389 { 00390 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00391 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00392 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00393 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00394 } b; /*!< Structure used for bit access */ 00395 uint32_t w; /*!< Type used for word access */ 00396 } CONTROL_Type; 00397 00398 /* CONTROL Register Definitions */ 00399 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ 00400 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ 00401 00402 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00403 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00404 00405 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 00406 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00407 00408 /*@} end of group CMSIS_CORE */ 00409 00410 00411 /** 00412 \ingroup CMSIS_core_register 00413 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00414 \brief Type definitions for the NVIC Registers 00415 @{ 00416 */ 00417 00418 /** 00419 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00420 */ 00421 typedef struct 00422 { 00423 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00424 uint32_t RESERVED0[24U]; 00425 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00426 uint32_t RESERVED1[24U]; 00427 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00428 uint32_t RESERVED2[24U]; 00429 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00430 uint32_t RESERVED3[24U]; 00431 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00432 uint32_t RESERVED4[56U]; 00433 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 00434 uint32_t RESERVED5[644U]; 00435 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 00436 } NVIC_Type; 00437 00438 /* Software Triggered Interrupt Register Definitions */ 00439 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 00440 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 00441 00442 /*@} end of group CMSIS_NVIC */ 00443 00444 00445 /** 00446 \ingroup CMSIS_core_register 00447 \defgroup CMSIS_SCB System Control Block (SCB) 00448 \brief Type definitions for the System Control Block Registers 00449 @{ 00450 */ 00451 00452 /** 00453 \brief Structure type to access the System Control Block (SCB). 00454 */ 00455 typedef struct 00456 { 00457 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00458 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00459 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00460 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00461 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00462 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00463 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 00464 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00465 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 00466 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 00467 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 00468 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 00469 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 00470 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 00471 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 00472 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 00473 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 00474 __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 00475 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 00476 uint32_t RESERVED0[1U]; 00477 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 00478 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 00479 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ 00480 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ 00481 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 00482 uint32_t RESERVED3[93U]; 00483 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 00484 uint32_t RESERVED4[15U]; 00485 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ 00486 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ 00487 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ 00488 uint32_t RESERVED5[1U]; 00489 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 00490 uint32_t RESERVED6[1U]; 00491 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 00492 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 00493 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 00494 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 00495 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 00496 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ 00497 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ 00498 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ 00499 uint32_t RESERVED7[6U]; 00500 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ 00501 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ 00502 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ 00503 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ 00504 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ 00505 uint32_t RESERVED8[1U]; 00506 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ 00507 } SCB_Type; 00508 00509 /* SCB CPUID Register Definitions */ 00510 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00511 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00512 00513 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00514 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00515 00516 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00517 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00518 00519 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00520 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00521 00522 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00523 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00524 00525 /* SCB Interrupt Control State Register Definitions */ 00526 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 00527 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00528 00529 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00530 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00531 00532 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00533 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00534 00535 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00536 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00537 00538 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00539 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00540 00541 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00542 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00543 00544 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00545 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00546 00547 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00548 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00549 00550 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 00551 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00552 00553 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00554 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00555 00556 /* SCB Vector Table Offset Register Definitions */ 00557 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00558 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00559 00560 /* SCB Application Interrupt and Reset Control Register Definitions */ 00561 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00562 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00563 00564 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00565 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00566 00567 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00568 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00569 00570 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 00571 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 00572 00573 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00574 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00575 00576 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00577 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00578 00579 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ 00580 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ 00581 00582 /* SCB System Control Register Definitions */ 00583 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00584 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00585 00586 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00587 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00588 00589 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00590 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00591 00592 /* SCB Configuration Control Register Definitions */ 00593 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ 00594 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ 00595 00596 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ 00597 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ 00598 00599 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ 00600 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ 00601 00602 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 00603 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00604 00605 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 00606 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00607 00608 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 00609 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00610 00611 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00612 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00613 00614 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 00615 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00616 00617 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ 00618 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ 00619 00620 /* SCB System Handler Control and State Register Definitions */ 00621 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 00622 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 00623 00624 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 00625 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 00626 00627 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 00628 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 00629 00630 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00631 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00632 00633 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 00634 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 00635 00636 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 00637 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 00638 00639 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 00640 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 00641 00642 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 00643 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00644 00645 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 00646 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00647 00648 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 00649 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 00650 00651 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 00652 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00653 00654 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 00655 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 00656 00657 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 00658 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 00659 00660 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 00661 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 00662 00663 /* SCB Configurable Fault Status Register Definitions */ 00664 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 00665 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 00666 00667 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 00668 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 00669 00670 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 00671 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 00672 00673 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 00674 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 00675 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 00676 00677 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ 00678 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ 00679 00680 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 00681 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 00682 00683 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 00684 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 00685 00686 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 00687 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 00688 00689 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 00690 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 00691 00692 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 00693 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 00694 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 00695 00696 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ 00697 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ 00698 00699 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 00700 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 00701 00702 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 00703 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 00704 00705 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 00706 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 00707 00708 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 00709 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 00710 00711 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 00712 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 00713 00714 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 00715 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 00716 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 00717 00718 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 00719 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 00720 00721 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 00722 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 00723 00724 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 00725 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 00726 00727 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 00728 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 00729 00730 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 00731 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 00732 00733 /* SCB Hard Fault Status Register Definitions */ 00734 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 00735 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 00736 00737 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 00738 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 00739 00740 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 00741 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 00742 00743 /* SCB Debug Fault Status Register Definitions */ 00744 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 00745 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 00746 00747 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 00748 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 00749 00750 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 00751 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 00752 00753 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 00754 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 00755 00756 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 00757 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 00758 00759 /* SCB Cache Level ID Register Definitions */ 00760 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ 00761 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ 00762 00763 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ 00764 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ 00765 00766 /* SCB Cache Type Register Definitions */ 00767 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ 00768 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ 00769 00770 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ 00771 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ 00772 00773 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ 00774 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ 00775 00776 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ 00777 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ 00778 00779 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ 00780 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ 00781 00782 /* SCB Cache Size ID Register Definitions */ 00783 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ 00784 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 00785 00786 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ 00787 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 00788 00789 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ 00790 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 00791 00792 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ 00793 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 00794 00795 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ 00796 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ 00797 00798 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ 00799 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ 00800 00801 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ 00802 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ 00803 00804 /* SCB Cache Size Selection Register Definitions */ 00805 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ 00806 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ 00807 00808 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ 00809 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ 00810 00811 /* SCB Software Triggered Interrupt Register Definitions */ 00812 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ 00813 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ 00814 00815 /* SCB D-Cache Invalidate by Set-way Register Definitions */ 00816 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ 00817 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ 00818 00819 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ 00820 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ 00821 00822 /* SCB D-Cache Clean by Set-way Register Definitions */ 00823 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ 00824 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ 00825 00826 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ 00827 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ 00828 00829 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ 00830 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ 00831 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ 00832 00833 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ 00834 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ 00835 00836 /* Instruction Tightly-Coupled Memory Control Register Definitions */ 00837 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ 00838 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ 00839 00840 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ 00841 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ 00842 00843 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ 00844 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ 00845 00846 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ 00847 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ 00848 00849 /* Data Tightly-Coupled Memory Control Register Definitions */ 00850 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ 00851 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ 00852 00853 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ 00854 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ 00855 00856 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ 00857 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ 00858 00859 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ 00860 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ 00861 00862 /* AHBP Control Register Definitions */ 00863 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ 00864 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ 00865 00866 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ 00867 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ 00868 00869 /* L1 Cache Control Register Definitions */ 00870 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ 00871 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ 00872 00873 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ 00874 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ 00875 00876 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ 00877 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ 00878 00879 /* AHBS Control Register Definitions */ 00880 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ 00881 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ 00882 00883 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ 00884 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ 00885 00886 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ 00887 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ 00888 00889 /* Auxiliary Bus Fault Status Register Definitions */ 00890 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ 00891 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ 00892 00893 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ 00894 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ 00895 00896 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ 00897 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ 00898 00899 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ 00900 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ 00901 00902 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ 00903 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ 00904 00905 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ 00906 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ 00907 00908 /*@} end of group CMSIS_SCB */ 00909 00910 00911 /** 00912 \ingroup CMSIS_core_register 00913 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00914 \brief Type definitions for the System Control and ID Register not in the SCB 00915 @{ 00916 */ 00917 00918 /** 00919 \brief Structure type to access the System Control and ID Register not in the SCB. 00920 */ 00921 typedef struct 00922 { 00923 uint32_t RESERVED0[1U]; 00924 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 00925 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00926 } SCnSCB_Type; 00927 00928 /* Interrupt Controller Type Register Definitions */ 00929 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 00930 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 00931 00932 /* Auxiliary Control Register Definitions */ 00933 #define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ 00934 #define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ 00935 00936 #define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ 00937 #define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ 00938 00939 #define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ 00940 #define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ 00941 00942 #define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ 00943 #define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ 00944 00945 #define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ 00946 #define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ 00947 00948 #define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ 00949 #define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ 00950 00951 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ 00952 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ 00953 00954 #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ 00955 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ 00956 00957 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ 00958 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ 00959 00960 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ 00961 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 00962 00963 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ 00964 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 00965 00966 /*@} end of group CMSIS_SCnotSCB */ 00967 00968 00969 /** 00970 \ingroup CMSIS_core_register 00971 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00972 \brief Type definitions for the System Timer Registers. 00973 @{ 00974 */ 00975 00976 /** 00977 \brief Structure type to access the System Timer (SysTick). 00978 */ 00979 typedef struct 00980 { 00981 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00982 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00983 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00984 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00985 } SysTick_Type; 00986 00987 /* SysTick Control / Status Register Definitions */ 00988 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 00989 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00990 00991 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 00992 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00993 00994 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 00995 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00996 00997 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 00998 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00999 01000 /* SysTick Reload Register Definitions */ 01001 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 01002 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 01003 01004 /* SysTick Current Register Definitions */ 01005 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 01006 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 01007 01008 /* SysTick Calibration Register Definitions */ 01009 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 01010 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 01011 01012 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 01013 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 01014 01015 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 01016 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 01017 01018 /*@} end of group CMSIS_SysTick */ 01019 01020 01021 /** 01022 \ingroup CMSIS_core_register 01023 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 01024 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 01025 @{ 01026 */ 01027 01028 /** 01029 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 01030 */ 01031 typedef struct 01032 { 01033 __OM union 01034 { 01035 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 01036 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 01037 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 01038 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 01039 uint32_t RESERVED0[864U]; 01040 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 01041 uint32_t RESERVED1[15U]; 01042 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 01043 uint32_t RESERVED2[15U]; 01044 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 01045 uint32_t RESERVED3[32U]; 01046 uint32_t RESERVED4[43U]; 01047 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 01048 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 01049 uint32_t RESERVED5[6U]; 01050 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 01051 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 01052 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 01053 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 01054 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 01055 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 01056 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 01057 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 01058 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 01059 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 01060 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 01061 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 01062 } ITM_Type; 01063 01064 /* ITM Trace Privilege Register Definitions */ 01065 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 01066 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 01067 01068 /* ITM Trace Control Register Definitions */ 01069 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 01070 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 01071 01072 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ 01073 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 01074 01075 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 01076 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 01077 01078 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ 01079 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 01080 01081 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 01082 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 01083 01084 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 01085 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 01086 01087 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 01088 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 01089 01090 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 01091 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 01092 01093 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 01094 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 01095 01096 /* ITM Lock Status Register Definitions */ 01097 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 01098 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 01099 01100 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 01101 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 01102 01103 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 01104 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 01105 01106 /*@}*/ /* end of group CMSIS_ITM */ 01107 01108 01109 /** 01110 \ingroup CMSIS_core_register 01111 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 01112 \brief Type definitions for the Data Watchpoint and Trace (DWT) 01113 @{ 01114 */ 01115 01116 /** 01117 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 01118 */ 01119 typedef struct 01120 { 01121 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 01122 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 01123 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 01124 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 01125 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 01126 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 01127 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 01128 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 01129 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 01130 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 01131 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 01132 uint32_t RESERVED0[1U]; 01133 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 01134 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 01135 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 01136 uint32_t RESERVED1[1U]; 01137 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 01138 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 01139 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 01140 uint32_t RESERVED2[1U]; 01141 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 01142 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 01143 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 01144 uint32_t RESERVED3[981U]; 01145 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ 01146 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ 01147 } DWT_Type; 01148 01149 /* DWT Control Register Definitions */ 01150 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 01151 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 01152 01153 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 01154 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 01155 01156 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 01157 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 01158 01159 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 01160 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 01161 01162 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 01163 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 01164 01165 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 01166 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 01167 01168 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 01169 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 01170 01171 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 01172 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 01173 01174 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 01175 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 01176 01177 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 01178 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 01179 01180 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 01181 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 01182 01183 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 01184 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 01185 01186 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 01187 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 01188 01189 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 01190 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 01191 01192 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 01193 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 01194 01195 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 01196 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 01197 01198 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 01199 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 01200 01201 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 01202 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 01203 01204 /* DWT CPI Count Register Definitions */ 01205 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 01206 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 01207 01208 /* DWT Exception Overhead Count Register Definitions */ 01209 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 01210 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 01211 01212 /* DWT Sleep Count Register Definitions */ 01213 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 01214 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 01215 01216 /* DWT LSU Count Register Definitions */ 01217 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 01218 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 01219 01220 /* DWT Folded-instruction Count Register Definitions */ 01221 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 01222 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 01223 01224 /* DWT Comparator Mask Register Definitions */ 01225 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ 01226 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ 01227 01228 /* DWT Comparator Function Register Definitions */ 01229 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 01230 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 01231 01232 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ 01233 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 01234 01235 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ 01236 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 01237 01238 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 01239 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 01240 01241 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ 01242 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 01243 01244 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ 01245 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 01246 01247 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ 01248 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 01249 01250 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ 01251 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 01252 01253 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ 01254 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ 01255 01256 /*@}*/ /* end of group CMSIS_DWT */ 01257 01258 01259 /** 01260 \ingroup CMSIS_core_register 01261 \defgroup CMSIS_TPI Trace Port Interface (TPI) 01262 \brief Type definitions for the Trace Port Interface (TPI) 01263 @{ 01264 */ 01265 01266 /** 01267 \brief Structure type to access the Trace Port Interface Register (TPI). 01268 */ 01269 typedef struct 01270 { 01271 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 01272 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 01273 uint32_t RESERVED0[2U]; 01274 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 01275 uint32_t RESERVED1[55U]; 01276 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 01277 uint32_t RESERVED2[131U]; 01278 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 01279 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 01280 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 01281 uint32_t RESERVED3[759U]; 01282 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 01283 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 01284 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 01285 uint32_t RESERVED4[1U]; 01286 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 01287 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 01288 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 01289 uint32_t RESERVED5[39U]; 01290 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 01291 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 01292 uint32_t RESERVED7[8U]; 01293 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 01294 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 01295 } TPI_Type; 01296 01297 /* TPI Asynchronous Clock Prescaler Register Definitions */ 01298 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ 01299 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 01300 01301 /* TPI Selected Pin Protocol Register Definitions */ 01302 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 01303 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 01304 01305 /* TPI Formatter and Flush Status Register Definitions */ 01306 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 01307 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 01308 01309 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 01310 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 01311 01312 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 01313 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 01314 01315 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 01316 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 01317 01318 /* TPI Formatter and Flush Control Register Definitions */ 01319 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 01320 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 01321 01322 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 01323 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 01324 01325 /* TPI TRIGGER Register Definitions */ 01326 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 01327 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 01328 01329 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 01330 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ 01331 #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 01332 01333 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ 01334 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 01335 01336 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ 01337 #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 01338 01339 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ 01340 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 01341 01342 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ 01343 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 01344 01345 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ 01346 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 01347 01348 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ 01349 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 01350 01351 /* TPI ITATBCTR2 Register Definitions */ 01352 #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ 01353 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ 01354 01355 #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ 01356 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ 01357 01358 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 01359 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ 01360 #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 01361 01362 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ 01363 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 01364 01365 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ 01366 #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 01367 01368 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ 01369 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 01370 01371 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ 01372 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 01373 01374 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ 01375 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 01376 01377 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ 01378 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 01379 01380 /* TPI ITATBCTR0 Register Definitions */ 01381 #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ 01382 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ 01383 01384 #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ 01385 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ 01386 01387 /* TPI Integration Mode Control Register Definitions */ 01388 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 01389 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 01390 01391 /* TPI DEVID Register Definitions */ 01392 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 01393 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 01394 01395 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 01396 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 01397 01398 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 01399 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 01400 01401 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ 01402 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 01403 01404 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ 01405 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 01406 01407 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 01408 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 01409 01410 /* TPI DEVTYPE Register Definitions */ 01411 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 01412 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 01413 01414 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 01415 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 01416 01417 /*@}*/ /* end of group CMSIS_TPI */ 01418 01419 01420 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01421 /** 01422 \ingroup CMSIS_core_register 01423 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 01424 \brief Type definitions for the Memory Protection Unit (MPU) 01425 @{ 01426 */ 01427 01428 /** 01429 \brief Structure type to access the Memory Protection Unit (MPU). 01430 */ 01431 typedef struct 01432 { 01433 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 01434 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 01435 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 01436 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 01437 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 01438 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 01439 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 01440 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 01441 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 01442 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 01443 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 01444 } MPU_Type; 01445 01446 #define MPU_TYPE_RALIASES 4U 01447 01448 /* MPU Type Register Definitions */ 01449 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 01450 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 01451 01452 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 01453 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 01454 01455 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 01456 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 01457 01458 /* MPU Control Register Definitions */ 01459 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 01460 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 01461 01462 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 01463 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 01464 01465 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 01466 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 01467 01468 /* MPU Region Number Register Definitions */ 01469 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 01470 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 01471 01472 /* MPU Region Base Address Register Definitions */ 01473 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ 01474 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 01475 01476 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 01477 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 01478 01479 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 01480 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 01481 01482 /* MPU Region Attribute and Size Register Definitions */ 01483 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 01484 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 01485 01486 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 01487 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 01488 01489 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 01490 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 01491 01492 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 01493 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 01494 01495 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 01496 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 01497 01498 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 01499 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 01500 01501 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 01502 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 01503 01504 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 01505 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 01506 01507 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 01508 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 01509 01510 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 01511 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 01512 01513 /*@} end of group CMSIS_MPU */ 01514 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ 01515 01516 01517 /** 01518 \ingroup CMSIS_core_register 01519 \defgroup CMSIS_FPU Floating Point Unit (FPU) 01520 \brief Type definitions for the Floating Point Unit (FPU) 01521 @{ 01522 */ 01523 01524 /** 01525 \brief Structure type to access the Floating Point Unit (FPU). 01526 */ 01527 typedef struct 01528 { 01529 uint32_t RESERVED0[1U]; 01530 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 01531 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 01532 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 01533 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 01534 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 01535 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ 01536 } FPU_Type; 01537 01538 /* Floating-Point Context Control Register Definitions */ 01539 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 01540 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 01541 01542 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 01543 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 01544 01545 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ 01546 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 01547 01548 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ 01549 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 01550 01551 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ 01552 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 01553 01554 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ 01555 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 01556 01557 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ 01558 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 01559 01560 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ 01561 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 01562 01563 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ 01564 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ 01565 01566 /* Floating-Point Context Address Register Definitions */ 01567 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ 01568 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 01569 01570 /* Floating-Point Default Status Control Register Definitions */ 01571 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ 01572 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 01573 01574 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ 01575 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 01576 01577 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ 01578 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 01579 01580 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ 01581 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 01582 01583 /* Media and FP Feature Register 0 Definitions */ 01584 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ 01585 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ 01586 01587 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ 01588 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ 01589 01590 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ 01591 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ 01592 01593 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ 01594 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ 01595 01596 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ 01597 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ 01598 01599 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ 01600 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ 01601 01602 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ 01603 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ 01604 01605 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ 01606 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ 01607 01608 /* Media and FP Feature Register 1 Definitions */ 01609 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ 01610 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ 01611 01612 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 01613 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 01614 01615 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ 01616 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 01617 01618 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ 01619 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ 01620 01621 /* Media and FP Feature Register 2 Definitions */ 01622 01623 #define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ 01624 #define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ 01625 01626 /*@} end of group CMSIS_FPU */ 01627 01628 01629 /** 01630 \ingroup CMSIS_core_register 01631 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01632 \brief Type definitions for the Core Debug Registers 01633 @{ 01634 */ 01635 01636 /** 01637 \brief Structure type to access the Core Debug Register (CoreDebug). 01638 */ 01639 typedef struct 01640 { 01641 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01642 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01643 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01644 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01645 } CoreDebug_Type; 01646 01647 /* Debug Halting Control and Status Register Definitions */ 01648 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 01649 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01650 01651 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01652 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01653 01654 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01655 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01656 01657 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01658 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01659 01660 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 01661 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01662 01663 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 01664 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01665 01666 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 01667 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01668 01669 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 01670 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 01671 01672 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01673 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01674 01675 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 01676 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01677 01678 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 01679 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01680 01681 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01682 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01683 01684 /* Debug Core Register Selector Register Definitions */ 01685 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 01686 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01687 01688 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 01689 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 01690 01691 /* Debug Exception and Monitor Control Register Definitions */ 01692 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ 01693 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 01694 01695 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ 01696 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 01697 01698 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ 01699 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 01700 01701 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ 01702 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 01703 01704 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ 01705 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 01706 01707 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01708 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01709 01710 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ 01711 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 01712 01713 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ 01714 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 01715 01716 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ 01717 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 01718 01719 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ 01720 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 01721 01722 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 01723 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 01724 01725 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ 01726 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 01727 01728 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01729 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01730 01731 /*@} end of group CMSIS_CoreDebug */ 01732 01733 01734 /** 01735 \ingroup CMSIS_core_register 01736 \defgroup CMSIS_core_bitfield Core register bit field macros 01737 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 01738 @{ 01739 */ 01740 01741 /** 01742 \brief Mask and shift a bit field value for use in a register bit range. 01743 \param[in] field Name of the register bit field. 01744 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 01745 \return Masked and shifted value. 01746 */ 01747 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 01748 01749 /** 01750 \brief Mask and shift a register value to extract a bit filed value. 01751 \param[in] field Name of the register bit field. 01752 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 01753 \return Masked and shifted bit field value. 01754 */ 01755 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 01756 01757 /*@} end of group CMSIS_core_bitfield */ 01758 01759 01760 /** 01761 \ingroup CMSIS_core_register 01762 \defgroup CMSIS_core_base Core Definitions 01763 \brief Definitions for base addresses, unions, and structures. 01764 @{ 01765 */ 01766 01767 /* Memory mapping of Core Hardware */ 01768 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01769 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 01770 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01771 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01772 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01773 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01774 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01775 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01776 01777 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 01778 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01779 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01780 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01781 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 01782 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01783 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01784 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 01785 01786 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01787 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01788 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01789 #endif 01790 01791 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 01792 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 01793 01794 /*@} */ 01795 01796 01797 01798 /******************************************************************************* 01799 * Hardware Abstraction Layer 01800 Core Function Interface contains: 01801 - Core NVIC Functions 01802 - Core SysTick Functions 01803 - Core Debug Functions 01804 - Core Register Access Functions 01805 ******************************************************************************/ 01806 /** 01807 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 01808 */ 01809 01810 01811 01812 /* ########################## NVIC functions #################################### */ 01813 /** 01814 \ingroup CMSIS_Core_FunctionInterface 01815 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 01816 \brief Functions that manage interrupts and exceptions via the NVIC. 01817 @{ 01818 */ 01819 01820 #ifdef CMSIS_NVIC_VIRTUAL 01821 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 01822 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 01823 #endif 01824 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 01825 #else 01826 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 01827 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 01828 #define NVIC_EnableIRQ __NVIC_EnableIRQ 01829 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 01830 #define NVIC_DisableIRQ __NVIC_DisableIRQ 01831 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 01832 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 01833 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 01834 #define NVIC_GetActive __NVIC_GetActive 01835 #define NVIC_SetPriority __NVIC_SetPriority 01836 #define NVIC_GetPriority __NVIC_GetPriority 01837 #define NVIC_SystemReset __NVIC_SystemReset 01838 #endif /* CMSIS_NVIC_VIRTUAL */ 01839 01840 #ifdef CMSIS_VECTAB_VIRTUAL 01841 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01842 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 01843 #endif 01844 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01845 #else 01846 #define NVIC_SetVector __NVIC_SetVector 01847 #define NVIC_GetVector __NVIC_GetVector 01848 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 01849 01850 #define NVIC_USER_IRQ_OFFSET 16 01851 01852 01853 /* The following EXC_RETURN values are saved the LR on exception entry */ 01854 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ 01855 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ 01856 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ 01857 #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ 01858 #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ 01859 #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ 01860 01861 01862 /** 01863 \brief Set Priority Grouping 01864 \details Sets the priority grouping field using the required unlock sequence. 01865 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 01866 Only values from 0..7 are used. 01867 In case of a conflict between priority grouping and available 01868 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01869 \param [in] PriorityGroup Priority grouping field. 01870 */ 01871 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 01872 { 01873 uint32_t reg_value; 01874 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01875 01876 reg_value = SCB->AIRCR; /* read old register configuration */ 01877 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 01878 reg_value = (reg_value | 01879 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01880 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 01881 SCB->AIRCR = reg_value; 01882 } 01883 01884 01885 /** 01886 \brief Get Priority Grouping 01887 \details Reads the priority grouping field from the NVIC Interrupt Controller. 01888 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 01889 */ 01890 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 01891 { 01892 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 01893 } 01894 01895 01896 /** 01897 \brief Enable Interrupt 01898 \details Enables a device specific interrupt in the NVIC interrupt controller. 01899 \param [in] IRQn Device specific interrupt number. 01900 \note IRQn must not be negative. 01901 */ 01902 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 01903 { 01904 if ((int32_t)(IRQn) >= 0) 01905 { 01906 __COMPILER_BARRIER(); 01907 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01908 __COMPILER_BARRIER(); 01909 } 01910 } 01911 01912 01913 /** 01914 \brief Get Interrupt Enable status 01915 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 01916 \param [in] IRQn Device specific interrupt number. 01917 \return 0 Interrupt is not enabled. 01918 \return 1 Interrupt is enabled. 01919 \note IRQn must not be negative. 01920 */ 01921 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 01922 { 01923 if ((int32_t)(IRQn) >= 0) 01924 { 01925 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01926 } 01927 else 01928 { 01929 return(0U); 01930 } 01931 } 01932 01933 01934 /** 01935 \brief Disable Interrupt 01936 \details Disables a device specific interrupt in the NVIC interrupt controller. 01937 \param [in] IRQn Device specific interrupt number. 01938 \note IRQn must not be negative. 01939 */ 01940 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 01941 { 01942 if ((int32_t)(IRQn) >= 0) 01943 { 01944 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01945 __DSB(); 01946 __ISB(); 01947 } 01948 } 01949 01950 01951 /** 01952 \brief Get Pending Interrupt 01953 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 01954 \param [in] IRQn Device specific interrupt number. 01955 \return 0 Interrupt status is not pending. 01956 \return 1 Interrupt status is pending. 01957 \note IRQn must not be negative. 01958 */ 01959 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 01960 { 01961 if ((int32_t)(IRQn) >= 0) 01962 { 01963 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01964 } 01965 else 01966 { 01967 return(0U); 01968 } 01969 } 01970 01971 01972 /** 01973 \brief Set Pending Interrupt 01974 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 01975 \param [in] IRQn Device specific interrupt number. 01976 \note IRQn must not be negative. 01977 */ 01978 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 01979 { 01980 if ((int32_t)(IRQn) >= 0) 01981 { 01982 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01983 } 01984 } 01985 01986 01987 /** 01988 \brief Clear Pending Interrupt 01989 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 01990 \param [in] IRQn Device specific interrupt number. 01991 \note IRQn must not be negative. 01992 */ 01993 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01994 { 01995 if ((int32_t)(IRQn) >= 0) 01996 { 01997 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 01998 } 01999 } 02000 02001 02002 /** 02003 \brief Get Active Interrupt 02004 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 02005 \param [in] IRQn Device specific interrupt number. 02006 \return 0 Interrupt status is not active. 02007 \return 1 Interrupt status is active. 02008 \note IRQn must not be negative. 02009 */ 02010 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 02011 { 02012 if ((int32_t)(IRQn) >= 0) 02013 { 02014 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02015 } 02016 else 02017 { 02018 return(0U); 02019 } 02020 } 02021 02022 02023 /** 02024 \brief Set Interrupt Priority 02025 \details Sets the priority of a device specific interrupt or a processor exception. 02026 The interrupt number can be positive to specify a device specific interrupt, 02027 or negative to specify a processor exception. 02028 \param [in] IRQn Interrupt number. 02029 \param [in] priority Priority to set. 02030 \note The priority cannot be set for every processor exception. 02031 */ 02032 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 02033 { 02034 if ((int32_t)(IRQn) >= 0) 02035 { 02036 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02037 } 02038 else 02039 { 02040 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02041 } 02042 } 02043 02044 02045 /** 02046 \brief Get Interrupt Priority 02047 \details Reads the priority of a device specific interrupt or a processor exception. 02048 The interrupt number can be positive to specify a device specific interrupt, 02049 or negative to specify a processor exception. 02050 \param [in] IRQn Interrupt number. 02051 \return Interrupt Priority. 02052 Value is aligned automatically to the implemented priority bits of the microcontroller. 02053 */ 02054 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 02055 { 02056 02057 if ((int32_t)(IRQn) >= 0) 02058 { 02059 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 02060 } 02061 else 02062 { 02063 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 02064 } 02065 } 02066 02067 02068 /** 02069 \brief Encode Priority 02070 \details Encodes the priority for an interrupt with the given priority group, 02071 preemptive priority value, and subpriority value. 02072 In case of a conflict between priority grouping and available 02073 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 02074 \param [in] PriorityGroup Used priority group. 02075 \param [in] PreemptPriority Preemptive priority value (starting from 0). 02076 \param [in] SubPriority Subpriority value (starting from 0). 02077 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 02078 */ 02079 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 02080 { 02081 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02082 uint32_t PreemptPriorityBits; 02083 uint32_t SubPriorityBits; 02084 02085 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 02086 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 02087 02088 return ( 02089 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 02090 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 02091 ); 02092 } 02093 02094 02095 /** 02096 \brief Decode Priority 02097 \details Decodes an interrupt priority value with a given priority group to 02098 preemptive priority value and subpriority value. 02099 In case of a conflict between priority grouping and available 02100 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 02101 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 02102 \param [in] PriorityGroup Used priority group. 02103 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 02104 \param [out] pSubPriority Subpriority value (starting from 0). 02105 */ 02106 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 02107 { 02108 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02109 uint32_t PreemptPriorityBits; 02110 uint32_t SubPriorityBits; 02111 02112 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 02113 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 02114 02115 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 02116 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 02117 } 02118 02119 02120 /** 02121 \brief Set Interrupt Vector 02122 \details Sets an interrupt vector in SRAM based interrupt vector table. 02123 The interrupt number can be positive to specify a device specific interrupt, 02124 or negative to specify a processor exception. 02125 VTOR must been relocated to SRAM before. 02126 \param [in] IRQn Interrupt number 02127 \param [in] vector Address of interrupt handler function 02128 */ 02129 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 02130 { 02131 uint32_t *vectors = (uint32_t *)SCB->VTOR; 02132 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 02133 __DSB(); 02134 } 02135 02136 02137 /** 02138 \brief Get Interrupt Vector 02139 \details Reads an interrupt vector from interrupt vector table. 02140 The interrupt number can be positive to specify a device specific interrupt, 02141 or negative to specify a processor exception. 02142 \param [in] IRQn Interrupt number. 02143 \return Address of interrupt handler function 02144 */ 02145 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 02146 { 02147 uint32_t *vectors = (uint32_t *)SCB->VTOR; 02148 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 02149 } 02150 02151 02152 /** 02153 \brief System Reset 02154 \details Initiates a system reset request to reset the MCU. 02155 */ 02156 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 02157 { 02158 __DSB(); /* Ensure all outstanding memory accesses included 02159 buffered write are completed before reset */ 02160 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 02161 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 02162 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ 02163 __DSB(); /* Ensure completion of memory access */ 02164 02165 for(;;) /* wait until reset */ 02166 { 02167 __NOP(); 02168 } 02169 } 02170 02171 /*@} end of CMSIS_Core_NVICFunctions */ 02172 02173 02174 /* ########################## MPU functions #################################### */ 02175 02176 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 02177 02178 #include "mpu_armv7.h" 02179 02180 #endif 02181 02182 02183 /* ########################## FPU functions #################################### */ 02184 /** 02185 \ingroup CMSIS_Core_FunctionInterface 02186 \defgroup CMSIS_Core_FpuFunctions FPU Functions 02187 \brief Function that provides FPU type. 02188 @{ 02189 */ 02190 02191 /** 02192 \brief get FPU type 02193 \details returns the FPU type 02194 \returns 02195 - \b 0: No FPU 02196 - \b 1: Single precision FPU 02197 - \b 2: Double + Single precision FPU 02198 */ 02199 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 02200 { 02201 uint32_t mvfr0; 02202 02203 mvfr0 = SCB->MVFR0; 02204 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) 02205 { 02206 return 2U; /* Double + Single precision FPU */ 02207 } 02208 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) 02209 { 02210 return 1U; /* Single precision FPU */ 02211 } 02212 else 02213 { 02214 return 0U; /* No FPU */ 02215 } 02216 } 02217 02218 /*@} end of CMSIS_Core_FpuFunctions */ 02219 02220 02221 02222 /* ########################## Cache functions #################################### */ 02223 /** 02224 \ingroup CMSIS_Core_FunctionInterface 02225 \defgroup CMSIS_Core_CacheFunctions Cache Functions 02226 \brief Functions that configure Instruction and Data cache. 02227 @{ 02228 */ 02229 02230 /* Cache Size ID Register Macros */ 02231 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) 02232 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) 02233 02234 #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ 02235 #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ 02236 02237 /** 02238 \brief Enable I-Cache 02239 \details Turns on I-Cache 02240 */ 02241 __STATIC_FORCEINLINE void SCB_EnableICache (void) 02242 { 02243 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) 02244 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 02245 02246 __DSB(); 02247 __ISB(); 02248 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 02249 __DSB(); 02250 __ISB(); 02251 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 02252 __DSB(); 02253 __ISB(); 02254 #endif 02255 } 02256 02257 02258 /** 02259 \brief Disable I-Cache 02260 \details Turns off I-Cache 02261 */ 02262 __STATIC_FORCEINLINE void SCB_DisableICache (void) 02263 { 02264 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) 02265 __DSB(); 02266 __ISB(); 02267 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ 02268 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 02269 __DSB(); 02270 __ISB(); 02271 #endif 02272 } 02273 02274 02275 /** 02276 \brief Invalidate I-Cache 02277 \details Invalidates I-Cache 02278 */ 02279 __STATIC_FORCEINLINE void SCB_InvalidateICache (void) 02280 { 02281 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) 02282 __DSB(); 02283 __ISB(); 02284 SCB->ICIALLU = 0UL; 02285 __DSB(); 02286 __ISB(); 02287 #endif 02288 } 02289 02290 02291 /** 02292 \brief I-Cache Invalidate by address 02293 \details Invalidates I-Cache for the given address. 02294 I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. 02295 I-Cache memory blocks which are part of given address + given size are invalidated. 02296 \param[in] addr address 02297 \param[in] isize size of memory block (in number of bytes) 02298 */ 02299 __STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) 02300 { 02301 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) 02302 if ( isize > 0 ) { 02303 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); 02304 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; 02305 02306 __DSB(); 02307 02308 do { 02309 SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 02310 op_addr += __SCB_ICACHE_LINE_SIZE; 02311 op_size -= __SCB_ICACHE_LINE_SIZE; 02312 } while ( op_size > 0 ); 02313 02314 __DSB(); 02315 __ISB(); 02316 } 02317 #endif 02318 } 02319 02320 02321 /** 02322 \brief Enable D-Cache 02323 \details Turns on D-Cache 02324 */ 02325 __STATIC_FORCEINLINE void SCB_EnableDCache (void) 02326 { 02327 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02328 uint32_t ccsidr; 02329 uint32_t sets; 02330 uint32_t ways; 02331 02332 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 02333 02334 SCB->CSSELR = 0U; /* select Level 1 data cache */ 02335 __DSB(); 02336 02337 ccsidr = SCB->CCSIDR; 02338 02339 /* invalidate D-Cache */ 02340 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 02341 do { 02342 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 02343 do { 02344 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 02345 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 02346 #if defined ( __CC_ARM ) 02347 __schedule_barrier(); 02348 #endif 02349 } while (ways-- != 0U); 02350 } while(sets-- != 0U); 02351 __DSB(); 02352 02353 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 02354 02355 __DSB(); 02356 __ISB(); 02357 #endif 02358 } 02359 02360 02361 /** 02362 \brief Disable D-Cache 02363 \details Turns off D-Cache 02364 */ 02365 __STATIC_FORCEINLINE void SCB_DisableDCache (void) 02366 { 02367 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02368 uint32_t ccsidr; 02369 uint32_t sets; 02370 uint32_t ways; 02371 02372 SCB->CSSELR = 0U; /* select Level 1 data cache */ 02373 __DSB(); 02374 02375 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ 02376 __DSB(); 02377 02378 ccsidr = SCB->CCSIDR; 02379 02380 /* clean & invalidate D-Cache */ 02381 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 02382 do { 02383 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 02384 do { 02385 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | 02386 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); 02387 #if defined ( __CC_ARM ) 02388 __schedule_barrier(); 02389 #endif 02390 } while (ways-- != 0U); 02391 } while(sets-- != 0U); 02392 02393 __DSB(); 02394 __ISB(); 02395 #endif 02396 } 02397 02398 02399 /** 02400 \brief Invalidate D-Cache 02401 \details Invalidates D-Cache 02402 */ 02403 __STATIC_FORCEINLINE void SCB_InvalidateDCache (void) 02404 { 02405 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02406 uint32_t ccsidr; 02407 uint32_t sets; 02408 uint32_t ways; 02409 02410 SCB->CSSELR = 0U; /* select Level 1 data cache */ 02411 __DSB(); 02412 02413 ccsidr = SCB->CCSIDR; 02414 02415 /* invalidate D-Cache */ 02416 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 02417 do { 02418 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 02419 do { 02420 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 02421 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 02422 #if defined ( __CC_ARM ) 02423 __schedule_barrier(); 02424 #endif 02425 } while (ways-- != 0U); 02426 } while(sets-- != 0U); 02427 02428 __DSB(); 02429 __ISB(); 02430 #endif 02431 } 02432 02433 02434 /** 02435 \brief Clean D-Cache 02436 \details Cleans D-Cache 02437 */ 02438 __STATIC_FORCEINLINE void SCB_CleanDCache (void) 02439 { 02440 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02441 uint32_t ccsidr; 02442 uint32_t sets; 02443 uint32_t ways; 02444 02445 SCB->CSSELR = 0U; /* select Level 1 data cache */ 02446 __DSB(); 02447 02448 ccsidr = SCB->CCSIDR; 02449 02450 /* clean D-Cache */ 02451 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 02452 do { 02453 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 02454 do { 02455 SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | 02456 ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); 02457 #if defined ( __CC_ARM ) 02458 __schedule_barrier(); 02459 #endif 02460 } while (ways-- != 0U); 02461 } while(sets-- != 0U); 02462 02463 __DSB(); 02464 __ISB(); 02465 #endif 02466 } 02467 02468 02469 /** 02470 \brief Clean & Invalidate D-Cache 02471 \details Cleans and Invalidates D-Cache 02472 */ 02473 __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) 02474 { 02475 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02476 uint32_t ccsidr; 02477 uint32_t sets; 02478 uint32_t ways; 02479 02480 SCB->CSSELR = 0U; /* select Level 1 data cache */ 02481 __DSB(); 02482 02483 ccsidr = SCB->CCSIDR; 02484 02485 /* clean & invalidate D-Cache */ 02486 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 02487 do { 02488 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 02489 do { 02490 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | 02491 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); 02492 #if defined ( __CC_ARM ) 02493 __schedule_barrier(); 02494 #endif 02495 } while (ways-- != 0U); 02496 } while(sets-- != 0U); 02497 02498 __DSB(); 02499 __ISB(); 02500 #endif 02501 } 02502 02503 02504 /** 02505 \brief D-Cache Invalidate by address 02506 \details Invalidates D-Cache for the given address. 02507 D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. 02508 D-Cache memory blocks which are part of given address + given size are invalidated. 02509 \param[in] addr address 02510 \param[in] dsize size of memory block (in number of bytes) 02511 */ 02512 __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) 02513 { 02514 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02515 if ( dsize > 0 ) { 02516 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 02517 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 02518 02519 __DSB(); 02520 02521 do { 02522 SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 02523 op_addr += __SCB_DCACHE_LINE_SIZE; 02524 op_size -= __SCB_DCACHE_LINE_SIZE; 02525 } while ( op_size > 0 ); 02526 02527 __DSB(); 02528 __ISB(); 02529 } 02530 #endif 02531 } 02532 02533 02534 /** 02535 \brief D-Cache Clean by address 02536 \details Cleans D-Cache for the given address 02537 D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. 02538 D-Cache memory blocks which are part of given address + given size are cleaned. 02539 \param[in] addr address 02540 \param[in] dsize size of memory block (in number of bytes) 02541 */ 02542 __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) 02543 { 02544 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02545 if ( dsize > 0 ) { 02546 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 02547 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 02548 02549 __DSB(); 02550 02551 do { 02552 SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 02553 op_addr += __SCB_DCACHE_LINE_SIZE; 02554 op_size -= __SCB_DCACHE_LINE_SIZE; 02555 } while ( op_size > 0 ); 02556 02557 __DSB(); 02558 __ISB(); 02559 } 02560 #endif 02561 } 02562 02563 02564 /** 02565 \brief D-Cache Clean and Invalidate by address 02566 \details Cleans and invalidates D_Cache for the given address 02567 D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. 02568 D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. 02569 \param[in] addr address (aligned to 32-byte boundary) 02570 \param[in] dsize size of memory block (in number of bytes) 02571 */ 02572 __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) 02573 { 02574 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02575 if ( dsize > 0 ) { 02576 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 02577 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 02578 02579 __DSB(); 02580 02581 do { 02582 SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 02583 op_addr += __SCB_DCACHE_LINE_SIZE; 02584 op_size -= __SCB_DCACHE_LINE_SIZE; 02585 } while ( op_size > 0 ); 02586 02587 __DSB(); 02588 __ISB(); 02589 } 02590 #endif 02591 } 02592 02593 /*@} end of CMSIS_Core_CacheFunctions */ 02594 02595 02596 02597 /* ################################## SysTick function ############################################ */ 02598 /** 02599 \ingroup CMSIS_Core_FunctionInterface 02600 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 02601 \brief Functions that configure the System. 02602 @{ 02603 */ 02604 02605 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 02606 02607 /** 02608 \brief System Tick Configuration 02609 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 02610 Counter is in free running mode to generate periodic interrupts. 02611 \param [in] ticks Number of ticks between two interrupts. 02612 \return 0 Function succeeded. 02613 \return 1 Function failed. 02614 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 02615 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 02616 must contain a vendor-specific implementation of this function. 02617 */ 02618 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 02619 { 02620 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 02621 { 02622 return (1UL); /* Reload value impossible */ 02623 } 02624 02625 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 02626 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 02627 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 02628 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 02629 SysTick_CTRL_TICKINT_Msk | 02630 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 02631 return (0UL); /* Function successful */ 02632 } 02633 02634 #endif 02635 02636 /*@} end of CMSIS_Core_SysTickFunctions */ 02637 02638 02639 02640 /* ##################################### Debug In/Output function ########################################### */ 02641 /** 02642 \ingroup CMSIS_Core_FunctionInterface 02643 \defgroup CMSIS_core_DebugFunctions ITM Functions 02644 \brief Functions that access the ITM debug interface. 02645 @{ 02646 */ 02647 02648 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 02649 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 02650 02651 02652 /** 02653 \brief ITM Send Character 02654 \details Transmits a character via the ITM channel 0, and 02655 \li Just returns when no debugger is connected that has booked the output. 02656 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 02657 \param [in] ch Character to transmit. 02658 \returns Character to transmit. 02659 */ 02660 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 02661 { 02662 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 02663 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 02664 { 02665 while (ITM->PORT[0U].u32 == 0UL) 02666 { 02667 __NOP(); 02668 } 02669 ITM->PORT[0U].u8 = (uint8_t)ch; 02670 } 02671 return (ch); 02672 } 02673 02674 02675 /** 02676 \brief ITM Receive Character 02677 \details Inputs a character via the external variable \ref ITM_RxBuffer. 02678 \return Received character. 02679 \return -1 No character pending. 02680 */ 02681 __STATIC_INLINE int32_t ITM_ReceiveChar (void) 02682 { 02683 int32_t ch = -1; /* no character available */ 02684 02685 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) 02686 { 02687 ch = ITM_RxBuffer; 02688 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 02689 } 02690 02691 return (ch); 02692 } 02693 02694 02695 /** 02696 \brief ITM Check Character 02697 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 02698 \return 0 No character available. 02699 \return 1 Character available. 02700 */ 02701 __STATIC_INLINE int32_t ITM_CheckChar (void) 02702 { 02703 02704 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) 02705 { 02706 return (0); /* no character available */ 02707 } 02708 else 02709 { 02710 return (1); /* character available */ 02711 } 02712 } 02713 02714 /*@} end of CMSIS_core_DebugFunctions */ 02715 02716 02717 02718 02719 #ifdef __cplusplus 02720 } 02721 #endif 02722 02723 #endif /* __CORE_CM7_H_DEPENDANT */ 02724 02725 #endif /* __CMSIS_GENERIC */
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